sequential and combinational circuits

1. CS 506-Final Exam
ARMANDO M. SO III
SOLUTIONS:
I Design a circuit using JK-Flip Flop, construct a state table, state diagram for the following counters:
(20 points each)
JK FF Excitation table
Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
a.) 3-bit synchronous counter
State Table:
Qa Qb Qc Qa+ Qb+ Qc+ Ja Ka Jb Kb Jc Kc
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X x 1
0 1 0 0 1 1 0 X x 0 1 X
0 1 1 1 0 0 1 X x 1 x 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X x 1
1 1 0 1 1 1 X 0 x 0 1 X
1 1 1 0 0 0 X 1 x 1 x 1
K-maps:
BC
A 00 01 11 10
BC
A 00 01 11 10
0 1 0 x x X X
1 x x x X 1 1
Ja = QbQc Ka = QbQc
BC
A 00 01 11 10
BC
A 00 01 11 10
0 1 X x 0 x x 1
1 1 X x 1 x x 1
Jb = Qc Kb =Qc
BC
A 00 01 11 10
BC
A 00 01 11 10
0 1 x x 1 0 x 1 1 X
1 1 x x 1 1 x 1 1 X
Jc = 1 Kc = 1

2. State diagram: Circuit:
b.) 4-bit synchronous counter
State table:
Qa Qb Qc Qd Qa+ Qb+ Qc+ Qd+ Ja Ka Jb Kb Jc Kc Jd Kd
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1
K-maps:
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 00 X x X X
01 1 01 x X x X
11 X X X X 11 1
10 X X X X 10
Ja = QbQcQd Ka = QbQcQd
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 00 x x X x
01 x x X x 01 1
11 x x X x 11 1
10 1 10 x x X x
Jb = QcQd Kb = QcQd

3. CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 X x 00 x x 1
01 1 X x 01 x x 1
11 1 X x 11 x x 1
10 1 X x 10 x x 1
Jc = Qd Kc = Qd
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 x X 1 00 x 1 1 x
01 1 x X 1 01 x 1 1 x
11 1 x x 1 11 x 1 1 x
10 1 x X 1 10 x 1 1 x
Jd = 1 Kd = 1
State diagram:
Circuit:

4. c.) 4-bit synchronous up/down counter
State table:
Dir Qa Qb Qc Qd Qa+ Qb+ Qc+ Qd+ Ja Ka Jb Kb Jc Kc Jd Kd
0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
0 1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
0 1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
0 1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
0 1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
0 1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
0 1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
0 1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
0 1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1
1 0 0 0 0 1 1 1 1 1 X 1 X 1 X 1 X
1 0 0 0 1 0 0 0 0 0 X 0 X 0 X X 1
1 0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X
1 0 0 1 1 0 0 1 0 0 X 0 X X 0 X 1
1 0 1 0 0 0 0 1 1 0 X X 1 1 X 1 X
1 0 1 0 1 0 1 0 0 0 X X 0 0 X X 1
1 0 1 1 0 0 1 0 1 0 X X 0 X 1 1 X
1 0 1 1 1 0 1 1 0 0 X X 0 X 0 X 1
1 1 0 0 0 0 1 1 1 X 1 1 X 1 X 1 X
1 1 0 0 1 1 0 0 0 X 0 0 X 0 X X 1
1 1 0 1 0 1 0 0 1 X 0 0 X X 1 1 X
1 1 0 1 1 1 0 1 0 X 0 0 X X 0 X 1
1 1 1 0 0 1 0 1 1 X 0 X 1 1 X 1 X
1 1 1 0 1 1 1 0 0 X 0 X 0 0 X X 1
1 1 1 1 0 1 1 0 1 X 0 X 0 X 1 1 X
1 1 1 1 1 1 1 1 0 X 0 X 0 X 0 X 1

5. K-maps:
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 00 1
01 1 01
11 x x x X 11 X x x X
10 x X x x 10 X x x x
Ja = Dir’QbQcQd + DirQb’Qc’Qd’
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 x x x X 00 x x x X
01 x x X x 01 X x x x
11 1 11
10 10 1
Ka = Dir’QbQcQd + DirQb’Qc’Qd’
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 00 1
01 x x X x 01 x x X x
11 x x x x 11 x x x x
10 1 10 1
Jb = Dir’QcQd + DirQc’Qd’
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 x x X x 00 x x x X
01 1 01 1
11 1 11 1
10 x x x X 10 X x x X
Kb = Dir’QcQd + DirQc’Qd’
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 X x 00 1 x X
01 1 X X 01 1 x X
11 1 x x 11 1 x x
10 1 x x 10 1 x X
Jc = Dir’Qd + DirQd’
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 x x 1 00 x x 1
01 x x 1 01 x x 1
11 x x 1 11 x x 1
10 x x 1 10 x x 1
Kc = Dir’Qd + DirQd’

6. Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 1 x X 1 00 1 x X 1
01 1 x X 1 01 1 x X 1
11 1 x x 1 11 1 x X 1
10 1 x X 1 10 1 x X 1
Jd = 1
Dir = 0 Dir = 1
CD
AB 00 01 11 10
CD
AB 00 01 11 10
00 x 1 1 x 00 x 1 1 x
01 x 1 1 x 01 x 1 1 x
11 x 1 1 x 11 x 1 1 x
10 x 1 1 x 10 x 1 1 x
Kd = 1
State diagram:
Circuit:

7. d.) 4-bit asynchronous counter
Timing diagram (negative edge trigger):
Circuit:

8. II Construct a truth table for each counter in Part-I for a decoder that will match the 7-segment display
output. (20 points each)
For (a):
Input Segments
Symbol
Qa Qb Qc a b c d e f g
0 0 0 1 1 1 1 1 1 0 0
0 0 1 0 1 1 0 0 0 0 1
0 1 0 1 1 0 1 1 0 1 2
0 1 1 1 1 1 1 0 0 1 3
1 0 0 0 1 1 0 0 1 1 4
1 0 1 1 0 1 1 0 1 1 5
1 1 0 1 0 1 1 1 1 1 6
1 1 1 1 1 1 0 0 0 0 7
For (b), (c), and (d):
Input Segments
Symbol
Qa Qb Qc Qd a b c d e f g
0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 0 1 1 0 0 0 0 1
0 0 1 0 1 1 0 1 1 0 1 2
0 0 1 1 1 1 1 1 0 0 1 3
0 1 0 0 0 1 1 0 0 1 1 4
0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 0 1 1 1 1 1 6
0 1 1 1 1 1 1 0 0 0 0 7
1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 1 1 1 0 0 1 1 9
1 0 1 0 1 1 1 0 1 1 1 A
1 0 1 1 0 0 1 1 1 1 1 B
1 1 0 0 1 0 0 1 1 1 0 C
1 1 0 1 0 1 1 1 1 0 1 D
1 1 1 0 1 0 0 1 1 1 1 E
1 1 1 1 1 0 0 0 1 1 1 F
a
b
c
d
e
f
g

9. III Design a shift register using D-Flip flop in SIPO mode.(20 points)
4-bit D-FF SIPO shift register, with output bits Qa, Qb, Qc, Qd, ordered from MSB to LSB.
IV Design a buffer register using D-Flip flop in PIPO mode.(20 points)
4-bit D-FF PIPO buffer register, with input Data A, Data B, Data C, Data D, and output bits Qa, Qb, Qc, Qd.
Prepared by:
Engr.Pepito Cardoza Jr.
Instructor
Note: Show your solution
Deadline of submission Oct 18, 2017
@ CSIT Faculty Workroom 1:00 PM
“Good luck and God bless”