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Fault Tolerant and Online
Testability in Reversible Logic
           Synthesis

             Sajib Kumar Mitra
Department of Computer Science and Engineering
                 University of Dhaka
                sajibmitra.csedu@yahoo.com
Overview
• Background Study
    Reversible Logic
    Fault Tolerant Method
    Online Testability
• Online Testable Fault Tolerant Circuit
• Full Adder Circuit
    Existing Design
    Proposed Design
• Performance Analysis
• About Authors
• Conclusion
Reversible Logic
• Unique mapping between input and output
  vectors which governs to have same number
  of input-output lines of any reversible circuit
• Recovers heat dissipation unlikely irreversible
  logic and uses low power CMOS technology
• Feedback and Fan-out are not allowed
• Single unit able to compute more than one
  operation
Reversible Logic (cont…)




    An (n x n) Reversible Circuit
Reversible Logic (cont…)
                              I1        O1
                              I2        O2
                              I3        O3
                               .         .
                               .         .
                               .         .
                              In        On

                            Input
                             Input     Output
                                       Output
                            Vector
                             Vector    Vector
                                        Vector



Unique mapping of Reversible Circuit
Reversible Logic (cont…)




An (n x n) Reversible Circuit Architecture
Reversible Logic (cont…)




Reversible EX-OR operation and 2x2 Feynman Gate
Reversible Logic (cont…)




   Popular 3x3 Reversible Gates
Reversible Logic (cont…)




     4x4 Reversible Gates
Reversibility prevents Bit Loss
   but not able to detect Bit
 Error or Fault in Circuit
Fault Tolerant Method

What is the meaning of Bit Error?
 Bit Error means the alteration of the value of output bits
    because of internal fault of digital circuit.

                                           Input           Output
                                       A           B   A       A B
                                       0           0   0            0
                                       0           1   0            1
                                       1           0   1            1
                                       1           1   1            0



                Bit Error in Reversible Circuit
Fault Tolerant Method (cont…)

What is the meaning of Bit Error?
 Bit Error means the alteration of the value of output bits
    because of internal fault of digital circuit.

                                           Input           Output
                                       A           B   A       A B
                                       0           0   0            0
                                       0           1   0            1
                                       1           0   1            1
                                       1           1   1            0



                Bit Error in Reversible Circuit
Fault Tolerant Method (cont…)
Preserves same parity between Input and Output
  vectors over one to one mapping of reversible
  circuit




        Parity Preservation of Reversible Circuit
Fault Tolerant Method (cont…)
Let, Iv and Ov are input and output vectors of a
  reversible circuit, so the relation is Iv↔Ov.
But to be a Reversible Fault Tolerant circuit, itself
  must preserve following equation:
           I1 ⊕ I 2 ⊕ ⊕ I n = O1 ⊕ O2 ⊕ ⊕ On


where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}

                 Input Parity = Output Parity
Fault Tolerant Method (cont…)
Parity Preservation over reversibility between Input and
  Output vectors can be realized from the Truth Table of
  Fredkin Gate as shown below:
                                       Input           Output
                                  A     B      C   P     Q      R
                                   0     0     0   0     0      0
                                   0     0     1   0     0      1
                                   0     1     0   0     1      0
                                   0     1     1   0     1      1
                                   1     0     0   1     0      0
                                   1     0     1   1     1      0
        Fredkin Gate and
                                   1     1     0   1     0      1
    Corresponding Truth Table
                                   1     1     1   1     1      1
Fault Tolerant Method (cont…)
Now Verify the following equation:
  A ⊕ B ⊕C = P ⊕Q ⊕ R
                                    Input           Output
                                A    B      C   P     Q      R
                                0     0     0   0     0      0
                                0     0     1   0     0      1
                                0     1     0   0     1      0
                                0     1     1   0     1      1
                                1     0     0   1     0      0
                                1     0     1   1     1      0
        Fredkin Gate and
                                1     1     0   1     0      1
    Corresponding Truth Table
                                1     1     1   1     1      1
Fault Tolerant Method (cont…)
Verify the following equation:
        A ⊕ B ⊕C = P ⊕Q ⊕ R




   No Fault exist in Circuit   Fault exist in Circuit


              Fault detection of FRG gate
Fault Tolerant Method (cont…)
Finally Reversible Gate which preserves same parity
  between input and output vectors is called Fault
  Tolerant Gate or Parity Preserving Gate

  But the minimum dimension of Fault Tolerant gates is 3.
                         Why?

                                       Input     Output
                                         A         A’
                                         0         1
          NOT operation                  1         0



      1x1 Reversible Gate Never be a Fault Tolerant Gate
Fault Tolerant Method (cont…)
But the minimum dimension of Fault Tolerant gates is 3.
                       Why?




Input    Output   Input   Output   Input   Output   Input   Output
A    B   P   Q    A   B   P   Q    A   B   P   Q    A   B   P   Q
0    0   0   0    0   0   0   0    0   0   1   1    0   0   1   1
0    1   0   1    0   1   1   0    0   1   1   0    0   1   0   1
1    0   1   0    1   0   0   1    1   0   0   1    1   0   1   0
1    1   1   1    1   1   1   1    1   1   0   0    1   1   0   0


    2x2 Reversible Gates have no any significance as Fault
                       Tolerant Gate
Fault Tolerant Method (cont…)




  Existing 3x3 and 4x4 Fault Tolerant Gates
Online Testability
• Built-In Self Testing method
• Detects bit-error at outputs of any circuit in run
  time
• Reversible gates able to adopt testability feature
  by deducing output and corresponding input bits
• To be online testable an (n x n) reversible gates
  must preserve the following properties:

                On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1

where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}
Online Testability (cont…)
To be online testable an (n x n) reversible gates must
  have the following properties:
           On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1

                             Let ,
                            O3 = C ⊕U ⊕V
                              = C ⊕ A⊕ A⊕B = C ⊕B
                            ∴O3 ≠ W


           3x3 F2G is not online Testable Gates

But F2G can be Testable by deducing extra an input and
               corresponding output line.
Online Testability (cont…)
To be online testable an (n x n) reversible gates must
  have the following properties:
             On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1




 Let ,                 Testing Input         Testing Output

 O3 = P ⊕U ⊕V ⊕W
   = P ⊕ A ⊕ A ⊕ B ⊕ A ⊕C = P ⊕ A ⊕ B ⊕C
 ∴ O3 = Q
Online Testability (cont…)
                               Let ,
                               O3 = P ⊕U ⊕V ⊕W
                                 = 0 ⊕1 ⊕1 ⊕1 = 1
                               ∴ O3 = Q




Verification of Testable F2G at Runtime
Online Testability (cont…)
                               Let ,
                               O3 = P ⊕U ⊕V ⊕W
                                 = 0 ⊕1 ⊕1 ⊕ 0 = 0
                               ∴ O3 ≠ Q




Verification of Testable F2G at Runtime
Online Testability (cont…)



                                      Assignment :
                                      D =U
                                      E =V
                                      F =W
                                      R =0


Verification of Testable F2G at Runtime
Online Testability (cont…)




        If Q = S then " NO Bit Error"
           else " Bit Error"
Online Testability (cont…)
Online Testability (cont…)


Operational Inputs                               Operational Outputs

 Testing Inputs
(Constant Value)                                Testing Outputs




                     TRC is a Cascading Block not Gate
Online Testability (cont…)
   Testable R based on                               Testable Reversible Cell by
     following Law:                                 using Cascading Attachment
On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1




                                Conversion of nxn
                                 Reversible Gate
                                 into (n+2)x(n+2)
                                  reversible Cell
Reversible Fault Tolerant Full Adder
                Circuit
• Full Adder circuit produces Sum and Cout as
  following equations respectively:
              Sum = A ⊕ B ⊕ Cin
              Cout = ( A ⊕ B )Cin ⊕ AB

• Full Adder can be realized by using only one
  MTSG gate as follows:
Reversible Fault Tolerant Full Adder
                Circuit (cont…)

 Pros
   o Garbage = 2
   o Gate = 1
   o Quantum Cost = 6
 Cons
    Neither Fault Tolerant nor Online testable




         You have to make Fault Tolerant and Online
        Testable circuit by using fault Tolerant Gates. So
                           start now…
Existing Fault Tolerant Fault
         Tolerant Adder Circuit
By using MIG…




 Design is Fault tolerant but uses higher dimensional
  reversible Gates
 To make online testable, circuit has to increase an extra
  input-output line
Proposed Design of Fault Tolerant Full
              Adder
 Uses 3x3 Fault Tolerant gates
 Easily adoptable to online testable full adder
 Minimum number of Garbage, 3
 Preferable for Carry Look Ahead adder
Proposed Design of Online
Testable Fault Tolerant Full Adder
Performance Analysis
       Table 1: Comparison between proposed and
                    existing design

                 Total Gates
Fault Tolerant                  Total Quantum
 Full Adder      3x3     4x4   Garbage Cost
Proposed [b]      4       0        3          11
 Existing [a]     0       2        3          14
About Author
Sajib Kumar Mitra is an MS student of Dept. of Computer
Science and Engineering, University of Dhaka, Dhaka,
Bangladesh. His research interests include Electronics, Digital
Circuit Design, Logic Design, and Reversible Logic Synthesis.




Md. Faisal Hossain has completed his undergraduate from
Dept. of Computer Science and Engineering, University of
Dhaka, Dhaka, Bangladesh. His research interest includes
Logic Design, especially Reversible Logic Design.




 Ahsan Raja Chowdhury received his B.Sc .and MS degrees
in Computer science and Engineering from the University of
Dhaka, Bangladesh, in 2004 and 2006, respectively.
He worked with the Department of Computer Science and
Engineering, Northern University, Bangladesh, from 2004 to
2007 as faculty member. He is the faculty member of the
Department of Computer Science and Engineering,
Thanks To All

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Fault tolerant and online testability

  • 1. Fault Tolerant and Online Testability in Reversible Logic Synthesis Sajib Kumar Mitra Department of Computer Science and Engineering University of Dhaka sajibmitra.csedu@yahoo.com
  • 2. Overview • Background Study  Reversible Logic  Fault Tolerant Method  Online Testability • Online Testable Fault Tolerant Circuit • Full Adder Circuit  Existing Design  Proposed Design • Performance Analysis • About Authors • Conclusion
  • 3. Reversible Logic • Unique mapping between input and output vectors which governs to have same number of input-output lines of any reversible circuit • Recovers heat dissipation unlikely irreversible logic and uses low power CMOS technology • Feedback and Fan-out are not allowed • Single unit able to compute more than one operation
  • 4. Reversible Logic (cont…) An (n x n) Reversible Circuit
  • 5. Reversible Logic (cont…) I1 O1 I2 O2 I3 O3 . . . . . . In On Input Input Output Output Vector Vector Vector Vector Unique mapping of Reversible Circuit
  • 6. Reversible Logic (cont…) An (n x n) Reversible Circuit Architecture
  • 7. Reversible Logic (cont…) Reversible EX-OR operation and 2x2 Feynman Gate
  • 8. Reversible Logic (cont…) Popular 3x3 Reversible Gates
  • 9. Reversible Logic (cont…) 4x4 Reversible Gates
  • 10. Reversibility prevents Bit Loss but not able to detect Bit Error or Fault in Circuit
  • 11. Fault Tolerant Method What is the meaning of Bit Error? Bit Error means the alteration of the value of output bits because of internal fault of digital circuit. Input Output A B A A B 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 Bit Error in Reversible Circuit
  • 12. Fault Tolerant Method (cont…) What is the meaning of Bit Error? Bit Error means the alteration of the value of output bits because of internal fault of digital circuit. Input Output A B A A B 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 Bit Error in Reversible Circuit
  • 13. Fault Tolerant Method (cont…) Preserves same parity between Input and Output vectors over one to one mapping of reversible circuit Parity Preservation of Reversible Circuit
  • 14. Fault Tolerant Method (cont…) Let, Iv and Ov are input and output vectors of a reversible circuit, so the relation is Iv↔Ov. But to be a Reversible Fault Tolerant circuit, itself must preserve following equation: I1 ⊕ I 2 ⊕ ⊕ I n = O1 ⊕ O2 ⊕ ⊕ On where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On} Input Parity = Output Parity
  • 15. Fault Tolerant Method (cont…) Parity Preservation over reversibility between Input and Output vectors can be realized from the Truth Table of Fredkin Gate as shown below: Input Output A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 Fredkin Gate and 1 1 0 1 0 1 Corresponding Truth Table 1 1 1 1 1 1
  • 16. Fault Tolerant Method (cont…) Now Verify the following equation: A ⊕ B ⊕C = P ⊕Q ⊕ R Input Output A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 Fredkin Gate and 1 1 0 1 0 1 Corresponding Truth Table 1 1 1 1 1 1
  • 17. Fault Tolerant Method (cont…) Verify the following equation: A ⊕ B ⊕C = P ⊕Q ⊕ R No Fault exist in Circuit Fault exist in Circuit Fault detection of FRG gate
  • 18. Fault Tolerant Method (cont…) Finally Reversible Gate which preserves same parity between input and output vectors is called Fault Tolerant Gate or Parity Preserving Gate But the minimum dimension of Fault Tolerant gates is 3. Why? Input Output A A’ 0 1 NOT operation 1 0 1x1 Reversible Gate Never be a Fault Tolerant Gate
  • 19. Fault Tolerant Method (cont…) But the minimum dimension of Fault Tolerant gates is 3. Why? Input Output Input Output Input Output Input Output A B P Q A B P Q A B P Q A B P Q 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 2x2 Reversible Gates have no any significance as Fault Tolerant Gate
  • 20. Fault Tolerant Method (cont…) Existing 3x3 and 4x4 Fault Tolerant Gates
  • 21. Online Testability • Built-In Self Testing method • Detects bit-error at outputs of any circuit in run time • Reversible gates able to adopt testability feature by deducing output and corresponding input bits • To be online testable an (n x n) reversible gates must preserve the following properties: On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1 where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}
  • 22. Online Testability (cont…) To be online testable an (n x n) reversible gates must have the following properties: On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1 Let , O3 = C ⊕U ⊕V = C ⊕ A⊕ A⊕B = C ⊕B ∴O3 ≠ W 3x3 F2G is not online Testable Gates But F2G can be Testable by deducing extra an input and corresponding output line.
  • 23. Online Testability (cont…) To be online testable an (n x n) reversible gates must have the following properties: On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1 Let , Testing Input Testing Output O3 = P ⊕U ⊕V ⊕W = P ⊕ A ⊕ A ⊕ B ⊕ A ⊕C = P ⊕ A ⊕ B ⊕C ∴ O3 = Q
  • 24. Online Testability (cont…) Let , O3 = P ⊕U ⊕V ⊕W = 0 ⊕1 ⊕1 ⊕1 = 1 ∴ O3 = Q Verification of Testable F2G at Runtime
  • 25. Online Testability (cont…) Let , O3 = P ⊕U ⊕V ⊕W = 0 ⊕1 ⊕1 ⊕ 0 = 0 ∴ O3 ≠ Q Verification of Testable F2G at Runtime
  • 26. Online Testability (cont…) Assignment : D =U E =V F =W R =0 Verification of Testable F2G at Runtime
  • 27. Online Testability (cont…) If Q = S then " NO Bit Error" else " Bit Error"
  • 29. Online Testability (cont…) Operational Inputs Operational Outputs Testing Inputs (Constant Value) Testing Outputs TRC is a Cascading Block not Gate
  • 30. Online Testability (cont…) Testable R based on Testable Reversible Cell by following Law: using Cascading Attachment On = I n ⊕ O1 ⊕ O2 ⊕ ⊕ On −1 Conversion of nxn Reversible Gate into (n+2)x(n+2) reversible Cell
  • 31. Reversible Fault Tolerant Full Adder Circuit • Full Adder circuit produces Sum and Cout as following equations respectively: Sum = A ⊕ B ⊕ Cin Cout = ( A ⊕ B )Cin ⊕ AB • Full Adder can be realized by using only one MTSG gate as follows:
  • 32. Reversible Fault Tolerant Full Adder Circuit (cont…)  Pros o Garbage = 2 o Gate = 1 o Quantum Cost = 6  Cons  Neither Fault Tolerant nor Online testable You have to make Fault Tolerant and Online Testable circuit by using fault Tolerant Gates. So start now…
  • 33. Existing Fault Tolerant Fault Tolerant Adder Circuit By using MIG…  Design is Fault tolerant but uses higher dimensional reversible Gates  To make online testable, circuit has to increase an extra input-output line
  • 34. Proposed Design of Fault Tolerant Full Adder  Uses 3x3 Fault Tolerant gates  Easily adoptable to online testable full adder  Minimum number of Garbage, 3  Preferable for Carry Look Ahead adder
  • 35. Proposed Design of Online Testable Fault Tolerant Full Adder
  • 36. Performance Analysis Table 1: Comparison between proposed and existing design Total Gates Fault Tolerant Total Quantum Full Adder 3x3 4x4 Garbage Cost Proposed [b] 4 0 3 11 Existing [a] 0 2 3 14
  • 37. About Author Sajib Kumar Mitra is an MS student of Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interests include Electronics, Digital Circuit Design, Logic Design, and Reversible Logic Synthesis. Md. Faisal Hossain has completed his undergraduate from Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interest includes Logic Design, especially Reversible Logic Design. Ahsan Raja Chowdhury received his B.Sc .and MS degrees in Computer science and Engineering from the University of Dhaka, Bangladesh, in 2004 and 2006, respectively. He worked with the Department of Computer Science and Engineering, Northern University, Bangladesh, from 2004 to 2007 as faculty member. He is the faculty member of the Department of Computer Science and Engineering,