Net content in computer architecture

NET – SET Training
BY
PROF. GOPIKA S
DEPARTMENT OF COMPUTER SCIENCE
KRISTU JAYANTI COLLEGE, BENGALURU
Computer System Architecture

UGC NET Computer Science
Syllabus and Paper Pattern
Paper Marks Number of Questions
I 100 50 Questions all are Compulsory
II 200 100 Question all are Compulsory
NET CLASSES - COMPUTER SYSTEM ARCHITECTURE - GOPIKA S , KRISTU JAYANTI
COLLEGE

Computer Organization and Architecture
It has around 9% weightage in the GATE exam.
The questions are quite tricky in this subject, so there is a need of a lot of practice for
different types of questions.
Important topics from Computer System Architecture are listed below:
◦ Digital Logic Circuits and Components: Digital Computers, Logic Gates, Boolean Algebra, Map
Simplifications, Combinational Circuits, Flip-Flops, Sequential Circuits, Integrated Circuits,
Decoders, Multiplexers, Registers and Counters, Memory Unit.
◦ Data Representation: Data Types, Number Systems and Conversion, Complements, Fixed Point
Representation, Floating Point Representation, Error Detection Codes, Computer Arithmetic -
Addition, Subtraction, Multiplication and Division Algorithms.
◦ Register Transfer and Micro-operations
NET CLASSES - COMPUTER SYSTEM ARCHITECTURE - GOPIKA S , KRISTU JAYANTI COLLEGE

Basic Computer Organization and Design: Instruction Codes, Computer Registers, Computer Instructions,
Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input-Output, Interrupt.
Programming the Basic Computer: Machine Language, Assembly Language, Assembler, Program Loops,
Subroutines, Input-Output Programming.
Microprogrammed Control: Control Memory, Address Sequencing, Design of Control Unit.
Central Processing Unit: General Register Organization, Stack Organization, Instruction Formats, Addressing
Modes, RISC Computer, CISC Computer.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline, Vector
Processing Array Processors.
Input-Output Organization: Peripheral Devices, Input-Output Interface, Asynchronous Data Transfer, Modes of
Transfer, Priority Interrupt, DMA, Serial Communication.
Memory Hierarchy: Main Memory, Auxillary Memory, Associative Memory, Cache Memory, Virtual Memory,
Memory Management Hardware.
COLLEGE

Q1. In the following truth table, V = 1 if and only if the input is valid. What
function does the truth table represent?
A Priority encoder
B Decoder
C Multiplexer
D Demultiplexer
COLLEGE
Topic: Digital Logic Circuits and Components

Ans: Priority Encoder
Since there are more than one outputs and number of outputs is less than
inputs, it is a Priority encoder V=1 when input is valid and for priority encoder it
checks first high bit encountered. Except all are having at least one bit high and
‘x’ represents the “don’t care” as we have found a high bit already. So answer is
(A).

Q2.
A xy+x'y'
B x⊕y'
C x'⊕y
D x'⊕y'
Which one of the following expressions does NOT represent exclusive
NOR of x and y?
B and C

Questions from Data representation
Answer : C
Q3 . What is the binary representation
of the decimal number 45?
a. 101001
b. 111001
c . 101101
d. 101000
Q4.

Topic: ComputerArithmetic
Q5. Suppose A = 0111 and B = 1010. Will there be an end around carry if you
subtract B from A using 2’s compliment Arithmetic?
a. YES
b. NO
A 1 in Flip flop E indicates that A >= B and the number
in A is the correct result.
0 in E indicates that A < B. For this case it is necessary
to take the 2's complement of the value in A.
The operation can be done with one micro-operation
A = A' +1
Ans B

Q6. Consider two 8 bit numbers with values R1 = 56(in hexadecimal)
and R2 = 27 in hexadecimal. What will be value of R1-R2?
A. 29
B.2D
C. 2E
D.2F
Answer D
5 6 –
2 7
_________
2 F

Topic: Digital Logic Circuits and Components
Answer a
Q6.

Topic: Memory Management - Cache
Q7. More than one word are put in one cache block to
A. Exploit the temporal locality of reference in a program
B. Exploit the spatial locality of reference in a program
C. Reduce the miss penalty
D. None of the above
GATE-CS
Answer : B

Topic: Basic Computer Organization and Design
Q8. Suppose a processor does not have any stack pointer register. Which of the following
statements is true ?
A. It cannot have subroutine call instruction
B. It can have subroutine call instruction, but no nested subroutine calls.
C. Nested subroutine calls are possible, but interrupts are not.
D. All sequences of subroutine calls and also interrupts are possible
GATE2001-1.10, UGCNET-Dec2012-III: 36
Answer : A

Topic : Digital Logic
Q9. The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is
a. m2 + m4 + m6 + m7
b. m0 + m1 + m3 + m5
c. m0 + m1 + m6 + m7
d. m2 + m3 + m4 + m5
GATE CS 2010
Answer : A

Topic : Memory Management
Q10. How many minimum number of physical pins are required
for a 1M x 8 memory chip.
a) 31
b) 32
c) 28
d) 36
Answer : b, 32
1 M = 2 pow 20 - Hence 20 Address lines
+ 8 Data lines
+ CS ( Chip Select)
+ R/W’ Signal
+ Powersupply (Vcc, GND)

Memory – Mapping schemes
Q11. In set associative mapping, if the number of blocks in a set is
reduced to one, that will become
a) Direct mapping
b) Fully associative mapping
c) 2-way set associative mapping
d) None of the above
Answer : a ) direct mapping

Topic : Memory management
Q12. After the entire block is loaded into the cache from main memory, this
word may be sent to the processor also. This approach is called
a) Early restart
b) Write through
c) Direct mapping
d) Associative mapping
Ans: a, Early restart

Q13. Consider a computer that has the following parameters. Access times to the cache and
main memory are τ and 10τ , respectively. When a cache miss occurs, a block of 16 words
is transferred from the main memory to the cache. It takes 10τ to transfer the first word of
the block, and the remaining words are transferred at the rate of one word every τ seconds.
Find out the miss penalty in this computer.
a) 25T
b) 26T
c) 27T
d) 11T
Ans: c, 27T
27 τ = 1τ (Cache access) + 10 τ(For transfer of
the first word from cache)+15 τ( for remaining) +
1 τ (t transfer the one requested word to processor)

NET and GATE
Q14. Consider a system with 2 level cache memory with access times of 10ns
and 80ns respectively. If the hit rates are 95% and 75% respectively in the two
caches and the memory access time is 250ns, what is the average access time?
a) 10.875 ns
b) 11.875 ns
c) 15.625 ns
d) 15.875 ns
Ans : c, 15.625ns
= 0.95 X10 + 0.05 X0.75x80 + 0.05 X0.25 X 250
= 9.5 + 3 + 3.125
= 15.625.

Explanation:
First, the system will look in cache 1.
If it is not found in cache 1, then cache 2 and then further in main memory (if not in cache 2 also).
The average access time would take into consideration success in cache 1, failure in cache 1 but
success in cache 2, failure in both the caches and success in main memory.
Average access time = [H1*T1]+[(1-H1)*H2*T2]+[(1-H1)(1-H2)*Hm*Tm]
where,
H1 = Hit rate of level 1 cache = 0.95
T1 = Access time for level 1 cache = 10 ns
H2 = Hit rate of level 2 cache = 0.75
T2 = Access time for level 2 cache = 80 ns
Hm = Hit rate of Main Memory = 1
Tm = Access time for Main Memory = 250 ns
= 0.95 X10ns + 0.05 X0.75x80ns+ 0.05 X0.25 X 250ns
= 9.5 + 3 + 3.125
= 15.625ns

Topic : Instructions, Addressing mode
Q15 . Consider the following assembly language program for a hypothetical processor. A,B
and C are 8 bit registers. The meanings of various instructions are shown as comments.
MOV B, # 0 ; B ← 0
MOV C, # 8 ; C ← 8
Z: CMP C, # 0 ; compare C with 0
JZ X ; jump to X if zero flag is set
SUB C, # 1 ; C ← C−1
RRC A, # 1 ;
JC Y ; jump to Y if carry flag is set
JMP Z ; jump to Z
Y: ADD B, # 1 ; B ← B+1
JMP Z ; jump to Z
X:
If the initial value of register A is A0, the value of
register B after the program execution will be
A. the number of 0 bits in A0
B. the number of 1 bits in A0
C. A0
D. 8
NET Question
Right rotate A through carry by one
bit. If the initial values of A and the
carry flag are a7 .......a0 and c0
respectively, their values after the
execution of this instruction will be
c0 a7 .....a1 and a0 respectively.

Topic : Memory – I/O Data transfer
Q16. In the following sentences, which one is correct related to
programmed I/O data transfer.
a) Continuous polling cycle is required
b) Stack need to be initialized
c) Implemented with the support of interrupts
d) All of the above
Ans a

Q17. A computer has a memory unit of 64K x 16 and a cache memory of 1K
words. The cache uses direct mapping with a block size of four words. How
many bits are there in tag, block and word fields of address.
a) 6, 8, 2
b) 8, 6, 4
c) 8, 8, 2
d) 6, 8, 4
Ans: a, 6, 8, 2

MAIN
MEMORY
64K X 16
CACHE
MEMORY
1K
• Data is transferred as blocks of size 4 words.
• Both MM and CM are divided into blocks of 4 words
• Thus we get 256 Blocks in CM
• For getting the location of a block in CM, we need 8 bits and that is the lock field value.
64 K = 2 pow 16
Hence, 2 pow 14 blocks are there
And a 14 bit address is required to
access a block.
6 8 2
Tag block byte

Q18. Compared to static RAM, dynamic memory has
a) Higher package density and low power consumption
b) Lower package density and higher power consumption
c) Lower package density and lower power consumption
Ans: a, Higher package density and low power consumption

Q19 How many (512K x 1 bit) RAM chips are required to
construct 1G byte memory.
a) 2048
b) 16384
c) 4096
d) 32768
Ans: b, 16384

20. Cycle stealing mode is used by
a) DMA controller
b) Interrupt controller
c) USB hub
Ans: a, DMA controller

Q21. The binary addresses that the processor issues for either instructions or
data are called
a) Physical address
b) Mirror address
c) Virtual address
Ans: c , Virtual Address

Q22. Consider the following circuit involving three D-type flip-
flops used in a certain type of counter configuration. If at some
instance prior to the occurrence of the clock edge, P, Q and R
have a value 0, 1 and 0 respectively, what shall be the value of
PQR after the clock edge?
GATECS2011
Answer 011

Q23. Which of the following addressing modes are suitable for program relocation at run
time?
1. Absolute addressing
2. Based addressing
3. Relative addressing
4. Indirect addressing
A. 1 and 4
B. 1 and 2
C. 2 and 3
D. 1,2 and 4

Q24.FAN IN of a component A is defined as
a. Number of components that can call or pass control to component A
b. Number of components that are called by component A
c. Number of components related to component A
d. Number of components dependent on component A
Ans A

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a
unit delay, the total delay of the multiplier is
A. Θ(1)
B. Θ(logn)
C. Θ(n)
D. Θ(n2)

Q25.
In serial data transmission, every byte of data is padded with a ‘0’ in the beginning and one or
two ‘1’s at the end of byte because
A. Receiver is to be synchronized for byte reception
B. Receiver recovers lost ‘0’s and ‘1’ from these padded bits
C. Padded bits are useful in parity computation.
D. None of the above
NET CLASSES - COMPTER SYSTEM ARCHITECTURE - GOPIKA S , KRISTU
JAYANTI COLLEGE

Which of the following statements are true?
I. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
II. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
III. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
IV. A device that accepts the value of a Boolean variable as input and produces its complement is called an
inverter.
a. I & II
b. Il & III Ans D
c. I, II, lll
d. I, III & IV

A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the
following is a legal program counter (all values in decimal)?
A. 400
B. 500
C. 600
D. 700

8.
A processor needs software interrupt to
A. Test the interrupt system of the processor.
B. Implement co-routines.
C. Obtain system services which need execution of privileged instructions.
D. Return from subroutine.

The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is
a. m2 + m4 + m6 + m7
b. m0 + m1 + m3 + m5
c. m0 + m1 + m6 + m7 GATE CS 2010
d. m2 + m3 + m4 + m5
NET CLASSES - COMPUTER SYSTEM ARCHITECTURE - GOPIKA S , KRISTU
JAYANTI COLLEGE
Ans a

In which addressing mode, the effective address of the operand is generated by adding a constant
value to the contents of register ?
a.
Absolute
b.
Indirect
c.
Immediate
d.
Index
JAYANTI COLLEGE
Ans D

FAN IN of a component A is defined as
a.
Number of components that can call or pass control to component A
b.
Number of components that are called by component A
c.
Number of components related to component A Ans A
d.
Number of components dependent on component A
JAYANTI COLLEGE

JAYANTI COLLEGE

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