1. Characterization of 1200V SiC Power
MOSFETs
Eddie Benitez-Jones
University of New Mexico
Dr. Paul Chow, Collin Hitchcock
ABSTRACT
In this study, several samples of TO-247 packaged, modern (soon-to-be
commercially available) 1200V, 20-30A rated 4H-SiC power MOSFETs
were characterized to compare and contrast the devices manufactured by
different vendors. By performing static characteristic tests on the devices,
basic device performance of DC characteristics (current-voltage) can be
used to compare the device functionality. Experimental results obtained
from the device models show the candidate with higher maturity in the
research process.

2. 1
1
INTRODUCTION
ower semiconductor devices are designed to handle significantly higher power levels than
ordinary Silicon devices to control the energy transfer of electrical and electronic systems.
There is currently a high demand of Power MOSFETs for applications to control medium
voltage motor drives, flexible AC transmission systems, high voltage DC systems and hybrid
electric vehicles. These applications require higher voltage breakdown capability, high power
density and functionality at high temperatures [1]. Silicon-based power semiconductor devices
have dominated these applications, however the devices have essentially reached their limitations
due to material properties such as low bandgap energy, small critical electric field, low thermal
conductivity, and switching frequency limitations [2]. Silicon Carbide is a semiconductor with
material properties favorable for power transistor applications. As you can see from Table 1, the
critical field of SiC is 10 times that of Si. This means that an SiC device blocking the same
voltage as an Si device can be 10 times smaller. This reduces the ON resistance, which also
reduces the energy losses, while increasing the power density [3]. Another benefit in using SiC is
the wide bandgap of the semiconductor, which results in a much lower leakage current and
higher operating temperatures. This allows the power electronics industry to create high power
applications that are more efficient.
The power transistors used in this study are planar vertical MOSFETs, as seen in Figure 1, with
the source and drain on opposite sides of the wafer to support higher voltage and current. The
planar MOSFET is beneficial for higher voltage ratings, since the on resistance in this structure
is dominated by the drift region resistance and high cell density is not beneficial [4].
PROCEDURE/METHODOLOGY
The basic methodology used for this study can be seen in Figure 2, where a
flowchart summarizes the following:
 Review Literature- It is necessary to review literature over the study that was
performed in order to get a good understanding of the device physics and proper
procedure for characteristic experiments. This literature included papers
reviewing basic power MOSFET structure and wide band gap semiconductor
characterization.
 Design the Study- We performed static characterization experiments, the most
basic evaluation of performance for power semiconductors. DC characterization
experiments included output characterization, ON-state resistance, gate-source
leakage current, threshold voltage measurement, breakdown voltage.
 Perform Experiment- Measurements were taken while the device was inside a
Delta 9023 oven for characterization under varied temperatures. The drain and
source had two wires soldered onto each terminal to take advantage of the four
terminal Kelvin sensing capabilities of the Tektronix 371A Curve Tracer and
P

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compensate for the losses within the resistance of the connecting wires. Prior to
conducting the experiment on samples from the vendors, the experiment was
performed on an Si power MOSFET (IRFP 440) & values were compared to the
data sheet to ensure a proper set up.
Characterization experiments were taken using four measuring equipment
available at RPI in CII 4108 and CII 4208. The four equipment included:
Tektronix 371A High-Power Curve Tracer: Performs DC parametric
characterization on a wide variety of power semiconductors including MOSFETs.
The pulsed high-current collector mode provides output current greater than 400
amps peak for testing On-Characteristics. It also permits high-power testing up to
3,000 W [5].
Tektronix 370A Programmable Curve Tracer: Performs DC parametric
characterization of semiconductors including MOSFETs. It is a versatile
workhorse in many labs and production stations with up to 20A/2000V sourcing
capability [5].
Delta Design Delta 9023 Oven: Offers a wide choice of temperature ranges and
capacities [6].
Hewlett Packard 4155A Semiconductor Parameter Analyzer: Electronic
instrument for measuring and analyzing characteristics of semiconductor devices
with a resolution of 0.2µV [7].
o Output Characteristics were extracted from the MOSFET by using
Tektronix 371A High Power Curve Tracer. This test is drain current (ID) vs
drain-source voltage (VDS). It is measured at different gate voltages (VGS).
The raw data I have taken takes 6 steps of gate voltages from VGS=0 to
VGS=25 in 5V intervals.
o ON-State Resistance RDS(on) was calculated by taking the slope of the
output characteristic curve at VGS=20V, ID=20A.
o Gate-Source Leakage Current (IGSS) was extracted using Tektronix 370A
Programmable Curve Tracer at VGS=20V, VDS=0V.
o Threshold Voltage (VTH) was extracted using Hewlett Packard 4155A
Semiconductor Parameter Analyzer and the Linear Extrapolation method
at VDS=VGS, ID=10mA.
o Breakdown Voltage (VBR(DSS)) was extracted using Tektronix 370A
Programmable Curve Tracer at VGS=0V, ID=250µA.
o
 Data Analysis- Data from the experiments was saved and converted into a format
which could be used in excel. The raw data was compiled into appropriate graphs
which would be used for presentation.

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3
 Report the Study- The work was presented in weekly meetings scheduled with
Prof. Chow and his research group. Bi-weekly research meetings were scheduled
with the vendor which sponsored our research to present the results of the devices.
DISCUSSION
The following experiments have been taken at varied temperature measurements ranging from -
196ºC to 150ºC. They include the following critical temperature points: -196 ºC (Liquid
Nitrogen), -129 ºC (melting point of 1-Propanol), -77 ºC (Dry Ice), -55 ºC (Standard Low
temperature datasheet measurement), 25 ºC (Room Temperature), 100 ºC and 150 ºC (Standard
High temperature datasheet measurements).
Output Characteristic Curves
The output characteristic curves of this experiment (IDS vs VDS) were measured at different gate
voltages VGS from 0V to 25V in 5V step intervals. By sweeping the gate voltages, we are able to
determine when the transistor turns on, and at what mode of operation it is for a given VDS.
Figures 3 and 4 display sample measurements of Output Characteristic Curves from two different
vendors at a gate-source voltage VGS=25V, with temperature measurements varying from -196ºC
to 150ºC.
As you can see from the Figures 3 and 4, both vendors demonstrate pentode-like1
I-V
characteristics for measurements taken at temperatures less than or equal to -129ºC, and triode-
like I-V characteristics at the extremely low temperature of -196 ºC [8].
On-State Resistance RDS(on)
On-State Resistance RDS(on) is a powerful and critical parameter of the device, since it is what
determines the conduction power dissipation. As you can see from Figure 5, the structure of the
power DMOSFET includes eight internal resistances between the gate and the source when the
device is turned on. Therefore, RDS(on)=RCS+ RN
+
+ RCH+ RA+ RJFET+ RD+ RSUB+ RCS (definition
of each resistance can be seen at the end of the paper)2
[2]. In this experiment, RDS(on) is
extracted from the output characteristic curve, by taking the slope of the curve at IDS=20A and
VGS=20V to remain consistent with datasheet parameters specified by the vendors. Figure 6 is a
representation of RDS(on) values for both vendors, normalized to the room temperature
measurement from each sample. Both vendors show a higher on-state resistance at either extreme
temperature measurement, nearly tripling the normalized value of room temperature, while
giving the minimum resistance from 0ºC to room temperature. The high temperature
characteristic is due to the decreasing carrier mobility under the MOS gate.

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As the device is scaled down to smaller dimensions, RN
+
, RCH, and RCS are reduced significantly,
since a larger number of individual unit cells can be packaged in some silicon area. In contrast,
RJFET suffers from a “JFET”-effect, where current is forced to flow in a narrow n-region by the
adjacent P-body region [4]. RDS(on) has an initial decrease as VGS increases above VTH, which
turns the device on. This happens, because RCH and RA decrease as VGS is increased. However, a
further increase in VGS will only decrease RDS(on) to a certain region where the resistance begins
to flattens out due to the channel being fully turned on and then the MOSFET resistance will be
limited the other resistance components [4].
Breakdown Voltage
The drain source breakdown voltage is a parameter used for the evaluation of the device’s
blocking capability. BVDSS of a power MOSFET is defined as the voltage where the reverse-
biased body-drift diode breaks down and significant current starts to flow between the source and
drain by an avalanche multiplication [9]. When a drain source voltage below the BVDSS is
applied, and bias below threshold is placed on the gate, no channel will form under the gate at
the surface, and the drain voltage will be entirely supported by the reverse-biased body-drift p-n
junction. The two related phenomena which typically occur in devices during breakdown are
punch-through3
and reach-through4
[9]. Tradeoffs can be made between decreasing RDS(on),
which requires shorter channel lengths and punch-through avoidance, which requires longer
channel lengths. BVDSS is typically measured at the voltage which produces 250µA of drain
leakage current. The results shown in figures 7 and 8 show breakdown as a function of
temperature for the two vendors. Vendor A shows a premature breakdown of 1200V at -196ºC,
with minimal punch through phenomenon for temperatures higher than -126ºC, and snap back
characteristics for -126 ºC and -196ºC. Vendor B demonstrates larger punch through
phenomenon than vendor A for temperatures higher than -196 ºC, and a premature breakdown at
1044V for -196 ºC.
Leakage Current (IDSS)
The drain source leakage current is another parameter used to evaluate the device’s blocking
capability. It is typically measured with the gate and source terminals shorted to ground,
(VGS=0V) and a VDS value at the device’s rated breakdown voltage, which is 1200V in this study.
Figure 9 is a normalized plot graph representing the leakage current vs temperature for each
vendor. Leakage current seems to multiply itself three to five times larger at high temperature
measurements. An oddity within this graph is the temperature measurement of -129ºC. This
drastic increase in leakage may have been due to the procedure the MOSFET was tested at to
gather data at this temperature. The procedure used to take measurements at this temperature
required that the MOSFET be immersed in a mixture of solid and liquid phase 1-Propanol .
Although precautions were taken to avoid immersing the device leads in the 1-Propanol, it is
probable that high leakage at this measurement was due to conduction between the source and
drain leads through the 1-Propanol. The MSDS for 1-Propanol indicates that it has a high
electrical conductivity in liquid state [10]. The use of 1-Propanol was avoided when testing

6. 5
5
devices from vendor B. Although leakage seems to rise for both vendors as temperature is
decreased, it has a more drastic increase for vendor A than that of vendor B.
Voltage Threshold (VTH)
The voltage threshold (VTH) of a device is defined to be the minimum gate bias which can form a
conducting channel between the source and drain. The method I have used to extract the
threshold voltage measurements from each device is known as the “Linear Extrapolation
Method” [11]. This method is the simplest and most commonly used. Using the parameter
analyzer, you begin by taking measurements for IDS vs VDS to recognize when the transistor is in
linear mode of operation. From this measurement I chose a VD value of 50mV, which puts the
transistor in the “Linear” region. Next, the transconductance5
(blue) is extracted by taking the
derivative of the IDS vs VGS curve (green). Finally, a tangent line is drawn on the IDS vs VGS curve
at the maximum transconductance point. This procedure can more easily be seen in Figures 10
and 11. Although both devices have an absolute maximum gate-source drive between -
10V<VGS<25V, the voltage threshold for vendor A is 3.36V, while vendor B is 2.25V. VGS(TH) is a
parameter which can be changed based on the gate oxide thickness and doping concentration of
the channel.
CONCLUSIONS
This study presented the static characterization of the TO-247 packaged, modern 1200V, 20-30A
rated 4H-SiC power MOSFETs, including output characterization, on-state resistance,
breakdown voltage, leakage current, and threshold voltage characterization. The static
characterization results as seen in Table 2 show SiC MOSFETs superiority in blocking higher
voltage while still keeping a very low on-resistance value. Although vendor A is nearing maturity
of low IDSS value as the IRFP 440 Si power MOSFET, further research is necessary to improve
this value within competing values of the mature Si transistor. Vendor A shows comparable
results to vendor B, however the maturity is higher in vendor A for every characterization
experiment.
FUTURE WORK
For an enhanced characterization of the devices, additional testing must be performed to include
characterization in gate capacitance, package stray inductance, device switching, and device
modeling. Gate capacitance (C-V) experiments will show characterization in accumulation,
depletion, and strong inversion regions. Package stray inductance measurements will show stray
impedances introduced by the package. Device switching measurements will give a better
understanding of the device switching behavior. Device modeling will make the model adoptable
in system level simulations [2].

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REFERENCES
[1]R. Fu, "Modeling of SiC Pwer Semiconductor Devices For Switching Converter
Applications", Doctor of Philosophy in Electrical Engineering, University of South
Carolina, 2013.
[2]X. Fang, "Characterization and Modeling of SiC Power MOSFETs", Masters, Ohio State
University, 2012.
[3]A. Mahajan, "Characterization of Wide Band Gap Power Semiconductor Devices", Master of
Science Electrical Engineering, University of North Carolina, 2016.
[4]"Power MOSFET Basics", ALPHA and OMEGA SEMICONDUCTOR, 2016.
[5]370A and 371A Digital Storage Curve Tracers, 1st ed. Tektronix Inc, 1996.
[6]Environmental Test Chambers, 1st ed. Delta Design Inc., 2016.
[7]C. Takakura, Parameter Analyzer, 1st ed. Tokyo: Yokogawa-Hewlett-Packard, Ltd, 1993.
[8]S. Chowdhury, C. Hitchcock and T. Chow, "Understanding the behavior of commercial
1200V SiC power MOSFETs at cryogenic temperatures", Abstract, ECSCRM, Halkidiki,
Greece, Sept. 25-29, 2015.
[9]V. Barkhordarian, Power MOSFET Basics, 1st ed. International Rectifier, 2016.
[10]MATERIAL SAFETY DATA SHEET 1-PROPANOL, 1st ed. CALEDON LABORATORY
CHEMICALS, 2016.
[11]L. Dobrescu, "Threshold Voltage Extraction Methods for MOS Transistors", University of
Bucharest, 2016.
[12]Intechopen.com, 2016. [Online]. Available:
http://www.intechopen.com/source/html/49015/media/fig5.png. [Accessed: 16- Jul- 2016].

8. 7
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TABLES
Parameter Silicon 4H-SiC
Band Gap (eV) 1.12 3.26
Critical Field
(MV/cm)
0.23 2.20
Electron Mobility
(Cm^2/V.s)
1400 950.0
Permittivity 11.8 9.0
Thermal
Conductivity
(W/cm.K)
1.5 1.3
Table 1: Material Properties for Si and SiC [4]
IRFP 440 (Si) Vendor A (SiC) Vendor B (SiC) Notes
RDS(on) (mΩ) 775 53.4 96.7 T=25ºC, ID=20A,
VGS=20V
IDSS (µA) 0.008 0.064 4.810 T=25ºC,
VDS=1200V,
VGS=0V
BVDSS (V) 574.0 1540 1462 T=25ºC,
ID=250µA
VGS(TH) (V) 3.150 3.356 1.847 VGS=VGD, Linear
Extrapolation
Method
Table 2: Summary of results, comparing Si to SiC power MOSFETs.

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FIGURES
Figure 1: Cross section of a planar power MOSFET structured device [12].
Figure 2: Methodology Flow Chart.
Review
Literature to get
Familiar with
Research Topic
Design the Study and
Develop Methods
Perform Experiment
and Collect Data
Data
Analysis
Report the Study and
Disseminate the Results

10. 9
9
0
5
10
15
20
25
30
0 2 4 6
Id(A)
Vds (V)
Vendor B Output I-V (VGS=25V)
-196
-129
-77
-55
0
25
100
150
Figures 3 and 4: Output characteristic curves at VGS=25V at varied temperatures for vendors A and B.
Figure 5: Illustration of internal resistances for a planar power MOSFET structured device [1].
0
5
10
15
20
25
30
0 2 4 6
Id(A)
Vds (V)
Vendor A Output I-V (VGS=25V)
-196
-129
-77
-55
0
25
100
150
Temperature (ºC)Temperature (ºC)

11. C
0
0.5
1
1.5
2
2.5
3
-200 -150 -100 -50 0 50 100 150
NormalizedtoRTValue
Temperature (ºC)
On Resistance Comparison
Vendor B (94.3mΩ)
Vendor A (53.4mΩ)
0
50
100
150
200
250
0 500 1000
Ids(µA)
Vds (V)
Vendor B Breakdown IV (Vgs = 0)
-196
-129
-77
-55
0
25
100
150
0
50
100
150
200
250
0 500 1000 1500
Id(µA)
Vds (V)
Vendor A Breakdown IV (Vgs = 0)
-196
-126
-77
-55
0
25
100
150
Figure 6: Comparison of vendors A and B on-state resistance varied temperature measurements
normalized at room temperature.
Figures 7 and 8: Breakdown voltage with VGS=0V at varied temperatures for vendors A and B.
1044V
Temperature (ºC) Temperature (ºC)

12. 11
11
0
1
2
3
4
5
6
-200 -150 -100 -50 0 50 100 150 200
NormalizedtoRTValue
Temperature (ºC)
Leakage current (µA) (Vds=1200V)
Vendor B (4.810µA)
Vendor A (0.064µA)
0
5
10
15
20
25
30
35
40
45
50
0 2 4 6 8 10
Current(mA)
Vg (V)
Vendor A Threshold Voltage
Intercept: 3.36V
𝑔 𝑚
𝐼 𝐷 𝑣𝑠 𝑉𝐺
0
5
10
15
20
25
30
35
40
45
50
0 2 4 6 8 10
Current(mA)
Vg (V)
Vendor B Threshold Voltage
Intercept: 2.25V
𝑔 𝑚
𝐼 𝐷 𝑣𝑠 𝑉𝐺
Figure 9: Comparison of vendors A and B leakage current at varied temperature measurements
normalized to room temperature taken at VDS=1200V.
Figures 10 and 11: Threshold voltage extracted using the “Linear Extrapolation Method” for vendors A and B.

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ACKNOWLEDGMENT
I would like to take this opportunity to express my sincere appreciation to my advisor, Dr. Paul
Chow for his guidance and advice, and for picking me to be part of his research group this
summer. I would also like to thank Collin Hitchcock for all of the help, knowledge, and time he
spent on the training sessions viral to the study to get results using the instrumentation in the
labs. I am also thankful to Zhibo Guo for his guidance of experimental measurements and
assistance in collecting experimental data. I am thankful to all of Dr. Chow’s research group, I
was able to learn or get help from every person involved within the group.
This memorable experience would not have been possible without the financial support of the
NSF, and I am thankful for the opportunity they gave me to be here for the program.
Terminology
pentode-like1
: An initial linear regime at low drain voltages followed by drain current saturation
at higher drain voltages [8].
Resistance parameters2
, RCS: Resistance of the source to contact interaction, RN
+
: Source
resistance, RCH: Channel resistance, RA: Accumulation resistance, RJFET: JFET resistance, RD:
Drift region resistance, RSUB: Substrate resistance, RCS: Resistance of the drain to contact
interaction.
Punch-through3
: This provides a current path between source and drain and causes a soft
breakdown characteristic [9].
Reach-through4
: This phenomenon occurs when the depletion region on the drift side of the
body-drift p-n junction reaches the epilayer-substrate interface before avalanching takes place in
the epi. Once the depletion edge enters the high carrier concentration substrate, a further increase
in drain voltage will cause the electric field to quickly reach the critical value of 2E5
𝑉
𝑐𝑚
where
avalanching begins [9].
Transconductance5
: (gm) is the gain of the MOSFETs, and it is influenced by gate width, channel
length, mobility, and gate capacitance through the following equation. g 𝑚 =
µnCoxW
LCH
[4].