2. September 2015 z IEEE Power Electronics Magazine 45
and in a totem-pole circuit. We speculate on a physical
model to explain the observed dynamic Rdson behaviors
in terms of trapping, detrapping, and back-gating effects.
One of the critical disadvantages of GaN power devices
compared with their Si counterparts is their lack of un-
clamped inductive-switching (UIS) capabilities, and this
problem has not received the proper attention it deserves. We
will show that the intrinsic UIS capability of cascode GaN
devices is low and mainly due to capacitive charging. Al-
though we have tested our 650-V GaN power devices in vari-
ous PFC circuits under harsh conditions without any issues,
we would like to provide comparable UIS capability to that of
Si counterpart devices. We report a dramatic improvement in
the UIS capability of our cascode GaN devices at the system
level, comparable with Si counterparts, and the improvement
comes with no sacrifices in terms of efficiency.
image licensed by ingram publishing
GaN-specific high-temperature reverse bias (HTRB)
tests are performed as partial qualification requirements
at 520 V/150 °C for our 650-V-rated cascode GaN power de-
vices. Dynamic Rdson, leakage currents, and other parame-
ters are measured at both 150 °C and 25 °C at each read-out
point to 1,000 hours, a read-out procedure that is different
from traditional Si HTRB tests, as we focus on high-temper-
ature dynamic Rdson behavior. The preliminary HTRB data
at 1,008 hours indicate solid reliability in terms of stable
high-temperature dynamic Rdson as well as drain and gate
leakage currents.
Improving Capability of
Next-Generation Power Devices
To increase system efficiency and reduce form factor, next-
generation high-efficiency power converters require power
devices that are capable of operating at high switching fre-
quencies (>500 kHz) and high reverse blocking voltage
(>600 V), but without penalties on specific on-resistance
RON [1], [2]. This allows one to shrink the overall system by
up to a factor of four, substantially reducing the total bill of
materials [3], [4]. Wide-bandgap materials and devices are
the best choice as potential candidates for these next-gener-
ation power devices.
Due to its unique combination of a wide-bandgap mate-
rial (hence high blocking voltage capability) with the pres-
ence of a low-resistive two-dimensional electron gas (2DEG)
and thus low on-state resistance, the aluminum gallium ni-
tride (AlGaN)/GaN material system has attracted a lot of at-
tention as a suitable choice for the next generation of power
devices, with device performance well beyond the limits
of Si [5], [6]. Although GaN layers were originally grown on
expensive substrates like silicon carbide and on small wa-
fer sizes (4 in or smaller), substantial progress in epitaxial
growth has been made. Today, high-quality AlGaN/GaN with
sufficiently thick buffer stacks can be grown on Si, on 6- and
8-in wafers. In addition, a gold-free GaN-on-Si process tech-
nology can run in any CMOS production line, using a stan-
dard CMOS tool set. Both factors strongly contribute to a
low production cost, bringing the GaN-on-Si device perfor-
mance # cost figure of merit well beyond its Si competitors
(mainly superjunctions for the 500–900-V application space).
To reduce the gate leakage present in Schottky-gate
AlGaN high-electron-mobility transistors (HEMTs;
~1-nA/mm best case), a metal–insulator–semiconduc-
tor HEMT (MISHEMT) structure is proposed. Several
dielectrics have been proposed in the literature [haf-
nium oxide, aluminum oxide, silicon nitride (SiN),
etc.]. The best results to date have been obtained us-
ing a high-quality SiN or aluminum nitride layer [7].
This article presents on Semiconductor 650-V cas-
code GaN power devices obtained from a combination
of a commercial depletion-mode high-electron-mobility
process, compatible with a Si CMOS production line [7],
and a Si FET manufactured at ON Semiconductor. The
cascode GaN devices are assembled in both TO-247 and
3. 46 IEEE Power Electronics Magazine z September 2015
QFN packages. We report a breakthrough in our epitaxial
and device structure designs that have made possible the
stable high-temperature dynamic Rdson, UIS capability
of the 650-V cascode GaN power devices, and initial re-
liability results under both dc (HTRB) and ac (PFC cir-
cuits) conditions.
UIS Capability of 650-V GaN Power Devices
Intrinsic UIS Capability of 650-V GaN Power Devices
In Figure 1(a), a typical intrinsic UIS test waveform of
current and voltage profiles is shown. The UIS circuit
consists of a 0.3-mH inductor, and the device under test is
ramped with 0.1 A per step to fail. The intrinsic UIS current
at a UIS voltage of 1.3 kV is typically between 2 and 4 A. This
indicates that the cascode 650-V GaN power devices have a
certain level of intrinsic UIS capability, and we attribute this
capability to capacitive charging. This intrinsic UIS
capability might be sufficient in most applications. However,
compared with its Si counterparts, the UIS capability of
these GaN devices needs to be improved.
Improved UIS Capability of 650-V GaN Power Devices
With innovative designs and packages, we have come up
with a solution to improve the UIS capability without sacri-
ficing performance. Figure 1(b) shows the typical current
and voltage UIS waveforms for a 200-mX, 650-V GaN power
device with a 0.3-mH inductor ramped (0.1 A/step) to fail in
the UIS circuit. The UIS current is improved dramatically to
over 20 A, while the UIS voltage is maintained over 790 V.
The UIS energy is typically over 60 mJ, while the UIS ener-
gy of a comparable 650-V-rated Si superjunction device is
typically 40 mJ, such as Infineon C7.
While achieving the UIS capability, we would like to
demonstrate that such an improvement does not nega-
tively affect the performance in circuit applications.
Figure 2 shows the efficiency comparison between the
650-V-rated GaN power devices with and without UIS ca-
pability improvements.
Stable Dynamic Rdson at High Temperatures—
The Key to GaN Power Device Reliability
A Few Years Back: Dynamic
Rdson Issues at High Temperatures
Several years ago, we tested our 650-V GaN power devices at
different temperatures, and we observed that at 250–275 °C,
the dynamic Rdson is quite stable, as reported in many publi-
cations. At 100 °C and above, the dynamic Rdson jumped
many times over, as observed in Figure 3(a). As a result of
the high-temperature dynamic Rdson, PFC tests failed when
the case temperature of the GaN power device reached
60 °C, while the device junction temperature is estimated to
be over 100 °C.
95
94
93
92
91
90
89
88
87
0 50 100 150
Power (W)
200 250 300
With UIS
Capability (Red)
Without UIS Capability (Black)
ON GaN UIS Capability Does
Not Sacrifice Performance
Efficiency(%)
FIG 2 The efficiency of an ON 650-V GaN power device
with improved UIS capability (dashed line) compared with
that without improved UIS capability (solid line) in a CCM
PFC circuit under the conditions of V V, ,V V110 400in out= =
frequency = 100 kHz, and temperature = 25 °C.
FIG 1 (a) An intrinsic UIS waveform. (b) The improved UIS
waveform.
(a)
Id (1 A div)
Vds (500 V div)
Vgs (5 V div)
1.3 kV
2.2 A
(b)
Id = 20 A
Vds = 790 V
4. September 2015 z IEEE Power Electronics Magazine 47
Breakthroughs in Epitaxial and
Device Designs That Achieved Stable
High-Temperature Dynamic Rdson—A Negative
Dynamic Rdson Trend
We believe there is an off-state loss of the 2DEG due to
high electric field stressing. The epitaxial and device
structures are designed to minimize or eliminate such a
loss. With our proprietary and innovative designs and opti-
mizations of epitaxial and device structures, we are able
to achieve stable high-temperature dynamic Rdson and
pass all the ruggedness tests in harsh PFC conditions. Fig-
ure 4(a) shows the dynamic Rdson versus temperature
with a negative dynamic Rdson trend all the way up to
200 °C, with the maximum hump Rdson increase being
less than 20%. Figure 4(b) compares the dynamic Rdson
with an old device at 25 °C and 150 °C. To further demon-
strate the ruggedness of our new 650-V GaN power devic-
es, we actually conducted PFC tests with case tempera-
tures at 150 °C and 175 °C (Figure 5), while the junction
temperature is estimated to be over 250 °C after the GaN
devices are subjected to 10 hours of continuous PFC tests
under harsh CCM conditions with V, V,V V110 400outin = =
and frequency = 100 kHz.
Extensive Circuit Application Tests:
GaN That Reached >99% Efficiency!
To further confirm the ruggedness of the new 650-V GaN
power devices, we have performed extensive circuit applica-
tion tests. These tests include traditional CCM PFC at
different power levels and frequencies and GaN favorite
topology totem pole. Figure 6 shows the comparison
between traditional CCM PFC (red curves) and totem-pole
PFC (blue curves). The efficiency using totem-pole PFC,
where the rectifier diodes are removed to reduce power loss,
is much higher than that of the CCM PFC. Figure 7(a) shows
the efficiency of a 650-V GaN power device at 750 kHz, and
Figure 7(b) shows the efficiency comparison between an on
650-V GaN and a Si superjunction device. The efficiency of
the on GaN device has reached over 99% in a totem-pole PFC
V, V,V V215 385in out= =^ variable frequency: 40–250 kHz).
(a)
PFC at 25 °C: Vin = 110 V, Vout = 400 V,
100 kHz, 300-W Board
95
94
93
92
91
90
89
88
87
86
95
85
75
65
55
45
35
25
0 25
30 W
60 W
150 W
210 W
50 75 100 125 150
Time (minutes)
(b)
Temperature(°C)
0 100
100
200 300 400
Vds (V)
Rdson(X)
500 600 700
150
125
100
75
50
25
10
1
0.1
Temperature(°C)
Temperature
Efficiency(%)
Efficiency
FIG 3 (a) Dynamic Rdson versus temperature. (b) PFC test
failure due to dynamic Rdson.
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0 100 200 300 400 500 600 700
Vds (V)
(a)
Rdson(X)
Temperature(°C)
200
175
150
125
100
75
50
25
Negative Dynamic Rdson
(b)
1.00E + 01
1.00E + 00
1.00E - 01
0 100 200 300 400 500 600 700
Vds (V)
New (Blue) and Old (Black) Devices at 25 °C
Rdson(X)
Old Device at 150 °C
New Device at 150 °C
FIG 4 (a) Negative dynamic Rdson versus temperature.
(b) Dynamic Rdson in the new versus old GaN devices.
5. 48 IEEE Power Electronics Magazine z September 2015
Preliminary HTRB Reliability Tests
Preliminary HTRB reliability tests have been conducted,
and Figure 8 shows the typical dynamic Rdson curves at
25 °C and 150 °C after 1,008 hours of HTRB tests at
150 °C/520 V for our 650-V-rated GaN power devices. The
negative dynamic Rdson trend remains almost
unchanged compared with that in the curves before
HTRB/RTRB tests. The leakage current at 150 °C and
650 V is less than 100 nA. The HTRB/RTRB has been the
most difficult reliability test so far for GaN power devic-
es due to off-state trapping and loss of 2DEG carriers.
TCAD Simulations to Understand
Negative Dynamic Rdson
We have conducted technology computer-aided design
(TCAD) simulations to understand the general shape of the
negative dynamic Rdson. Figure 9(a) shows the trapped elec-
tron distributions after 3-ms stressing under double-pulse con-
ditions at 150 °C: off-state: 90 microseconds, V V,10gs =-
V,V 0sub = and V;V 100ds = on-state: 10 microseconds,
V,V V 0gs sub= = and . V.V 0 1ds = The transient time between
the on- and off-states is 100 nanoseconds. We see electrons
injected from the Si substrate into the GaN buffer layer indi-
cated by the three arrows at the bottom of Figure 9(a). These
injected electrons form a fixed-charge region that produces an
electric field toward the GaN channel and depletes 2DEG and
increases the dynamic Rdson. This accounts for the dynamic
Rdson rising region before 200 V. In Figure 9(b), the conduc-
tion band energy is plotted as a function of the distance from
the Si substrate at x = 4.5 nm. The fixed-charge region near
the Si substrate establishes a negative electric field toward the
Si substrate and stops further electron injection, forming the
maximum at 200 V. The electric field toward the buffer can
now detrap the electrons in the buffer and releases them into
the GaN channel, thus reducing the dynamic Rdson and
accounting for the negative dynamic Rdson region after 400 V.
Summary and Conclusions
We have demonstrated that GaN power devices can have UIS
capability comparable with their Si counterparts without sac-
rificing performance. We have also demonstrated that the key
for power GaN products is to control high-temperature
dynamic Rdson, not the dynamic Rdson at room temperature.
ON Semi-GaN Device:Totem-Pole Versus CCM PFC Tests
(Vin = 230 V, Vout = 400 V, 50 kHz,1-kW Board)
99.5
99
98.5
98
97.5
97
96.5
70
65
60
55
50
45
40
35
30
25
0 200 400 600 800 1,000
Output Power (W)
(a)
Temperature(°C)
Efficiency(%)
Totem-Pole
Temperature
CCM Temperature
CCM Efficiency
Totem-Pole
Efficiency
ON GaN: Totem-Pole Versus CCM PFC
(Vin = 110 V, Vout = 400 V, 50 kHz)
98
98.5
97.5
97
96.5
96
95.5
95
94
94.5
70
65
60
55
50
45
40
35
30
25
0 100 200 300 400 500 600
Output Power (W)
(b)
Temperature(°C)
Efficiency(%)
Totem-Pole
Temperature
CCM
Temperature
CCM Efficiency
Totem-Pole
Efficiency
FIG 6 (a) The totem-pole versus CCM PFC with V.V 230in =
(b) The totem-pole versus CCM PFC with V.V 110in =
95
94
93
92
91
90
89
88
87
86
85
95
85
75
65
55
45
35
25
0 30
30 W
60 W
150 W
210 W 300 W
60 90 120 150 180
Time (minutes)
(a)
SurfaceTemperature(°C)
Efficiency(%)
Old Device
Failed New Device
Passes!
95
96
94
93
92
91
90
89
88
87
0 50 100 150 200 250 300
Power (W)
(b)
Efficiency(%)
175 °C: ON GaN Lasted
10 minutes/300 W After
10 hours/25 °C/300 W, and
10 minutes/150 °C/300 W
25 °C: ON GaN 2
10 hours Reference
Part 2 30 minutes
150 °C: ON GaN Lasted
10 minutes/300 W After
10 hours/25 °C PFC at 300 W
FIG 5 (a) The new GaN device that passed PFC tests at 25 °C.
(b) The new GaN device that passed PFC tests at 150 °C/175 °C.
6. September 2015 z IEEE Power Electronics Magazine 49
We have a new understanding that high-temperature dynamic
Rdson is proposed based on TCAD simulations for the nega-
tive dynamic Rdson. Overall, we have addressed the impor-
tant issues associated with 650-V GaN power devices: UIS
capability and stable high-temperature dynamic Rdson with
over 1,000 hours of HTRB data at 520 V/150 °C. These accom-
plishments represent breakthroughs for on Semiconductor
650-V GaN power devices on an industrial scale.
About the Authors
Charlie Liu (Charlie.Liu@onsemi.com) received his Ph.D.
degree in materials science and engineering from the Uni-
versity of Illinois, Urbana-Champaign, in 1992. Since then,
he has worked at Oak Ridge National Laboratory, the Uni-
versity of California at Santa Barbara, Motorola, Freescale,
IR, and on Semiconductor. Currently, he is a manager and
technical leader for GaN power electronic technology
development at on Semiconductor. He is responsible for
all the technical aspects of 650-V cascode GaN technology
development, including GaN epitaxial and substrate
designs, device designs and layouts, process flows,
device characterizations, circuit applications, intellectual
property, customer interactions, GaN reliability, and prod-
uct designs and qualifications. He has authored 90 publica-
tions and holds 60 issued patents and applications.
Ali Salih (Ali.Salih@onsemi.com) received his B.S.
degree (honors) in physics, his M.S. degree in solid-state
physics, and his Ph.D. degree in electronic materials science
750 kHz: Vin = 110 V, Vout = 400 V,
ON Semi 160-mX GaN
96
95
93
94
92
90
91
89
88
80
75
70
65
60
55
50
45
40
0 50 100 150 200 250
Output Power (W)
(a)
Temperature(°C)
Efficiency(%)
99
99.50
GaN Versus Si MOSFET
98.50
98
97.50
97
96.50
96
95
95.50
10% 25% 50%
95.64 %
97.26%
98.73%
98.24%
98.83% 98.88% 98.90%
99.03%99.11%99.13%
75% 100%
Load (500 W max)
(b)
Efficiency(%)
ON-160 mX
Temperature-ON
130 mX Si MOSFET
120 mX GaN FET
FIG 7 (a) The ON GaN device in a 750-kHz CCM PFC. (b) The ON
GaN device reached >99% efficiency.
1
0.1
150 °C
25 °C
dRdson After 1,008 hours of HTRB
and 24 hours of RTRB
Rdson(X)
0 100 200 300
Vds (V)
400 500 600 700
Negative Dynamic Rdson
FIG 8 Negative dynamic Rdson after 1,008 hours of HTRB reli-
ability tests.
Trapped Electrons Close to Gate Edge
Injected From GaN Channel
3 milliseconds
Trapped Electrons,
Injected from Substrate
4.0E + 16
4.8E + 15
5.8E + 14
6.9E + 13
8.3E + 12
1.0E + 12
-1
0
1
3
2
4
5
5 10 15 20
X (nm)
(a)
Y(nm)
1
1.5
0.5
0
-0.5
-1
-1.5
-2
-3
-2.5
4.2 4.3 4.4 4.6 4.7 4.8
Distance (nm)
(b)
Ec(eV)
002: n43_Stress_0015_Des.tdr 0-0
1 millisecond
3 milliseconds
10 milliseconds
GaN Si
2
Reverse
Electric Field
Toward Si
eTrapped Charge (cm-3)
FIG 9 (a) Electron injection from Si. (b) Conduction band energy.
7. 50 IEEE Power Electronics Magazine z September 2015
and engineering (with a minor in electrical engineering), all
from North Carolina State University. He is the senior direc-
tor of the Technology Development for the Standard Prod-
ucts Group of ON Semiconductor, Phoenix, Arizona. He has
a long career in the semiconductor industry with 27 years of
experience in power device design and new product devel-
opment. He is responsible for the development of IGBTs,
MOSFET, rectifiers, wide band gap, and small signal devic-
es. He has spent most of his career at ON Semiconductor
(formerly a group of Motorola), where his responsibility
covered all classes of power semiconductor devices. He has
published over 50 papers, presented in technical conferenc-
es, and has 28 issued patents to his credit.
Balaji Padmanabhan received his B.E. degree in elec-
tronics and communication engineering from Osmania Uni-
versity, Hyderabad, India, in 2006 and his M.S. and Ph.D.
degrees in electrical engineering from Arizona State Univer-
sity, Tempe, in 2008 and 2013, respectively. He is currently a
design engineer at on Semiconductor, Phoenix, Arizona. His
work includes the design of the state-of-the-art power MOS-
FET and GaN devices. He has authored or coauthored over
15 journal and conference publications and holds eight pat-
ents. He is a recipient of several awards, including the Next
Generation Distinguished Innovator Award and Employee of
the Year Award nomination at on Semiconductor.
Woochul Jeon (Woochul.Jeon@onsemi.com) received
his B.E. degree in electronics engineering from Kyungpook
National University, Daegu, South Korea, in 1999, and his
M.S. and Ph.D. degrees in electrical and computer engineer-
ing from the University of Maryland, College Park, in 2005.
He was a research scientist at the Institute for Research in
Electronics and Applied Physics at the University of Mary-
land from 2005 to 2007. In 2007, he joined Samsung Electro-
Mechanics and Samsung Advanced Institute of Technology
as a senior GaN device engineer. In 2014, he joined on
Semiconductor as a principal device engineer. His main
research interests include the area of GaN power device
design, fabrication, characterization, and applications.
Peter Moens (Peter.Moens@onsemi.com) received his
M.S. and Ph.D. degrees in solid-state physics from the Uni-
versity of Gent, Belgium, in 1990 and 1993, respectively.
From 1993 to 1996, he worked as a postdoctoral fellow in
collaboration with Agfa-Gevaert, Mortsel, Belgium. In 1996,
he joined on Semiconductor, Oudenaarde, Belgium, where
he was involved in the technology and device development
for smart power applications and the related reliability
aspects. Since 2008, he has been responsible for the devel-
opment of 600+ V discrete power devices, both in Si and in
wide-bandgap materials. He is/was a member of the techni-
cal program committees of IEDM, ISPSD, IRPS, IRW, ESS-
DERC, and ESDEOS Symposium. He was the vice chair of
the integrated power subcommittee of IRPS 2005 and 2008
and the chair of the same committee of IRPS 2006 and IRPS
2007. He was the technical program chair of ISPSD 2009
and the general chair of ISPSD 2012. He has authored and
coauthored over 140 publications in peer-reviewed journals
or conferences and is the recipient of three best paper
awards. He holds more than 20 patents.
Marnix Tack (Marnix.Tack@onsemi.com) received his
M.S. degree in electrical engineering from the University of
Gent, Belgium, in 1984 and his Ph.D. degree from the Catho-
lic University of Leuven, Belgium, in 1991. He joined IMEC
in 1985 while working in the field of silicon-on-insulator
CMOS and cryogenic MOS. He joined Mietec in 1990. He has
authored or coauthored more than 80 publications, holds
eight patents, and served on the technical committees of
ESSDERC and ISPS. With his team, he was awarded two
best paper awards at ISPSD2007 and ISPSD2011. He is now
with on Semiconductor and is the senior director of the
Power Technology Center, Corporate R&D, Belgium, devel-
oping smart power and discrete high-voltage and power
technologies in Si and GaN. He is also chairing the Corpo-
rate Technology Innovation Board at ON Semiconductor.
Eddy De Backer (Eddy.DeBacker@onsemi.com)
received his M.S. degree in electrical engineering from the
University of Ghent, Belgium, in 1987. In 1990, he joined
AMIS (formerly Alcatel Microelectronics), Oudenaarde,
Belgium, as a device development engineer. Later, he was
responsible for fab process integration and process devel-
opment in Oudenaarde. Currently, he is the head of the
fab engineering team at on Semiconductor, Oudenaarde,
Belgium, responsible for the process engineering, e-test-
ing, and yield-improvement teams.
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![September 2015 z IEEE Power Electronics Magazine 45
and in a totem-pole circuit. We speculate on a physical
model to explain the observed dynamic Rdson behaviors
in terms of trapping, detrapping, and back-gating effects.
One of the critical disadvantages of GaN power devices
compared with their Si counterparts is their lack of un-
clamped inductive-switching (UIS) capabilities, and this
problem has not received the proper attention it deserves. We
will show that the intrinsic UIS capability of cascode GaN
devices is low and mainly due to capacitive charging. Al-
though we have tested our 650-V GaN power devices in vari-
ous PFC circuits under harsh conditions without any issues,
we would like to provide comparable UIS capability to that of
Si counterpart devices. We report a dramatic improvement in
the UIS capability of our cascode GaN devices at the system
level, comparable with Si counterparts, and the improvement
comes with no sacrifices in terms of efficiency.
image licensed by ingram publishing
GaN-specific high-temperature reverse bias (HTRB)
tests are performed as partial qualification requirements
at 520 V/150 °C for our 650-V-rated cascode GaN power de-
vices. Dynamic Rdson, leakage currents, and other parame-
ters are measured at both 150 °C and 25 °C at each read-out
point to 1,000 hours, a read-out procedure that is different
from traditional Si HTRB tests, as we focus on high-temper-
ature dynamic Rdson behavior. The preliminary HTRB data
at 1,008 hours indicate solid reliability in terms of stable
high-temperature dynamic Rdson as well as drain and gate
leakage currents.
Improving Capability of
Next-Generation Power Devices
To increase system efficiency and reduce form factor, next-
generation high-efficiency power converters require power
devices that are capable of operating at high switching fre-
quencies (>500 kHz) and high reverse blocking voltage
(>600 V), but without penalties on specific on-resistance
RON [1], [2]. This allows one to shrink the overall system by
up to a factor of four, substantially reducing the total bill of
materials [3], [4]. Wide-bandgap materials and devices are
the best choice as potential candidates for these next-gener-
ation power devices.
Due to its unique combination of a wide-bandgap mate-
rial (hence high blocking voltage capability) with the pres-
ence of a low-resistive two-dimensional electron gas (2DEG)
and thus low on-state resistance, the aluminum gallium ni-
tride (AlGaN)/GaN material system has attracted a lot of at-
tention as a suitable choice for the next generation of power
devices, with device performance well beyond the limits
of Si [5], [6]. Although GaN layers were originally grown on
expensive substrates like silicon carbide and on small wa-
fer sizes (4 in or smaller), substantial progress in epitaxial
growth has been made. Today, high-quality AlGaN/GaN with
sufficiently thick buffer stacks can be grown on Si, on 6- and
8-in wafers. In addition, a gold-free GaN-on-Si process tech-
nology can run in any CMOS production line, using a stan-
dard CMOS tool set. Both factors strongly contribute to a
low production cost, bringing the GaN-on-Si device perfor-
mance # cost figure of merit well beyond its Si competitors
(mainly superjunctions for the 500–900-V application space).
To reduce the gate leakage present in Schottky-gate
AlGaN high-electron-mobility transistors (HEMTs;
~1-nA/mm best case), a metal–insulator–semiconduc-
tor HEMT (MISHEMT) structure is proposed. Several
dielectrics have been proposed in the literature [haf-
nium oxide, aluminum oxide, silicon nitride (SiN),
etc.]. The best results to date have been obtained us-
ing a high-quality SiN or aluminum nitride layer [7].
This article presents on Semiconductor 650-V cas-
code GaN power devices obtained from a combination
of a commercial depletion-mode high-electron-mobility
process, compatible with a Si CMOS production line [7],
and a Si FET manufactured at ON Semiconductor. The
cascode GaN devices are assembled in both TO-247 and](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)