High Performance DSP with Xilinx All Programmable Devices (Design Conference 2013)

3,696 views

Published on

This session includes a discussion on rapid prototyping concepts using Xilinx All Programmable FPGAs and SoCs with Analog Devices high speed and precision products. Covered in this session will be common use cases for Xilinx devices in DSP applications that interface to high speed analog. An overview will be provided of how Xilinx accelerates development with DSP platforms that can be used to quickly evaluate and prototype systems that include high speed analog, programmable logic, and embedded processing. Also covered will be an introduction to Xilinx’s new Vivado Design Suite development environment that shortens design cycles by providing an IP centric design flow, easy to use design analysis and debug, and high level design flows supporting C/C++ and MATLAB/Simulink.

Published in: Technology
0 Comments
3 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
3,696
On SlideShare
0
From Embeds
0
Number of Embeds
125
Actions
Shares
0
Downloads
218
Comments
0
Likes
3
Embeds 0
No embeds

No notes for slide

High Performance DSP with Xilinx All Programmable Devices (Design Conference 2013)

  1. 1. High Performance DSP with XilinxAll Programmable Devices
  2. 2. The Signal Processing Design ChallengeRequires 4 distinct skill sets Analog, Digital, Software, IOAnalog and Digital designsneed to be optimized togetherto maximize systemperformance and minimizehardware costRequires real world data fortesting to insure functionalcorrectness2
  3. 3. Rapid Prototyping Addresses this Challenge byProviding:Analog Interfaces that can be easily programmedDigital hardware that can be easily configured withalgorithms MATLAB/Simulink C/C++Large ecosystem of interchangeable analog interfaces FMC PMODsPartners working together! Algorithms Analog Digital Software High-Speed IO3
  4. 4. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms4
  5. 5. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms5
  6. 6. Lowest Total Powerand System CostIndustry’s BestPrice-PerformanceIndustry’s HighestSystem Performanceand CapacityScalable Optimized 28 nm Architecture EnablesDesign Portability6Low-end HDTVHigh-end2 Channel 4 Channel 8+ Channel
  7. 7. Lowest Total Powerand System CostIndustry’s BestPrice-PerformanceIndustry’s HighestSystem Performanceand CapacityScalable Optimized 28 nm Architecture EnablesDesign Portability7Low-end HDTVHigh-end2 Channel 4 Channel 8+ Channel
  8. 8. The First All Programmable SoC8
  9. 9. Industry’s most Advanced DSP SliceArtix-7, Kintex-7, Virtex-7, Zynq-7000+/-X=BADC+-Pre-Add25x18Pattern Detector48-Bit AccumPDSP48E1 SliceDSP48E1 SliceInterconnectDSP48TileDSP48E1 SliceTwo DSP48E1 slices / tileconnected by 5 high-speed interconnectsIndependent accessto accumulatorsWide multiplies for greaternumerical precisionFlexible access todedicated pre-adderPattern detector forefficient rounding hardwareResources / Family Artix Kintex Virtex ZynqMax DSP48E1 Fmax 628 MHz 741 MHz 741 MHz 741 MHzMax DSP48E1 Count 740 1920 3600 20209
  10. 10. 16x16 GMACsSingle Precision Multiply GFLOPsDSP Silicon Performance Leadership at 28nm10160 196.04N/A 6021,0241,12902004006008001,0001,200Multicore DSP Artix Zynq PS Zynq PL Kintex Industry Best HP VirtexGMACs40.0 2124651,4967171,4221,9632,66701,0002,0003,000Multicore DSP CompetitiveHigh VolumeFPGAArtix Zynq CompetitiveCostPerformanceFPGAKintex CompetitiveHighPerformanceFPGAVirtexGFLOPs
  11. 11. Xilinx 7 Series Transceiver7 series offers a full transceiver portfolio for variant customer needs Ultra-high performance GTZ: 28.05Gb/s X 16 High-end Low-power GTH: 13.1Gb/s X 96 Mid-Range GTX: 12.5Gb/s X 32 High-Volume Low-Power GTP: 6.6Gb/s X 16Virtex-7 HT has up to 2.802Tbps total transceiver bandwidth 16 GTZ and 72 GTH transceivers11
  12. 12. Jitter Performance7 series transceivers offer the best jitter performance at 6Gb/s,10Gb/s+ and 28Gb/s in FPGA industryBoth transmitter and receiver use the high performance PLL126.25Gb/s 10.3125Gb/s28Gb/s13.1Gb/s
  13. 13. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms13
  14. 14. Oversampling and Process GainFor a Gaussian signal with signal power Ps and total noise powerdue to quantization Pn the Signal to Noise Ration is SNR = Ps / PnOversampling by M improves the SNR Pnb = Noise power in the signalbandwidth (B) M = Oversampling Factor Pnb = Pn / MEach 2X over-sampling improves the SNR by 3db SNR = Ps / Pnb SNR = M*Ps / PFaster Sample Rates However leads to More difficult timing closure in the FPGA design Extra FPGA Resources Higher Power Consumption14Ps = Signal PowerPn = Quantization Noise PowerB = Bandwidth of InterestNyquist = 2*BFs = Actual Sampling Rate
  15. 15. Decimation and SNR of Ideal ADC15
  16. 16. Decimation Filter Preserves Processing Gain16
  17. 17. System Design ConsiderationsHigher analog IF Sample rates result in better SNRDesigning a digital down converter that minimizes hardwareresourcesIF Sampling clock and the decimation filtering clocks need to bemultiples of each other17DSP48
  18. 18. Improving Area Efficiency using HardwareOverclockingThe DSP Resources in the FPGA can be overclocked to savehardware resources DSP48E1 slice Fmax = 741 MHz at 28nm Implement more channels or more signal processing with smaller AllProgrammable FPGAs or SoCs18XXX100 MHzXTime Division Mux Time Division DeMux100 MHz 300 MHz 100 MHz3X Over ClockingDSP48
  19. 19. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms19
  20. 20. DSP Design Methodology LeadershipFlexible design environmentFloating-point and Fixed-pointHardware GenerationReal time analog dataacquisitionWorld class C design flow20HDLCoderSystemGeneratorVivadoHLSZC706MATLAB / SimulinkToolbox IP Xilinx IPMATLABSimulinkMATLABSimulinkC/C++C LibrariesAnalogSignalsA/DD/AVivadoRTLIP CatalogVivado System EditionAlgorithm SpecificationAD9250AD9129
  21. 21. DSP IP and Reference Designs LeadershipDSP IP libraries available for multiple design environmentsIndustries most advanced library of LTE specific wireless IPReference Designs provide working starting points DSP, SDR, Wireless, Aerospace and Defense21LTE Specific IP General Wireless IP Video IP HLS LibrariesLTE Turbo Enc/Dec Convolutional Encoder Scalar Math.hLTE Channel Enc/Dec Viterbi Decoder Color Correction Floating Point libraryLTE MIMO Enc/Dec DFT/iDFT Timing controller OpenCVLTE FFT DUC/DDC Compiler On-Screen Display AXI InterfacesLTE Channel Estimator FIR Compiler Image Edge Enhancement Linear Algebra *LTE PUCCH Receiver DDS Compiler H.264 EncoderLTE RACH Detector CORDIC Color Space ConverterRTLMATLAB/SimulinkC/C++
  22. 22. Xilinx System Generator for DSPEnables MATLAB/Simulink for DSP FPGA Design 100+ Xilinx optimized DSP building blocks Automatic code generation Supports parameterization in MATLABVivado Integration Import C-based IP from Vivado HLS Automatic bitstream generation Vivado Project File generation22System Generator for DSP
  23. 23. Vivado High-Level C/C++ SynthesisComprehensive coverage C/C++/SystemC Arbitrary precision Floating-pointAccelerated verification 2 to 3 orders of magnitudefaster than RTL for largerdesignFast compilation and designexploration Algorithm feasibility Architecture IterationCustomer proven results23
  24. 24. Introducing Vivado IP IntegratorIP Deployment and AssemblyAbstract IP Assembly Does not require RTL Debug integrationIntelligent IP Integration Real time design rule checks Parameter propagation Designer AssistanceIP Aware AXI Interconnect Automated interface Device driver & address map generation
  25. 25. Use with High-Level Tool Flows and DesignSubsystemsIPCatalogIP IntegratorVivado HLSSystem Generator for DSPVivado Integrated Design EnvironmentPopulate the VivadoIP Catalog using High-Level Design tools• HLS• System GeneratorIntegrate IP intodesign subsystemsfor Xilinx platforms
  26. 26. Vivado Design Suite: From Months to Weeks
  27. 27. High-level Hardware DebuggingFlexible, targeted probing ofHDL and XDC usingMARK_DEBUG propertyRTL and synthesized netlistprobing in multiple viewsSystem-level probing insideof IP integrator view27entity FIR isport (clk : inrst : indin : inHDLSchematicHierarchyDebug ProbeVivado IPIntegrator
  28. 28. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms28
  29. 29. DUC/DDC Architectural ConsiderationsBoth system performance and hardware resources should be takeninto accountPulse shaping needs to be performed on TX / RX sideWideband / Narrowband signalFilter type and # of filter stagesIF Sampling rate vs Programmable Logic Fmax29
  30. 30. Using Model Based Design to Explore FilterConfigurations30Anti-AliasingFilterFilter Lengthand SampleRate for 1stFilterFilter Lengthand SampleRate for 2ndFilterFilter Lengthand SampleRate for 3rdFilterArchitectureof choiceConfiguration 1 91 taps (↑8)61.44 MSPSConfiguration 2 47 taps (↑4)30.72 MSPS11 taps (↑2)61.44 MSPSConfiguration 3 23 taps (↑4)15.38 MSPS25 taps (↑2)61.44 MSPSConfiguration 4 23 taps (↑2)15.38 MSPS11 taps (↑2)30.72 MSPS11 taps (↑2)61.44 MSPS√MathWorks FDATool
  31. 31. Create Executable Specification in Simulink31Filters automaticallygenerated by FDATool
  32. 32. Correct by Construction Hardware Designusing System Generator32System GeneratorHardware DesignSimulinkExecutable SpecXilinx Gateways define FPGA Boundary
  33. 33. Improve Results through Overclocking33Resource Separate Filter Chains TDM TDM + 3X OverclockingDUC IF Sample Rate 61.44 MHz 61.44 MHz 61.44 MHzHardware Clock Frequency 61.44 MHz 122.88 MHz 368.64 MHzLUTs 1486 952 961Registers 1987 1230 1176DSP48E1 27 17 11DSP48E1s used in Filters 20 10 4
  34. 34. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms34
  35. 35. Xilinx JESD204 IP v3.1 (Released in 2012.4)Designed to JEDEC JESD204Bstandard specificationSupports Transmit, Receive, andDuplex (TX & RX) Modes1 to 8 lane configurations up to12.5 GbpsSupport for subclass 0, 1, and 2Deterministic latency forsubclass 1 and 2Supports GTX, GTH, GTP35JESD204BStateMachineGTTILEClocksManagementRegistersControl &StatusJESD204 Data (AXI4-Stream)Test DataGen/CheckerStatus & Control(AXI4-Lite)
  36. 36. Wizard Based JESD204 IP Core GenerationEasy to use Graphical InterfaceGenerated Files include The netlist file for the core XCO files Release notes and documentation A Verilog example design anddemonstration test bench Scripts to synthesize, implementand simulate the example design36
  37. 37. JESD204B Example Design37
  38. 38. Analog Devices Scan ViewerDisplays Eye Scan diagram forJESD204B transceiversLeverages the eyescan block inthe Xilinx 7-series transceivers Validate interface Reusable into production designs38
  39. 39. AgendaXilinx All Programmable Devices for Signal ProcessingSignal Processing System Design ConsiderationsXilinx DSP Design EnvironmentDUC/DDC Design using Model Based DesignXilinx JESD204B SolutionRapid Prototyping using Xilinx DSP Platforms39
  40. 40. HDL Blocks: AD9250-FMC-250EBZReference design for: Virtex-7, Kintex-7, Virtex-6 KC705 ZC706 VC707 ML60540ADI IP CoreXilinx IP Core
  41. 41. JESD204B High-Speed ADC Demo41Analog Devices’AD9250-FMC-250EBZ 14-bit /250 MSPS4-ch ADCAD9250 HighSpeedJESD204BSerdesOutputs DataEye @ 5GbpsAnalog Input(Single-Tone FFT withfIN = 90.1 MHz)Ethernet dataconnection to PCfor Verification ofAnalog Signal onVisualAnalog™Xilinx Kintex-7 FPGA KC705 Eval KitRecovered Eye(after EQ/CDR)
  42. 42. SummaryView Demonstrations at Show Analog Devices Booth JESD204B Platform Demonstration Xilinx Booth Zynq SDR Kit with ZC702Development board Artix-7 AMS DemoGet Started Today with the ZynqSDR KitLearn More at www.xilinx.com/DSP www.mathworks.com/Xilinx www.mathworks.com/zynq www.analog.com/xilinx42

×