vlsi_12.pdf

MOSFET Fundamentals & Trends in
VLSI Devices
Department of Electronics Engineering
YMCA University of Science & Technology, Faridabad,
Haryana 1

YMCAUST, Faridabad …….Recent trends in VLSI 2
Outline of the Presentation
 Brief History of the device evolution
 Device and Technology Simulator
 Basics of MOSFET
 Scaling principle
 Perspective beyond CMOS Technology

In 1945, Bell Labs established a group to develop a semiconductor
replacement for the vacuum tube. The group led by William Shockley,
included, John Bardeen, Walter Brattain and others.
History: Semiconductor Devices & Technology

In 1947 Bardeen and Brattain and Shockley succeeded in creating an
amplifying circuit utilizing a Ge point-contact "transfer resistance"
device that later became known as a transistor
The transistor invented at Bell lab. in 1947
In 1951 Shockley developed the junction transistor, a more practical
form of the transistor.
By 1954 the transistor was an essential component of the telephone
system and the transistor first appeared in hearing aids followed by
radios.
In 1956 the importance of the invention of the transistor by Bardeen,
Brattain and Shockley was recognized by the Nobel Prize in physics.

Kilby's invention had a serious drawback, the
individual circuit elements were connected
together with gold wires making the circuit
difficult to scale up to any complexity.

Germanium has such attractive features as low junction forward
voltage and high electron mobility. However, it lost out to silicon as
the semiconductor of choice due to its disadvantages:
 Limited maximum temperature
 Relatively high leakage current
 Unable to withstand high voltages
 Less suitable for fabrication of integrated circuits
Exits the Ge Transistor

The Silicon Transistor
Bell Labs chemist Morris Tanenbaum fabricated
the first silicon transistor in January 1954.
However, Bell Labs did not pursue the process
further, thinking it unattractive for commercial
production.
This allowed Gordon Teal of Texas
Instruments to claim credit for the breakthrough
several months later.
Image source: Computer History Museum

9
1958 - Integrated circuit invented
September 12th 1958 Jack Kilby at
Texas instrument had built a simple
oscillator IC with five integrated
components (resistors, capacitors,
distributed capacitors and transistors)
In 2000 the importance of the IC was
recognized when Kilby shared the
Nobel prize in physics with two others.
a simple oscillator IC

The Planar
Transistor
Jean Hoerni, a cofounder of Fairchild Semiconductor,
invented the first planar, or flat, transistor in 1959. He
developed a structure with N and P junctions formed in
silicon. Over the junctions a thin layer of silicon dioxide
was used as an insulator and holes were etched open in
the silicon dioxide to connect to the junctions.
In 1959, Robert Noyce also of Fairchild had the
idea to evaporate a thin metal layer over the circuits
created by Hoerni's process. The metal layer connected
down to the junctions through the holes in the silicon
dioxide and was then etched into a pattern to
interconnect the circuit. Planar technology set the stage
for complex integrated circuits and is the process used
today. The result was the best-performing transistor of
its time.
Image source: Fairchild Semiconductor

1960 - First MOSFET fabricated
Kahng and Atalla at Bell Labs fabricates the first MOSFET.
Integrating Multiple Components
Robert Noyce—cofounder of Fairchild
Semiconductor and later cofounder of Intel— saw
a way to use Hoerni’s process to combine multiple
electronic components, including transistors, on a
single piece of silicon. Announced in 1961, this
resistor-transistor logic (RTL) chip was one of the
first commercial integrated circuits. The one
shown has four transistors (quadrants in the
middle). The white lines are metal traces, which
connect the transistors to the two resistors below
(horizontal blue bar). The Apollo Guidance
Computer used the chip.
I
1961 - First commercial ICs
Fairchild and Texas
Instruments both introduce
commercial ICs.

1962 - Transistor-Transistor Logic invented
1962 - Semiconductor industry surpasses $1-billion in sales
At that time only a few simple gates offering primitive logic
functions such as not, nand, nor etc. could be accommodated (SSI)
1963 - First MOS IC
RCA produces the first PMOS IC.

1963 - CMOS invented
• Frank Wanlass at Fairchild Semiconductor originated and published
the idea of complementary-MOS (CMOS).
• It occurred to Wanlass that a complementary circuit of NMOS and
PMOS would draw very little current. Initially Wanlass tried to
make a monolithic solution, but eventually he was forced to prove
the concept with discrete devices.

1965 - Moore's law
In 1965 Gordon Moore, director of
research and development at
Fairchild Semiconductor
wrote a paper for Electronics
entitled "Cramming more
components onto integrated
circuits".

1965 - Moore's law
• In the paper Moore observed that "The complexity for minimum
component cost has increased at a rate of roughly a factor of two
per year". This observation became known as Moore's law, the
number of components per IC double every year.
• Moore's law was later amended to, the number of components per
IC doubles every 18 months.
• Moore's law hold to this day ?.

 By 1970 MSI circuits with about a thousand transistors appeared
 By 1980 LSI circuits of approximately one hundred thousand
devices were possible
This ultimately led the arena of VLSI

VLSI Arena
 A VLSI contains more than a million or so switching devices or logic
gates
 Early in the first decade of the 21st century, the actual number of
transistors has exceeded 100 million
 A piece of silicon (a chip) is typically about 1 centimeter on a side

WHY VLSI DESIGN?

Money,
technology,
civilization
Broad Objective of VLSI

How to Achieve Broad Objectives
 Integration reduces manufacturing cost - (almost) no manual assembly
 Integration improves the design
 Lower parasitics = higher speed
 Lower power consumption
 Physically smaller
Integration

Choice of Technology in VLSI
 Two distinct types of technology are fabricated in silicon based
upon
 BJT (Bipolar Junction Transistor)
 MOS (Metallic Oxide Semiconductor)
 Since processing of these technologies is very different, it is
impractical to mix them up within a chip
Results Both BJT and MOS Technologies
are used separately

Brief comparison between BJT and MOSFET
Structure
Size
Driving capability
Speed
Power dissipation
Gain
Faults during manufacturing : Easier MOS manufacturing process
makes it less prone to defaults and errors.
Thus in terms of area, power dissipated, yield and flexibility MOS technology
is superior to BJT

Material Choice for VLSI Technology
Ge
Si
GaAs

……ultimate choice of Electronic Device
Technology ultimately focused on Si based MOSFET
Old wine in new bottle

Device and Technology- Simulator
Why to simulate Device
To save the cost
Knowing the Performance before
fabrication
Simulator, at present,
used are:
1) Sentaurus TCAD (Synopsis)
2) Atlas TCAD ( Silvaco)
3) Genesis TCAD (Cogenda)
Oxide
Spacer
S S1 D1 D
Poly Gate
N-MOSFET device structure
Virtually fabricated in Sentaurus simulation.

MOSFET -STRUCTURE
G
B
n
+
n
+
D
W
S
SiO2 Gate
L
tox
p-Si sub (NA)
L – Channel Length, W – Channel Width
tox – Oxide Thickness, NA – Substrate Doping

MOSFET –OPERATION MODE
• Gate biased negatively
with respect to substrate
– holes move towards
the surface –
Accumulation
• Gate biased positively
with respect to substrate
– holes get repelled from
surface, leaving ionized
acceptors there –
Depletion
• Eventually, with larger
gate bias, electrons get
attracted towards surface
– creation of an inversion
layer - Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg
< 0
(b)
+
-
0 < Vg < Vt
depletion region
(c)
+
-
Vg > Vt
depletion region
inversion region

MOSFET –OPERATING MODEs(continued)
• Under the accumulation mode, the device behaves
like a parallel plate capacitor and is not of much
interest
• For the device to be able to be used as an amplifier
or a switch, the most important mode of operation is
inversion
Conclusion

Regions of Operation
Gate to channel:
Vds near source
Vgd near drain
Switching delay is
determined by:
• time required to
charge/discharge gate
• time for current to travel
across channel
drain

Ideal I-V Characteristics
ds gs t
V V V
= −
( )
2
0,
,
2
,
2
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
β
β

 <

  
= − − <
  
 


− >


Saturation region:
into equation…
cutoff
linear
saturation
NMOS
PMOS
2 3
n
p
µ
µ
≤ ≤
Holes have less mobility than electrons,
so PMOS’s provide less current (and are
slower) than NMOS’s of the same size
Which parameters do we change to make
MOSFETs faster?
ox
W
C
L
β µ
=
Shockley 1st order transistor models

Ideal I-V Characteristics
ds gs t
V V V
= −
( )
2
0,
,
2
,
2
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
β
β

 <

  
= − − <
  
 


− >


Saturation region:
into equation…
cutoff
linear
saturation
NMOS
PMOS
2 3
n
p
µ
µ
≤ ≤
ox
W
C
L
β µ
=
But this current behaves like a parabola !!

MOSFET Fabrication Steps

Building A MOSFET Transistor Using Silicon
http://micro.magnet.fsu.edu/electromag/java/transistor/index.html

It is done. Now, how does it
work?

To enhance performance: Speed, Area, Power Consumption, cost
Why to improve ?
Main Problems : Power Dissipation
Reduced time of operation
Higher weight (batteries)
Restricted mobility
High efforts for cooling
Increased operational costs
Reduced reliability

Performance Enhancement in Recent Years in IC
Device
Miniaturization
Scaling
Scaling Objective Between Two Technology
 Doubling of the transistor density
 Reduction of the gate delay by 30% (43% increase in frequency)
 Reduction of the power by 50% (at 43% increase in frequency)

How could it be done
exactly?

Scaling Principle-Constant Field
Motivation for scaling
Field pattern is essential to determine the behavior of device & it can be determined by
solving the Poison’s equation
2
2
qN
x
φ ρ
ε ε
∂
=
− =
−
∂
Device dimension can be reduced if the solution of Poison’s
equation remain same I.e field pattern remain constant
φ =potential
N= doping
X= dimensions
For large
geometry
Let
For small
geometry
λ is scaling factor less than 1

YMCAUST, Faridabad …….Recent trends in VLSI
Scaling Principle-Constant Field(contd.)
2 ' ' '
'2
qN
x
φ ρ
ε ε
∂
=
− =
−
∂
( )
( )
2 ' '
2
qN
x
λφ ρ
ε ε
λ
∂
=
− =
−
∂
' N
N
λ
=
If
(1)
Then equation (1) becomes
( )
( )
2 '
2
2
qN
x
λ φ ρ
ε λε
λ
∂
=
− =
−
∂
2
2
qN
x
φ ρ
ε ε
∂
=
− =
−
∂
This shows that solution for both the geometry remain same

Scaling, what does it mean?

Ultimately Scaling is done:
By reducing all
the dimension
By reducing all
the voltages
By increasing the
doping density

Micrograph of fabricated MOS at fab House
Cross-sectional micrograph of a 60-nm MOSFET built at Bell Labs
with 1.2 nm gate oxide.
Fab Houses (Foundries)
In India  Nil
In USA  10
In Taiwan  600

Performance at present due to Scaling
For example: Processor Development
On November 15, 2011, Intel celebrated the 40th anniversary of the
Intel 4004 microprocessor and made the following claims about
the development since then:
 Processor performance has increased by a factor
of 350,000X
 Transistor power consumption has decreased by
a factor of 5,000X
 Price has decreased by a factor of 50,000X

Scaling Problems -- Concerns for Future ICs
Due to scaling following problems have been arisen
• Tunnel currents in gate oxide and junctions
• Power dissipation
• Subthreshold leakage current
• Short channel effects
• Interconnect RC time constants, power consumption
• Statistical fluctuations
– Local stochastic and global systematic variations
– Gate length
– Oxide thickness
– Doping density
– Threshold voltage
Of course device size is reaching its physical limits

Scaling Problems -- Concerns for Future ICs
Due to scaling following problems have been arisen
• Short channel effects (Very Serious)
• Consequences
• Tunnel currents in gate oxide and junctions
• Power dissipation
• Subthreshold leakage current
• Interconnect RC time constants, power consumption
• Statistical fluctuations
– Local stochastic and global systematic variations
– Gate length
– Oxide thickness
– Doping density
– Threshold voltage
Of course device size is reaching its physical limits

Short Channel Effects in MOSFET
• Threshold Voltage variation
• Mobility Degradation with vertical field
• Velocity saturation
• Hot carrier Effects
• Drain Induced Barrier Lowering
• Drain Source series Resistance
• Punch through
• Output impedance with VDS

When Will CMOS Scaling End?
The 2012 version of the ITRS indicates that CMOS physical gate
lengths will be on the order of 10 nm and that of gate oxide will 0.8 nm
These are near the scaling limit people forecast from
fundamental physical considerations
First
This
should occur in the
2016-2018 time
frame

Perspectives Beyond CMOS Technology
Following are the most probable technologies for future VLSI domain
 SOI Based MOSFET
 Double Gate MOSFET
 FinFET
 CNT MOSFET
 Power MOSFETs

SOI –Based MOSFET Structure
Features-:
•Silicon channel layer grown on a layer of oxide.
•Absence of junction capacitance makes this an attractive option.
•Low leakage currents and compatible fabrication technology.

Merits
• Reduced parasitic effect – reduction of source/channel and drain/channel
capacitances.
• Absence of latch up.
• Compatible with conventional Silicon processing
• Reduced leakage.
Demerits
• Drain Current Overshoot.
• Kink effect
• Thickness control is problem.
• Surface states.
(de)Merits of SOI Technology

Front Gate
Back Gate
Drain
Source
body
n+
source
n+
drain
Gate
(metal/poly)
Gate
(metal/poly)
Front Gate
Back Gate
Drain
Source
body
n+
source
n+
drain
Gate
(metal/poly)
Gate
(metal/poly)
Double Gate MOSFET Technology
Features -:
• Upper and lower gates control the channel region
• Ultra-thin body acts as a rectangular quantum well at device limits
• Directly scalable down to 20 nm channel length

(de)Merits of DG MOSFET Technology
Merits
• Short channel effect control: Better scalability & Lower DIBL
• High drive Current
• Near-Ideal Sub threshold slope
• Lower Gate Leakage and sub threshold current
• Elimination of Vt variation due to Random dopant fluctuation
Demerits
• Standard fabrication process still need to be developed.
• Thin Silicon channel introducing series resistance is of particular concern.
• Maintaining a thin, uniform channel thickness is major obstacle.

finFET
Features-:
• A FinFET transistor is a MOSFET built on an SOI substrate where the gate is
placed on two, three, or four sides of the channel .
• These devices have been given the generic name "finfets" because the
source/drain region forms fins on the silicon surface.

Merits
• It is Quasi-Planner Structure.
• It achieve high drive currents at small device footprint, because the device
‘‘width’’, which is mainly determined by the fin height, can be scaled
independently from the lateral dimension.
• Very suitable for SRAMs where high density together with the capability of
driving a large bitline load is required.
• The FinFET devices have significantly faster switching times due to large
current drive capability than the mainstream CMOS technology
(de)Merits of DG MOSFET Technology
Demerits
Its fabrication is very difficult.

58
CNTFET
Drain
Source
Carbon nano-tubes are molecular sheets of carbon wrapped around into a
tube
The attractiveness of nano-wires lies in the fact that its fabrication is still
based on the highly mature existing bulk-silicon technology
Also, it has been reported that at such small dimensions electron mobilities
are higher than those in bulk-silicon; this would translate into faster devices
Features:

Serious Technological Limitations of CNT FET
At such small dimensions,
the minimum theoretical equivalent
resistance of such CNT has been
theoretically
and experimentally been shown to be
6 KΩ or more

Research Challenges in CNTFET
1) The most challenging issues is to reduce the contact resistance between nano
devices and external world which is 6 K Ohm, a very high value.
2) Developing circuit models for nano devices that could be used for integration
into CAD tools for design verification and simulation will require significant effort.
3) It would be quite a challenge to develop design and test strategies for such
dense systems.
4) The Cost-effective manufacturing processes will have to be developed for mass
production of CNTFET and hence nano-computers.

A New Generation of Power Semiconductor
Devices

Still number of Power Devices
are possible

Finally: An Accurate Statement
“Bill Gates is a very rich man today ...
and do you want to know why? The
answer is one word: versions”
Welcome Windows 1, 2, 3, NT, 95, 98, 2000,
ME, Xp, Vista, 7, 8.
We’re so happy to pay for all of you!

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