8. Signal Bandwidths can be Processed Introduction 5 C.–J. Yen Analog Layout and Process Concern
9. Digitization of a Nature Signal Introduction 6 C.–J. Yen Analog Layout and Process Concern
10. Symbols for MOS Transistors Integrated-Circuit Devices and Modeling Commonly used symbols for p-channel transistors. Commonly used symbols for n-channel transistors. 7 C.–J. Yen Analog Layout and Process Concern
11. Cross Section of a MOS Transistor 8 Integrated-Circuit Devices and Modeling A cross section of a typical n-channel transistor. C.–J. Yen Analog Layout and Process Concern
12. N-Channel MOS Transistor (V G << 0) 9 Integrated-Circuit Devices and Modeling V G << 0 resulting in an accumulated channel (no current flow). C.–J. Yen Analog Layout and Process Concern
13. N-Channel MOS Transistor (V G >> 0) 10 Integrated-Circuit Devices and Modeling The channel is present (current flow possible from drain to source). C.–J. Yen Analog Layout and Process Concern
14. Dimensions of a MOS Transistor 11 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
15. Channel Charge Density 12 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
16. Pinch Off 13 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
17. I D -V DS Curve for a MOS Transistor 14 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
18. I D -V DS Curve for Different V GS 15 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
19. Weak Inversion 16 Integrated-Circuit Devices and Modeling if and then is a characteristic current C.–J. Yen Analog Layout and Process Concern
20. Moderate Inversion 17 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
21. Transfer Characteristics of Temperature 18 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
22. Small-Signal Capacitances 19 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
23. Small-Signal Model in Active Region 20 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
24. MOS Transistor Equations in Active Region 21 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
25. Small-Signal Model in Triode Region 22 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
26. MOS Transistor Equations in Triode Region 23 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
27. MOS Parameters for a 0.8- μ m Technology 24 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
28. SPICE Parameters for Modeling BJTs 25 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
29. Simple CMOS Logic Circuits 26 Modern CMOS Process C.–J. Yen Analog Layout and Process Concern
30. Cross Section of the CMOS IC 27 Modern CMOS Process C.–J. Yen Analog Layout and Process Concern
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54. MOS Transistor 51 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
55.
56. Weight Current Cell Layout 53 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
57. Current Mirror Layout Technique (I) 54 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
58. Current Mirror Layout Technique (II) 55 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
59. Current Mirror Layout Technique (III) 56 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
60. Current Mirror Layout Technique (IV) 57 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
61. Current Mirror Layout Technique (V) 58 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
![[object Object],[object Object],[object Object],[object Object],[object Object],Contents](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)