The document discusses using the Xilinx Block RAM core generator to generate a block RAM intellectual property core. It walks through selecting the width and depth of the RAM, generating the core, and provides options to view the HDL instantiation template and synthesized output files. The core generator creates parameterized RAM components that can be instantiated in FPGA designs.

1. CORE Generator
Xilinx Block RAM
2010. 06. 09

2. Project → New Source...

3. CORE Generator
Block RAM

4. bram_test

5. BlockRAM IP

6. Next >
BlockRAM
Memories & Storage Elements → RAMs&ROMS

7. Block Memory Generator
Finish BlockRAM

8. Block Memory
Generator

9. (1)
2
(2) Next >

10. (1) width( ) Depth( )
32bit 0-9
10bit(=1024) !!
(2) Next >

11. (1) Next >

12. (1) Next >

13. (1) Generate !!

14. ISE Console

15. Block RAM

16. ....
HDL
!!

17. (1)
(4) component
(3) View HDL Instantiation Template
(2)