The analysis describes what a given circuit will do under certain
operating conditions. The behaviour of a clocked sequential
circuit is determined from the inputs, the outputs, and the
state of its flip-flops.
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1. ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS
D.R.V.L.B Thambawita
October 29, 2017
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
https://sites.google.com/view/vajira-thambawita/leaning-materials/slides
2. Introduction
Analysis describes what a given circuit will do under certain
operating conditions. The behavior of a clocked sequential
circuit is determined from the inputs, the outputs, and the
state of its ļ¬ip-ļ¬ops.
State Equation
The behavior of a clocked sequential circuit can be described
algebraically by means of state equations. A state equation(also
called a transition equation) speciļ¬es the next state as a function
of the present state and inputs.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
4. Example: State equations
A(t + 1) = A(t)x(t) + B(t)x(t) (1)
B(t + 1) = A (t)x(t) (2)
Boolean expressions are a function of the present state, we can
omit the designation (t) after each variable for convenience and
can express the state equations in the more compact form:
A(t + 1) = Ax + Bx (3)
B(t + 1) = A x (4)
Similarly, the present-state value of the output can be expressed
algebraically as:
y(t) = [A(t) + B(t)]x (t) (5)
By removing the symbol(t)
y = (A + B)x (6)
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
5. State Table
The time sequence of inputs, outputs, and ļ¬ip-ļ¬op states can
be enumerated in a state table (sometimes called a transition
table ).
The table consists of four sections labeled present state,
input, next state, and output .
The derivation of a state table requires listing all possible
binary combinations of present states and The derivation of
a state table requires listing all possible binary combinations
of present states and inputs.
The next-state values are then determined from the logic
diagram or from the state equations.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
6. State Table
Figure: State table for above example
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
7. State Table
The next state of ļ¬ip-ļ¬op A must satisfy the state equation
A(t + 1) = Ax + Bx (7)
Similarly, the next state of ļ¬ip-ļ¬op B is derived from the state
equation
B(t + 1) = A x (8)
The output column is derived from the output equation
y = Ax + Bx (9)
In general, a sequential circuit with m ļ¬ipļ¬ops and n inputs
needs 2m+n rows in the state table.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
8. State Table
It is sometimes convenient to express the state table in a slightly
diļ¬erent form having only three sections: present state, next
state, and output.
Figure: Second form of state table
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
9. State Diagram
The information available in a state table can be represented
graphically in the form of a state diagram.
In this type of diagram, a state is represented by a circle, and
the (clock-triggered) transitions between states are indicated
by directed lines connecting the circles.
The directed lines are labeled with two binary numbers
separated by a slash. The input value during the present
state is labeled ļ¬rst, and the number after the slash gives
the output during the present state with the given input.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
10. State Diagram
Figure: State diagram of the above example
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
11. Up to now!
Circuit diagram ā Equations - State table ā State diagram.
This sequence of steps begins with a structural representation
of the circuit and proceeds to an abstract representation of its
behavior.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
12. Flip-Flop Input Equations
The logic diagram of a sequential circuit consists of ļ¬ip-ļ¬ops
and gates.
The knowledge of the type of ļ¬ip-ļ¬ops and a list of the
Boolean expressions of the combinational circuit provide the
information needed to draw the logic diagram of the
sequential circuit.
The part of the combinational circuit that generates external
outputs is described algebraically by a set of Boolean
functions called output equations .
The part of the circuit that generates the inputs to ļ¬ip-ļ¬ops is
described algebraically by a set of Boolean functions called
ļ¬ip-ļ¬op input equations (or, sometimes, excitation
equations ).
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
13. Flip-Flop Input Equations
Flip-ļ¬op input equations and an output equation for the above
example,
DA = Ax + Bx (10)
DB = A x (11)
y = (A + B)x (12)
Note that the expression for the input equation for aD
ļ¬ip-ļ¬op is identical to the expression for the corresponding
state equation.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
14. Analysis with D Flip-Flops
The procedure for analyzing a clocked sequential circuit with
D ļ¬ip-ļ¬ops.
The circuit we want to analyze is described by the input
equation DA = A ā x ā y.
The x and y variables are the inputs to the circuit.
No output equations are given, which implies that the output
comes from the output of the ļ¬ip-ļ¬op.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
15. Analysis with D Flip-Flops
Figure: The logic diagram is obtained from the input equation
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
16. Analysis with D Flip-Flops
The state table has one column for the present state of
ļ¬ip-ļ¬op A, two columns for the two inputs, and one column
for the next state of A .
The next-state values are obtained from the state equation
A(t + 1) = A ā x ā y
Figure: State Table
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
17. Analysis with D Flip-Flops
The circuit has one ļ¬ip-ļ¬op and two states. The state diagram
consists of two circles, one for each state.
Figure: State diagram
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
18. Analysis with JK Flip-Flops
The next-state values are evaluated from the state equations.
For a D-type ļ¬ip-ļ¬op, the state equation is the same as the
input equation.
When a ļ¬ip-ļ¬op other than the D type is used, such as JK or
T, it is necessary to refer to the corresponding characteristic
table or characteristic equation to obtain the nextstate
values.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
19. Analysis with JK Flip-Flops
The next-state values of a sequential circuit that uses JK or T type
ļ¬ip-ļ¬ops can be derived as follows:
1 Determine the ļ¬ip-ļ¬op input equations in terms of the present
state and input variables.
2 List the binary values of each input equation.
3 Use the corresponding ļ¬ip-ļ¬op characteristic table to
determine the next-state values in the state table.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
20. Analysis with JK Flip-Flops: Example
Figure: Example circuit with JK ļ¬ip ļ¬ops
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
21. Analysis with JK Flip-Flops: Example
The circuit can be speciļ¬ed by the ļ¬ip-ļ¬op input equations.
JA = B
KA = Bx
JB = x
KB = A ā x = A x + Ax
The next state of each ļ¬ip-ļ¬op is evaluated from the
corresponding J and K inputs and the characteristic table of
the JK ļ¬ip-ļ¬op
Figure: The characteristic table of the JK ļ¬ip-ļ¬op
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
22. Analysis with JK Flip-Flops: Example
Figure: State Table for Sequential Circuit with JK Flip-Flops
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
23. Analysis with JK Flip-Flops: Example
The next-state values can also be obtained by evaluating the state
equations from the characteristic equation.
1 Determine the ļ¬ip-ļ¬op input equations in terms of the present
state and input variables.
2 Substitute the input equations into the ļ¬ip-ļ¬op characteristic
equation to obtain the state equations.
3 Use the corresponding state equations to determine the
next-state values in the state table.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
24. Analysis with JK Flip-Flops: Example
The characteristic equations for the ļ¬ip-ļ¬ops are obtained by
substituting A or B for the name of the ļ¬ip-ļ¬op, instead of Q :
A(t + 1) = JA + K A (13)
B(t + 1) = JB + K B (14)
Substituting the values of JA and KA from the input equations, we
obtain the state equation for A:
A(t + 1) = BA + (Bx ) A = A B + AB + Ax (15)
B(t + 1) = x B + (A ā x) B = B x + ABx + A Bx (16)
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
25. Analysis with JK Flip-Flops: Example
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
26. Analysis with T Flip-Flops
The analysis of a sequential circuit with T ļ¬ip-ļ¬ops follows
the same procedure outlined for JK ļ¬ip-ļ¬ops.
The next-state values in the state table can be obtained by
using either the characteristic table or the characteristic
equation.
Q(t + 1) = T ā Q = T Q + TQ
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
27. Analysis with T Flip-Flops: Example
Figure: Sequential circuit withT ļ¬ip-ļ¬ops (Binary Counter)
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
28. Analysis with T Flip-Flops: Example
The values for the next state can be derived from the state
equations by substituting TA and TB in the characteristic
equations.
A(t + 1) = (Bx) A + (Bx)A = AB + Ax + A Bx
B(t + 1) = x ā B
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
29. Analysis with T Flip-Flops: Example
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
30. Analysis with T Flip-Flops: Example
Output y is equal to 1 when the present state is 11. Here, the
output depends on the present state only and is independent of the
input. The two values inside each circle and separated by a slash
are for the present state and output.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
31. Mealy and Moore Models of Finite State Machines
There are two models of sequential circuits: the Mealy
model and the Moore model.
They diļ¬er only in the way the output is generated.
In the Mealy model, the output is a function of both the
present state and the input.
In the Moore model, the output is a function of only the
present state.
The two models of a sequential circuit are commonly referred
to as a ļ¬nite state machine, abbreviated FSM.
The Mealy model of a sequential circuit is referred to as a
Mealy FSM or Mealy machine.
The Moore model is referred to as a Moore FSM or Moore
machine.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
32. Mealy and Moore Models of Finite State Machines
Figure: Mealy Machine
Figure: Moore Machine
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
33. Mealy and Moore Models of Finite State Machines
The ļ¬rst example is an example for a Mealy machine
Output y is a function of both input x and the present state of
A and B.
The corresponding state diagram shows both the input and
output values, separated by a slash along the directed lines
between the states.
The last example is an example for a Moore machine
The output depends only on ļ¬ip-ļ¬op values, and that makes it
a function of the present state only.
The input value in the state diagram is labeled along the
directed line, but the output value is indicated inside the
circle together with the present state.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
34. State Reduction and Assignment
The design (synthesis) of a sequential circuit starts from a set
of speciļ¬cations and culminates in a logic diagram.
Two sequential circuits may exhibit the same inputoutput
behavior, but have a diļ¬erent number of internal states in
their state diagram.
The current section discusses certain properties of sequential
circuits that may simplify a design by reducing the number of
gates and ļ¬ip-ļ¬ops it uses.
Reducing the number of ļ¬ip-ļ¬ops reduces the cost of a circuit.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
35. State Reduction
The reduction in the number of ļ¬ip-ļ¬ops in a sequential
circuit is referred to as the state-reduction problem.
State-reduction algorithms are concerned with procedures for
reducing the number of states in a state table, while keeping
the external inputoutput requirements unchanged.
Since m ļ¬ip-ļ¬ops produce 2m states, a reduction in the
number of states may (or may not) result in a reduction in the
number of ļ¬ip-ļ¬ops.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
36. State Reduction: Example
Figure: State Diagram
In our example, only the inputoutput sequences are important;
the internal states are used merely to provide the required
sequences.
For that reason, the states marked inside the circles are
denoted by letter symbols instead of their binary values.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
37. State Reduction: Example
As an example, consider the input sequence 01010110100 starting
from the initial state a.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
38. State Reduction: Example
We now proceed to reduce the number of states for the above
example. First, we need the state table;
Figure: State Table
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
39. State Reduction: Example
Steps:
Two states are said to be equivalent if, for each member of
the set of inputs, they give exactly the same output and send
the circuit either to the same state or to an equivalent state.
When two states are equivalent, one of them can be removed
without altering the inputoutput relationships.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
40. State Reduction: Example
we look for two present states that go to the same next state and
have the same output for both input combinations. States e and g
are two such states.
Figure: Reducing the State Table
The row with present state g is removed, and stateg is replaced by
state e each time it occurs in the columns headed āNext State.ā
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
41. State Reduction: Example
states f and d are equivalent, and state f can be removed and
replaced by d.
Figure: Reduced state table
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
43. State Reduction: Example
This state diagram satisļ¬es the original inputoutput speciļ¬cations
and will produce the required output sequence for any given input
sequence.
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
44. State Assignment
Figure: Three possible binary state assignments
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
45. State Assignment
Figure: Reduced State Table with Binary Assignment 1
D.R.V.L.B Thambawita ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS