Datapath flow diagram for arithmetic, memory reference and branching instructions with 5 stages pipelined stages.

1. Five-stage Pipelined Datapath
1
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data 1
Read
data 2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Inst. Fetch Inst. Decode Exec Mem WB
02/08/2019 C.KARTHIKEYAN , AP/ECE

2. Example for lw instruction:
Instruction Fetch (IF)
2
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Instruction fetch
02/08/2019 C.KARTHIKEYAN , AP/ECE

3. Example for lw instruction:
Instruction Decode (ID)
3
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Instruction decode
02/08/2019 C.KARTHIKEYAN , AP/ECE

4. Example for lw instruction: Execution (EX)
4
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Execution
02/08/2019 C.KARTHIKEYAN , AP/ECE

5. Example for lw instruction: Memory (MEM)
5
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Memory
02/08/2019 C.KARTHIKEYAN , AP/ECE

6. Example for lw instruction: Writeback (WB)
6
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Writeback
02/08/2019 C.KARTHIKEYAN , AP/ECE

7. Example for sw instruction: Memory (MEM)
7
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Memory
02/08/2019 C.KARTHIKEYAN , AP/ECE

8. Example for sw instruction: Writeback (WB): do nothing
8
Instruction
memory
Address
4
32
0
Add
Add
result
Shift
left 2
Instruction
IF/ID EX/MEM MEM/WB
M
u
x
0
1
Add
PC
0
Write
data
M
u
x
1
Registers
Read
data1
Read
data2
Read
register 1
Read
register 2
16
Sign
extend
Write
register
Write
data
Read
data
1
ALU
result
M
u
x
ALU
Zero
ID/EX
Data
memory
Address
Writeback
02/08/2019 C.KARTHIKEYAN , AP/ECE

9. Datapath with Control
10
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
EX
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
IF: lw $10, 8($1)
02/08/2019 C.KARTHIKEYAN , AP/ECE

10. Datapath with Control
11
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
X
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
IF: sub $11, $2, $3 ID: lw $10, 8($1)
01
00
000 E
“lw”
02/08/2019 C.KARTHIKEYAN , AP/ECE

11. Datapath with Control
12
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
X
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
11
010
00E
ID: sub $11, $2, $3 EX: lw $10, 8($1)IF: and $12, $4, $5
1
0
10
000
1100
“sub”
02/08/2019 C.KARTHIKEYAN , AP/ECE

12. Datapath with Control
13
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
X
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
10
000
10E
EX: sub $11, $2, $3 MEM: lw $10, 8($1)ID: and $12, $4, $5
0
1
10
000
1100
IF: or $13, $6, $7
11
0
1
0
“and”
02/08/2019 C.KARTHIKEYAN , AP/ECE

13. Datapath with Control
14
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
X
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
10
000
10E
MEM: sub $11, .. WB: lw $10,
8($1)
EX: and $12, $4, $5
0
1
10
000
1100
ID: or $13, $6, $7
10
0
0
0
“or”
IF: add $14, $8, $9
1
1
02/08/2019 C.KARTHIKEYAN , AP/ECE

14. Datapath with Control
15
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
X
M
WB
M
WB
WB
IF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
10
000
10E
WB: sub $11, ..MEM: and $12…
0
1
10
000
1100
EX: or $13, $6, $7
10
0
0
0
“add”
ID: add $14, $8, $9
1
0
IF: xxxx
02/08/2019 C.KARTHIKEYAN , AP/ECE

15. Datapath with Control
16
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
M
WB
WB
IF/ID
PCSrc
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
10
000
10
WB: and $12…
0
1
MEM: or $13, ..
10
0
0
0
EX: add $14, $8, $9
1
0
IF: xxxx ID: xxxx
X
M
WB
ID/EX
E
02/08/2019 C.KARTHIKEYAN , AP/ECE

16. Datapath with Control
17
WB: or $13…
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
M
WB
WB
IF/ID
PCSrc
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
MEM: add $14, ..
10
0
0
0
EX: xxxx
1
0
IF: xxxx ID: xxxx
X
M
WB
ID/EX
E
02/08/2019 C.KARTHIKEYAN , AP/ECE

17. Datapath with Control
18
PC
Instruction
memory
Instruction
Add
Instruction
[20– 16]
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
[15– 0]
0
0
M
u
x
0
1
Add
Add
result
Registers
Write
register
Write
data
Read
data 1
Read
data 2
Read
register 1
Read
register 2
Sign
extend
M
u
x
1
ALU
result
Zero
Write
data
Read
data
M
u
x
1
ALU
control
Shift
left 2RegWrite
MemRead
Control
ALU
Instruction
[15– 11]
6
M
WB
WB
IF/ID
PCSrc
EX/MEM
MEM/WB
M
u
x
0
1
MemWrite
Address
Data
memory
Address
WB: add $14..MEM: xxxxEX: xxxx
1
0
IF: xxxx ID: xxxx
X
M
WB
ID/EX
E
02/08/2019 C.KARTHIKEYAN , AP/ECE

18. Forwarding (operand selection)
19
ALU
Data
Memory
Register
File
MUX
ID/EX EX/MEM MEM/WB
MUXMUX
Forwarding
Unit
02/08/2019 C.KARTHIKEYAN , AP/ECE

19. Forwarding (operand propagation)
20
ALU
Data
Memory
Register
File
MUX
ID/EX EX/MEM MEM/WB
MUXMUX
Forwarding
Unit
Rt
Rs
MUX
Rd
Rt
EX/MEM Rd
MEM/WB Rd
02/08/2019 C.KARTHIKEYAN , AP/ECE

20. Data Hazard Even with Forwarding
21
Time (clock cycles)
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
or r8,r1,r9
Reg
ALU
DMemIfetch Reg
Reg
ALU
DMemIfetch Reg
Reg
ALU
DMemIfetch Reg
Reg
ALU
DMemIfetch Reg
Forward backward in time… no way!! (or way?)
Instructionorder
02/08/2019 C.KARTHIKEYAN , AP/ECE

21. Data Hazard Even with Forwarding
22
Time (clock cycles)
or r8,r1,r9
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
Reg
ALU
DMemIfetch Reg
RegIfetch
ALU
DMem RegBubble
Ifetch
ALU
DMem RegBubble Reg
Ifetch
ALU
DMemBubble Reg
Need “pipeline interlock” (or stall) to stop instructions
from issuing. How is this detected?
Instructionorder
02/08/2019 C.KARTHIKEYAN , AP/ECE

22. Hazard Detection Unit
• Stall by letting an instruction that won’t write anything go forward
• Stall the pipeline if ID/EX is a load, and (rt=IF/ID.rs or rt=IF/ID.rt)
23
PC
Instruction
memory
Registers
M
u
x
M
u
x
M
u
x
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
Data
memory
M
u
x
Hazard
detection
unit
Forwarding
unit
0
M
u
x
IF/ID
Instruction
ID/EX.MemRead
IF/IDWrite
PCWrite
ID/EX.RegisterRt
IF/ID.RegisterRd
IF/ID.RegisterRt
IF/ID.RegisterRt
IF/ID.RegisterRs
Rt
Rs
Rd
Rt
EX/MEM.RegisterRd
MEM/WB.RegisterRd
02/08/2019 C.KARTHIKEYAN , AP/ECE

23. Code Rescheduling to Avoid Load Hazards
Fast code:
LW Rb,b
LW Rc,c
LW Re,e
ADD Ra,Rb,Rc
LW Rf,f
SW a,Ra
SUB Rd,Re,Rf
SW d,Rd
24
Try producing fast code for
a = b + c;
d = e – f;
assuming a, b, c, d ,e, and f in memory.
Slow code:
LW Rb,b
LW Rc,c
ADD Ra,Rb,Rc
SW a,Ra
LW Re,e
LW Rf,f
SUB Rd,Re,Rf
SW d,Rd
Compiler optimizes for performance. Hardware checks for safety.
02/08/2019 C.KARTHIKEYAN , AP/ECE