RMD Engineering College Professor Details and MIPS Instruction Set Overview

13-11-2020 1Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Contact E-mail:
acdean@rmd.ac.in
kkthyagharajan@yahoo.com
kkthyagharajan@gmail.com
Dr. K.K. THYAGHARAJAN
Professor & Dean (Academic)
Department of Electronics and Communication Engineering
RMD ENGINEERING COLLEGE
Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Instruction Formats & Addressing Modes
Click on the following links to view videos
https://youtu.be/DcMM_dIxWEE
https://youtu.be/JoSONsTuopk

Please go to
https://thyagharajan.blogspot.com/
Click on the ‘Open’ button or the link provided there. It will take
you to Google drive. Download the content of the ‘Computer
Architecture’ session conducted on 4-7-2020.
You can also get 2-marks questions and answers, assignment
problems and important Part-B questions from that blog.

PART - 1
MIPS-Instruction Set

MIPS-Instruction Set
Why should you study this topic?
 To understand MIPS Assembly language
 In future you will be studying Microprocessor and Microcontroller assembly
languages and processors for IoT. If you study MIPS assembly language
now, it will help you to understand other assembly languages.
 If you are going to study VLSI, the architecture studied here will help you to
design your own microprocessor.
 MIPS – Microprocessor without Interlocked Pipeline Stages – It is a 32 bit
microprocessor Architecture
 MIPS is a RISC (Reduced Instruction Set Computer) architecture
 High level language instructions are translated to Assembly language and these
assembly instructions are translated to machine codes. Only these machine codes
can be understood by the processor or computer.
 Instruction format and addressing modes help to translate assembly language to
machine code

MIPS Instruction Set
Arithmetic Instructions
Logical Instructions
Data Transfer Instructions
Conditional Instructions
Unconditional Instructions
Types of Instructions / Operations

Instruction: add $s1,$s2,$s3
Operation: $s1  $s2 + $s3
Explanation: data stored in the registers s2 and s3 are added and the
result is stored in register s1
Here $s2 and $s3 are used as source registers – content will be read from
$s1 is used as destination register – content i.e. result is written into
Arithmetic Instructions - Examples
Instruction: sub $s1,$s2,$s3
Operation: $s1  $s2 - $s3
Explanation: data stored in the register s3 is subtracted from data stored
in register s3 and the result is stored in register s1
Here $s2 and $s3 are used as source registers – content will be read from

Instruction: addi $s1,$s2,20
Operation: $s1  $s2 +20
Explanation: data 20 is given directly in the instruction itself (so it is called as
immediate data). This immediate data is added with the content (data) stored
in the register s2 and the result is stored in register s1
Here $s2 is used as source register – content will be read from
Arithmetic Instructions (Immediate Data) - Examples
Instruction: subi $s1,$s2,20
Operation: $s1  $s2 - 20
Explanation: data 20 is given directly in the instruction itself (so it is called as
immediate data). This immediate data is subtracted from the content (data)
stored in the register s2 and the result is stored in register s1
Here $s2 is used as source register – content will be read from

 In these examples $s1, $s2, $s3, 20 are called as operands.
 Since data are read from $s2, $s3 they are source operands.
 Since data (result) is written into $s1 it is destination operand.
 The operations to be performed is indicated by symbolic code add,
addi, sub and subi. These operation codes are represented by 6-bit
operation code. So, we will have 64 (26) operations.
 All these instructions are in MIPS Assembly language
 32 registers are available - $s0 - $s7, $t0 - $t9, $a0 - $a3 (arguments
to function), $v0 & $v1 (values returned by functions), $gp, $fp
(frame pointer or $30), $sp (stack pointer or $29), $ra, $at, $zero.
The length of each register is 32 bits
 To represent these registers we use 5-bit address (25=32)
 $s0 (register 0 also denoted as $0) is always has value zero. 2
registers HI & LO stores the results of multiply and divide
What do you have to Understand?

Instruction: and $s1,$s2,$s3  bitwise AND operation (if both bits are 1 then
result is 1)
Operation: $s1  $s2 & $s3
Explanation: data stored in the registers s2 is Anded with s3 bit by bit and the
S2  0000 1111 0100 0000 1010 0101 1001 0011
S3  0000 1001 0010 0000 0010 0101 1001 0001
S1  0000 1001 0000 0000 0010 0101 1001 0001
Logical Instructions - Examples
Instruction: andi $s1,$s2,20  AND immediate
Operation: $s1  $s2 & 20
Explanation: data stored in the registers s2 is Anded with immediate data 20 bit by bit
and the result is stored in register s1 (if both bits are 1 then result is 1)
S2  0000 1111 0100 0000 1010 0101 1001 0011
20  0000 0000 0000 0000 0000 0000 0001 0100
S1  0000 0000 0000 0000 0000 0000 0001 0000

Instruction: or $s1,$s2,$s3  bitwise OR operation
Operation: $s1  $s2 OR $s3
Explanation: data stored in the registers s2 is ORed with s3 bit by bit and the
S2  0000 1111 0100 0000 1010 0101 1001 0011
S3  0000 1001 0010 0000 0010 0101 1001 0001
S1  0000 1111 0110 0000 1010 0101 1001 0001
Instruction: ori $s1,$s2,20
OR immediate  bitwise OR operation with immediate data
Operation: $s1  $s2 OR 20
Instruction: nor $s1,$s2,$s3  NOR
Operation: $s1  $s2 NOR $s3

Instruction: sll $s1,$s2,10  shift left logical
Operation: $s1  $s2 << 10
Explanation: the bits stored in the registers s2 is shifted by 10 positions left. The left most bit is discarded and
the right most bit is replaced by zero after each bit shift. The result is stored in register s1
S2  0000 1111 0100 0000 1010 0101 1001 0011
S2  0000 1111 0100 0000 1010 0101 1001 0011
S1  00 0000 1010 0101 1001 001100 0000 0000
Instruction: srl $s1,$s2,10  shift right logical
Operation: $s1  $s2 >> 10
Explanation: the bits stored in the registers s2 is shifted by 10 positions right. The right most bit is
discarded and the left most bit is replaced by zero after each bit shift. The result is stored in register s1
S2  0000 1111 0100 0000 1010 0101 1001 0011
S2  0000 1111 0100 0000 1010 0101 1001 0011
S1  0000 0000 0000 0011 1101 0000 0010 10 01

$s1 1234
Before
Execution
6
7
8
9
Memory
1000
1001
1002
1003
Address
$s1 9876
After
Execution of
load word
lw
Register
1234
9876
Data Transfer Instruction Load

$s1 1234
Before
Execution
4
3
2
1
Memory
1000
1001
1002
1003
Address
$s1 1234
After
Execution of
store word
sw
Register
1234
Data Transfer Instruction Store

Instruction: lw $s1, 20($s2)
lw  load word (32-bit word)
Operation: $s1  memory(20+$s2)
Explanation: data available in the memory address (20 + $s2) will be loaded
(copied) into register s1
Here register $s2 provides a 32-bit value & 20 is another 32-bit value provided in the instruction
itself. Both are added to get the actual memory address (32-bit value).
The 32-bit data (4 bytes) pointed by this address will be loaded into $s1
Data Transfer Instructions- Examples
Instruction: sw $s1, 20($s2)
sw  store word (32-bit word)
Operation: memory(20+$s2)  $s1
Explanation: data available in the register s1 will be stored in to the memory
pointed by the address (20 + $s2)
Here register $s2 provides a 32-bit value & 20 is another 32-bit value provided in the
instruction itself. Both are added to get the actual memory address (32-bit value)

Instruction: lb $s1, 20($s2)
lb  load byte
Operation: $s1  memory(20+$s2)
Explanation: data available in the memory address (20 + $s2) will be loaded
(copied) into register s1
Here register $s2 provides a 32-bit value & 20 is another 32-bit value provided in the instruction
itself. Both are added to get the actual memory address (32-bit value).
The 8-bit data (1 byte) pointed by this address will be loaded into $s1
Data Transfer Instructions- Examples
Instruction: sb $s1, 20($s2)
sb  store byte
Operation: memory(20+$s2)  $s1
Explanation: data (one byte) available in the register s1 will be stored in to the
memory pointed by the address (20 + $s2)
lh  load half word (16-bit word)
sh  store half word (16-bit word)

 Reading from the memory is the load operation
 Writing into the memory is the store operation
 MIPS can access (read from or write into) memory only to transfer data.
 The instructions can read data from memory and put it in a register (called
as load)
OR
 The instructions can store the data available in a register into the memory
(called as store)
 The memory location is pointed (or accessed) by giving a 16-bit address
directly (immediate value) or indirectly (using a register ) in the instruction.
What do you have to understand?

Instruction: beq $s1, $s2,25
beq  branch on equal
Operation: if ($s1 == $s2) go to the address PC+4 + (25*4) and continue
execution - omit 25 instructions and continue execution
Explanation: PC is the program counter which points the starting address of
the current instruction. Each instruction is a 4-byte instruction. So, the next
instruction will be available at the address PC+4
The immediate value 25 indicates that the processor has to skip 25
instructions i.e. 25*4 locations and continue execution
So, the starting address for the next instruction is calculated as PC+4 + (25*4)
Conditional Instructions - Branch
Instruction: bne $s1, $s2,25
bne  branch on not equal
Operation: if ($s1 != $s2) go to the address PC+4 + (25*4) and continue
execution

Instruction: slt $s1, $s2,$s3
slt  set on less than
Operation: if ($s2 < $s3) then set $s1 to 1 else set $s1 to 0
Conditional Instructions
Instruction: slti $s1, $s2, 20
slti  set on less than immediate value
Operation: if ($s2 < 20) then set $s1 to 1 else set $s1 to 0
slti  set on less than the immediate value (data) 20

Instruction: j 2500
j  jump
Operation: go to 2500th instruction i.e. go to the address (2500*4) and
continue execution
Explanation: Each instruction is a 4-byte instruction. So, The
immediate value 2500 indicates that the processor has to jump to the
address 2500*4 = 10000 and continue execution
The maximum value that can be used in the place of 2500 is 226 i.e. 26
bits are used for this purpose.
Unconditional jump Instructions
Instruction: jr $ra
jr  jump register
Operation: return to the address pointed by the value stored in
the register $ra

1. When an instruction has three operands generally
the 2nd and 3rd operands are the source operands.
But in beq and bne the 1st and 2nd operands act as
source operands.
2. When immediate value (data or address) is given in
the instruction it will be last operand.
What do you have to understand?

PART - 2
Writing Programs

Programming Exercises
Remember the following MIPS assembly language instructions to write simple programs
1. add $s1,$s2,$s3 #content (data) available in the register s2 will be added to the
# content available in the register s3 and the result is stored in the register s1.
2. sub $s1,$s2,$s3 # s2-s3 is calculated and the result is stored in s1
3. lw $t0, 32($s3) # 4 byte word pointed by the address 32+s3 will be loaded into register t0
4. sll $t1, $t2 ,4 # shift left the content of register t2 by 4 bits and store the result in register t1.
5. mul $t1, $t0, 25 # data stored in the register t0 is multiplied by 25 and the result is stored in t1
6. div $t1, $t0, 4 # t0/4 is calculated and the result is stored in register t1

Program 1: For the following C statement, write a minimal sequence of MIPS
assembly instructions that does the identical operation. Assume $s0 = f, $s1 = g,
$s2 = h, $s3 = i, and $s4 = j.
f = (g+h) – (i+j)
Hint: Store the value g + h in the temporary register $t0 and I + j in $t1.
Solution:
add $t0, $s1,$s2 # contents of registers s1 (g) & s2 (h) are added and the
# result is store in t0
add $t1, $s3,$s4 # contents of registers s3 & s4 are added and the result is
# store in t1
sub $s0,$to,$t1 # t0 - t1 is calculated and the result is stored in register s0

Program 2: Assume that ‘A’ is an array of 100 words and the compiler has associated the variables ‘g’ and
‘h’ with registers $s1 and $s2 respectively. Let us assume that the starting (base address) of the array is in
$s3. Translate the following ‘C’ instruction to MIPS assembly language instructions.
g = h + A(8); # 8 indicates the 8th word in the table
Explanation: First we have to bring the 8th word from the array and store it in a temporary register
$t0. Register s3 has the starting address of the array (e.g. 0), and each word is of length 4 bytes, and
only one byte is stored in each memory address. So, to bring the 8th word , the address is 8 x4 = 32.
To read from the memory we have to use ‘lw‘ (load word) instruction
Solution:
lw $t0, 32($s3) # starting address 0 is in register s3 and the offset address 32 (8x4) is given
# as immediate value in the instruction. This instruction brings a 4 byte
#word starting from the address 32 of the memory and stores in register t0
add $s1, $s2,$t0 # contents of registers s2 (h) & t0 are added and the result is store in s1 (g)

Program 3: For the following C statement, write a minimal sequence of MIPS assembly
instructions that does the identical operation. Assume $t1 = A, $t2 = B, and $s1 is the base
address of C.
A = C[0] << 4; #here index 0 indicates that first word in the array has to be shifted left
Explanation: We have to bring the 1st word (index=0) from the array and store it in a temporary register
$t1. Since register s1 has the base address, it is the starting address of the array. Each word Is of length 4
bytes, and only one byte is stored in each memory address. The first word in the array has always zero
offset address. To read from the memory we have to use ‘lw‘ (load word) instruction
Solution:
lw $t2, 0($s1) # starting address of the table is in register s1 and the offset address 0 is given
# as immediate value in the instruction. This instruction brings a 4 byte
#word from memory and stores in register t2
sll $t1, $t2 ,4 # shift left the content of register t2 by 4 bits and store the result in register t1.

Program 4: Write a sequence of instructions to evaluate (x + 15 - y) * 25 / 4
assume that the values x and y are obtained from memory
Hint: Since the actual addresses of x and y are not given, you can use the symbols as it is in the
program. The ‘x’ here will be accessed using a register and an offset value but it is not specified in
the instruction explicitly. Similarly ‘y’ will also use a register and an offset address.
Solution:
lw $t0, x # load x from memory i.e. any register and offset value may be used
lw $t1, y # load y from memory
add $t0, $t0, 5 # x +15
sub $t0, $t0, $t1 # x + 15 - y
mul $t0, $t0, 25 # (x + 15 - y)*25
div $t0, $t0, 4 # (x + 5 - y)*25/4

PART - 3
MIPS INSTRUCTION FORMAT

Instruction Format
R-Format Register Type Arithmetic & Logical Instructions
I-Format Immediate Type Data transfer and branch instructions and
some Arithmetic & Logical Instructions
J-Format Jump type Jump instructions
Instruction format includes an opcode (Operation code) and zero
or more operands. It defines how the bits are assigned to the
opcode and operands.

add $s1,$s2,$s3
lw $t1, 100 ($s0)
beq $s1,$t1,100
j 2500
I-Type:
R-type:
J-type:
Example
Instructions
addi $s1,$s2,5
address offset /data
funct
op rs rt
31 25 20 15 0
31 25 20 15 5
0
op rs rt rd shamt
10
31 25 0
op target address
Instruction Format
5 bits 6 bits5 bits5 bits5 bits6 bits
op – Opcode (operation code)
shamt – shift amount
funct - function
rs – source register
rd – destination register –used to store results
rt – temporary register – can be used as rs or rd

 op (operation code) field always in bits 31-26 (6 bits)
 address of registers is specified by the rs field bits 25-21 (5bits)
 rs (register source) is the base register for lw and sw.
 address of registers specified by rt (register temporary) field
(bits 20-16) are always read except for lw instructions.
 For lw the register specified by bits 20-16 (rt field) is written
 address of registers specified by rd (register destination) field
(bits 15-11) are written when used in R-type instructions
 Address offset for beq, lw, and sw (I-Type) is always provided
in bits 15-0
 26-bit target address for jump instruction is obtained by bits
25-0
Instruction Formats

PART - 4
Addressing Modes

Addressing Modes
Addressing modes specify how the operands in an instruction are
to be specified or interpreted.
There are five types of addressing modes
1. Register addressing mode
2. Immediate addressing mode
3. Base / Displacement / Indirect addressing mode
4. PC (Program Counter) -relative addressing mode
5. Pseudo direct addressing mode

Addressing Modes
Example: add $s1,$s2,$s3
The values available in the registers s2 and s3 are added and the result is stored in
the register s1
1. Register Addressing Mode:
$s2 is the source register (rs) which hold one value (data)
$s3 holds another data (you can also use a temporary register ($t1) for this purpose)
These two data are added and the result is stored the register s1
The value 5 is called immediate data because it is given in the instruction itself.
It should be represented using 16 bits according to I-format.
The 16-bit immediate value used here is interpreted as data because add instruction will require
two data and it does not require any immediate value as address
shamt  shift amount is not used by this instruction. It will be used in shift logical operations
funct  function is not used here
R-Format
0
funct
31 25 20 15 5
op rs rt rd shamt
10
Explanation: funct
31 25 20 15 5
op $s2 $s3 $s1 shamt
10 0

Addressing Modes
Example: addi $s1,$s0,5  add immediate
The value (data) 5 is added with the data stored in the register s0 and the
result is stored in the register s1
2. Immediate Addressing Mode:
$s0 is the source register (rs)
$s1 is used to hold the result of addition (the 6 bits of temporary register rt are used
for this purpose).
The value 5 is called immediate data because it is given in the instruction itself.
It should be represented using 16 bits according to I-format.
The 16-bit immediate value used here is interpreted as data because add instruction
will require two data and it does not require any immediate value as address
16-bit dataop rs rt
31 25 20 15 0
I-Format
0000op $s0 $s1 0000 00000101

Addressing Modes
Example: lw $s1, 32($s3)  load word
The value 32 is added with the value stored in the register s3 and this value is used
as address to read the data from the memory. This data is stored in the register s1.
s3 is used as source register which gives part of the address. And the 16-bit value
(bit 0 to 15) given in the instruction itself provides remaining part of the address.
These two addresses are added to provide an effective address.
The data taken from this address will be stored in the temporary (or destination)
register (here register s1) specified by the rt field of the instruction
3. Base / Displacement / Indirect addressing mode:
16-bit addressop rs rt
31 25 20 15 0
I-Format

Base / Displacement / Indirect addressing mode contd. . ..
4
3
2
1
Memory
100
101
102
103
Address
31 25 20 15 0
rs = $s3
68 +
rt = $s1 4 bytes 1234
$s3 $s1lw 32
lw $s1, 32($s3)

 The constant value (address) given in the instruction
is also known as displacement. So this addressing is
also called as displacement addressing.
 Since part of the address is given by a register (here
s3) indirectly, this addressing is also called as indirect
addressing.
 The source register (s3) here acts as base register and
it can be used to access the values in a table.
What you have to understand?
Base / Displacement / Indirect addressing mode contd. . ..

Addressing Modes
Example: bne $s0, $s1, 100  branch on not equal
If $s0 != $s1 go to the address PC+4+(100*4) and continue to execute the
program from there.
 PC is the program counter which holds the address of the current
instruction being executed. To execute next immediate instruction, this PC
will be incremented by 4.
 Here 100 is a 16-bit value and it is used as address. So the program
execution is transferred relative to PC value.
 This is not a data transfer instruction it is a program control instruction.
4. PC-relative addressing mode:
31 25 20 15 0
I-Format

PC-relative addressing mode contd. . . .
4
3
2
1
Before bne
Memory
1001
1000
Address
31 25 20 15 0
PC
1000 +
$s0 $s1bne 100
bne $s0, $s1, 100
1404
1403
1300

Addressing Modes
Example: j 2500  jump
Here 2500 is multiplied by 4 and this value is concatenated with
the upper 6 bits of the program counter (PC) to get the effective
address.
The execution is transferred to this effective address
5. Pseudo direct addressing mode:
PC
1234 :
2500
J 2500
31 25 0
op target address
2500 x 4
PC:10000
Effective address

PART - 5
Translating Assembly Instruction
to Machine Instruction

Translating Assembly Instruction to Machine Instruction
 There are 32 registers in MIPS architecture. They can
be addressed (or accessed) by using the symbols
$s0-$s7, $t0-$t7 etc. They can also be addressed by
their address i.e. from 0 to 31.
 To address 32 registers we use 5 bits (25=32) in the
instruction format.
 Registers t0-t7 are located at addresses 8-15
 Registers so-s7 are located at addresses 16-23
 Other registers occupy the remaining 16 addresses.
What do you have to Understand?

Remember the addresses (decimal value) of some of the important registers
and the opcodes (decimal value) for some of the important instructions. If
you need opcodes for all instructions search in Google with trems “MIPS
Instruction Reference”
What do you have to Remember?
Register $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7
address 8 9 10 11 12 13 14 15
Register $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7
address 16 17 18 19 20 21 22 23
Operation(op) Add/
sub
addi lw sw beq bne j
Opcode 0 8 35 43 4 5 2
$t8 $t9
24 25

Problem: Find out the machine code for the instruction add $to, $s1,$s2
Analyze: Since this instruction uses only registers, it comes under R-format. Refer instruction
formats (slide 30). Note the number of bits used for each field. First and last fields use 6 bits and
remaining fields use 5 bits.
The ‘funct’ value is 32 for ‘add ‘
and 34 for ‘sub’ operation
Refer previous slide (no. 44) to get the address of registers. For add, funct =32
0
funct
31 25 20 15 5
op rs rt rd shamt
10
OP rs rt rd shamt funct
add $s1 $s2 $t0 0 32
0 17 18 8 0 32
0
100000
31 25 20 15 5
000000 10001 10010 01000 00000
10
Values encoded to binary form–
Machine Instruction
Values in decimal form

Translating Machine Instruction to Assembly Instruction
Problem: What is the assembly language statement corresponding to this machine
instruction? 0000 0010 0001 0000 1000 0000 0010 0000 base 2
Analysis: Take the least significant 6 bits 0000 00  This indicates that the operation is add.
For this operation the most significant 6 bits are also 000000 . So the format is R-format.
It is given by
The remaining 20 bits are divided into four fields with 5 bits in each field as given
below. Register 16 is $s0 (refer slide 41)
0
funct
31 25 20 15 5
op rs rt rd shamt
10
OP rs rt rd shamt funct
000000 10000 10000 10000 00000 100000
add 16 16 16 0 0
So the instruction is
add rd, rs, rt i.e.
add $s0, $s0,$s0
Contents of register s0 is
added with itself and the
result is stored in s0

RMD Engineering College Professor Details and MIPS Instruction Set Overview

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