Basics of Intel 8086 Processor- Its features, Pin discription, Modes..

1. 8086- Introduction
by vinod k dept of electronics

2. 2
Intel 8086 Microprocessor
Key Features:
• Released by Intel in 1978
• Produced from 1978 to 1990s
• A 16-bit microprocessor chip.
• Max. CPU clock rate :
5 MHz to 10 MHz
• Package: 40 pin DIP
Fig1:Intel 8086 Microprocessor

3. 3
8086 CPU Chip
Fig1: 8086 CPU Chip in DIP Package Fig2: CPU Chip

4. 8086- Pin Diagram

5. Pin Details
AD0- AD15 : Bideirectional Address / Data Bus
A16- A19/ S3- S0 : Higher order address bus/ Segment identifier signals

6. Multiplex of Data and Address Lines
• Address lines A0-A7 and Data lines D0-D7 are
multiplexed in 8088. These lines are labelled as AD0-
AD7.
– By multiplexed we mean that the same pin carries
an address bit at one time and the data bit another
time.

7. Multiplex of Data and Address Lines
• Address lines A0-A15 and Data lines D0-D15 are multiplexed
in 8086. These lines are labeled as AD0-AD15.
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086

8. Minimum-mode and Maximum-mode
• 8088 and 8086 microprocessors can
be configured to work in either of the
two modes: the minimum mode and
the maximum mode
 Minimum mode:
 Pull MN/MX to logic 1
 Typically smaller systems and contains
a single microprocessor
 Cheaper since all control signals for
memory and I/O are generated by the
microprocessor.
 Maximum mode
 Pull MN/MX logic 0
 Larger systems with more than one
processor (designed to be used when a
coprocessor (8087) exists in the system)
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086
Lost Signals in
Max Mode

9. Minimum-mode and Maximum-mode
Signals
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
RQ/GT0
RQ/GT1
QS0
READY
RESET
BHE/S7
MN/MX
RD
LOCK
S2
S1
S0
QS1
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086
Max Mode
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086
Min Mode
Vcc GND

10. 8086
CPU
F/C
AEN1
AEN2
Clock
generator
+5V
RES
Wait-State
Generator
CLK
READY
RESET
M/IO
INTA
RD
WR
PCLK
MN/MX +5V
STB
OE
8282
Latch
ALE
AD0-AD15
A16-A19
BHE BHE
D0 - D15
8286
DT/R
DEN
T
OE
16
A0 - A19
Address Bus
Control
Bus
8086 System Minimum mode

11. 8086
CPU
Clock
generator
Wait-State
Generator
CLK
READY
RESET
MN/MX
AD0-AD15
A16-A19 BHE
STB
OE
8282
Latch
A0 - A19
Address Bus
+5V
RES
S0
S1
S2
CLK
S0
S1
S2
DATA
8286
Transceiver
T
OE
ALE
Gnd
DEN
DT/R
MRDC
MWTC
IORC
IOWC
AIOWC
AMWC
INTA
8288
Bus
Controller
8086 System Maximum Mode

12. Description of the Pins
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
RQ/GT0
RQ/GT1
QS0
READY
RESET
BHE/S7
MN/MX
RD
LOCK
S2
S1
S0
QS1
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086
Max Mode
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
AD15
A16/S3
A17/S4
A18/S5
A19/S6
HOLD
HLDA
ALE
READY
RESET
BHE/S7
MN/MX
RD
WR
M/IO
DT/R
DEN
INTA
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
8086
Min Mode
Vcc GND

13. CPU component Contents
Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty
RESET Operation results

14. AD0 – AD15
Address
Data
AD0 - AD15: Address Data Bus

15. A17/S4 A16/S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access
A17/S4, A16/S3 Address/Status

16. A18/S5: The status of the
interrupt enable flag bit is updated
at the beginning of each cycle. The status of the flag
is indicated through this pin
A19/S6: When Low, it indicates that 8086 is in control
of the bus. During a "Hold acknowledge" clock
period, the 8086 tri-states the S6 pin and thus allows
another bus master to take control of the status bus.
A19/S6, A18/S5 Address/Status

17. S2 S1 S0 Characteristics
0 0 0
Interrupt
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
S0, S1 and S2 Signals

18. QS1 QS1 Characteristics
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
QS1 and QS2 Signals

19. IO/M DT/R SSO CHARACTERISTICS
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
1 0 0 Interrupt Acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
Read Write Control Signals

20. THANKS