This document provides instruction details for the TMS320C5X processor. It describes instructions like ADD, SUB, AND, OR and their syntax, operands, status bit effects, and examples. For each instruction, it gives the execution flow, addressing modes, and how they affect and are affected by status bits. Examples with before and after memory and register contents are provided to illustrate the instruction functionality.

1. Unit III
TMS320C5X
INSTRUCTIONS
By
Dr. Sudhir Shelke
Page 1 of 136
Dr Sudhir Shelke

2. ADD
Syntax:
Direct : ADD dma [ ,shift ]
Indirect : ADD {ind} [ ,shift [,ARn]]
Short Immediate : ADD #K
Long Immediate : ADD #lk
Operands:
d a
shift
k
- lk
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 2 of 136
Dr Sudhir Shelke

3. Execution:-
Direct or Indirect Addressing
PC + → PC
(ACC) + ((dma) x 2shift)
Short Immediate Addressing
PC + → PC
ACC + K → ACC
Long Immediate Addressing
PC + → PC
(ACC) + (( lk ) x 2shift → ACC
ADD
Page 3 of 136
Dr Sudhir Shelke

4. ADD
Status Bits:-
Description:-
If Direct , Indirect or Long Immediate addressing is used , the contents of the
data memory address (dma) or a 16 bit constant are shifted as defined by the
shift code & added to the contents of ACC. The result of is stored in ACC.
Affected By Affects Addressing Mode
OVM & SXM C & OV Direct/Indirect
OVM C & OV Short Immediate
OVM & SXM C & OV Long Immediate
Page 4 of 136
Dr Sudhir Shelke

5. ADD
EXAMPLES:-
1. ADD DAT1, 1 ; (DP = 6) Direct Addressing
Before Instruction After Instruction
0001h
0X 0000 0002 h 0000 0004h
0001hData Memory
0301h
Data Memory
0301h
ACC ACC
C C
Page 5 of 136
Dr Sudhir Shelke

6. ADD
2. ADD *+ , 0, AR0 Indirect Addressing
Before Instruction After Instruction
0002h 0002hData Memory
0302h
Data Memory
0302h
0X 0000 0002 h 0000 0004hACC ACC
C C
4
0302h AR4
ARP
0303h
0ARP
AR4
Page 6 of 136
Dr Sudhir Shelke

7. ADD
3. ADD #1h Short Immediate
Before Instruction After Instruction
0X 0000 0002 h 0000 0003hACC ACC
C C
Page 7 of 136
Dr Sudhir Shelke

8. ADD
4. ADD #1111h , 1 Long Immediate Addressing
Before Instruction After Instruction
0X 0000 0002 h 0000 2224hACC ACC
C C
Page 8 of 136
Dr Sudhir Shelke

9. SUB
Syntax:
Direct : SUB dma [ ,shift ]
Indirect : SUB {ind} [ ,shift [,ARn]]
Short Immediate : SUB #K
Long Immediate : SUB #lk
Operands:
d a
shift
k
- lk
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 9 of 136
Dr Sudhir Shelke

10. Execution:-
Direct or Indirect Addressing
PC + → PC
(ACC) - ((dma) x 2shift)
Short Immediate Addressing
PC + → PC
(ACC) - K → ACC
Long Immediate Addressing
PC + → PC
(ACC) - (( lk ) x 2shift → ACC
SUB
Page 10 of 136
Dr Sudhir Shelke

11. SUB
Status Bits:-
Description:-
If Direct , Indirect or Long Immediate addressing is used , the contents of the
data memory address (dma) or a 16 bit constant are shifted as defined by the
shift code & subtracted from the contents of ACC. The result of is stored in
ACC.
Affected By Affects Addressing Mode
OVM & SXM C & OV Direct/Indirect
OVM C & OV Short Immediate
OVM & SXM C & OV Long Immediate
Page 11 of 136
Dr Sudhir Shelke

12. SUB
EXAMPLES:-
1. SUB DAT80 ; (DP = 8) Direct Addressing
Before Instruction After Instruction
0011h
1X 0000 0024 h 0000 0013h
0011h
Data Memory
0450h
Data Memory
0450h
ACC ACC
C C
Page 12 of 136
Dr Sudhir Shelke

13. SUB
2. SUB *- , 1 , AR0 Indirect Addressing
Before Instruction After Instruction
0004h 0004hData Memory
0301h
Data Memory
0301h
1X 0000 0009 h 0000 0001hACC ACC
C C
4
0301h AR4
ARP
0300h
0ARP
AR4
After Instruction
0004hData Memory
0301h
AR4
ARP
0300h
0
Page 13 of 136
Dr Sudhir Shelke

14. SUB
3. SUB #8h Short Immediate
Before Instruction After Instruction
0X 0000 0007 h FFFF FFFF hACC ACC
C C
Page 14 of 136
Dr Sudhir Shelke

15. SUB
4. SUB #0FFFh , 4 Long Immediate Addressing
Before Instruction After Instruction
1X 0000 FFFFh 0000 000FhACC ACC
C C
Page 15 of 136
Dr Sudhir Shelke

16. ADDC
Syntax :
Direct : ADDC dma
Indirect: ADDC {ind}[,Arn]
Operands :
d a
Ind :- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Execution:-
PC + → PC
ACC + d a + → ACC
Page 16 of 136
Dr Sudhir Shelke

17. ADDC
Status Bits:-
Examples :-
1. ADDC DAT0 ; (DP = 6)
Affected By Affects
OVM C & OV
Before Instruction After Instruction
0004h 0004hData Memory
0300h
Data Memory
0300h
01 0000 0013 h 0000 0018hACC ACC
C C
Page 17 of 136
Dr Sudhir Shelke

18. ADDC
2. ADDC *- , AR4 Indirect Addressing
Before Instruction After Instruction
0000h 0000hData Memory
0300h
Data Memory
0300h
11 FFFF FFFFh 0000 0000hACC ACC
C C
0300h AR0
ARP
02FFh
4ARP
AR0
Before Instruction
0ARP
Page 18 of 136
Dr Sudhir Shelke

19. SUBB
Syntax :
Direct : SUBB dma
Indirect: SUBB {ind}[,Arn]
Operands :
d a
Ind :- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Execution:-
PC + → PC
(ACC) - (dma) - logi al i versio of C → ACC
Page 19 of 136
Dr Sudhir Shelke

20. SUBB
Status Bits:-
Examples :-
1. SUBB DAT5 ; (DP = 8)
Affected By Affects
OVM C & OV
Before Instruction After Instruction
0006h 0006hData Memory
0405h
Data Memory
0405h
00 0000 0006 h FFFF FFFF hACC ACC
C C
Before Instruction
Data Memory
0405h
Page 20 of 136
Dr Sudhir Shelke

21. SUBB
2. SUBB * Indirect Addressing
Before Instruction After Instruction
0002h 0002hData Memory
0301h
Data Memory
0301h
11 0000 0004 h 0000 0002hACC ACC
C C
6
0301h AR6
ARP
0301h
6ARP
AR6
Page 21 of 136
Dr Sudhir Shelke

22. AND
Syntax:-
Direct : AND dma
Indirect : AND {ind}[,ARn]
Long Immediate : AND #lk [,shift]
Operands:-
d a
Ind :- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Lk :- 16 bit constant
shift
Page 22 of 136
Dr Sudhir Shelke

23. AND
Status Bits:- Not Affected
Execution:-
Direct/Indirect Addressing
PC + → PC
ACC(15- AND d a → ACC -0)
→ ACC -16)
Long Immediate Addressing
PC + → PC
ACC(31-0) AND (lk x 2shift → ACC
Page 23 of 136
Dr Sudhir Shelke

24. AND
EXAMPLES:-
1. AND DAT16 ; (DP = 4) Direct Addressing
Before Instruction After Instruction
00FF h 00FF hData Memory
0210h
Data Memory
0210h
1234 5678 h 0000 0078 hACC ACC
Page 24 of 136
Dr Sudhir Shelke

25. AND
2. AND * Indirect Addressing
Before Instruction After Instruction
FF00 h FF00 hData Memory
0301h
Data Memory
0301h
1234 5678 h 0000 5600 hACC ACC
0
0301h AR0
ARP
0301h
0ARP
AR0
Page 25 of 136
Dr Sudhir Shelke

26. AND
Before Instruction After Instruction
1234 5678 h 0000 0670hACC ACC
3. AND #00FFh ,4
Page 26 of 136
Dr Sudhir Shelke

27. OR
Syntax:-
Direct : OR dma
Indirect : OR {ind}[,ARn]
Long Immediate : OR #lk [,shift]
Operands:-
d a
Ind :- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Lk :- 16 bit constant
shift
Page 27 of 136
Dr Sudhir Shelke

28. OR
Status Bits:- Not Affected
Execution:-
Direct/Indirect Addressing
PC + → PC
ACC(15- OR d a → ACC -0)
ACC(31- → ACC -16)
Long Immediate Addressing
PC + → PC
ACC(31-0) OR (lk x 2shift → ACC
Page 28 of 136
Dr Sudhir Shelke

29. OR
EXAMPLES:-
1. OR DAT8 ; (DP = 8) Direct Addressing
Before Instruction After Instruction
F000 h F000 hData Memory
0408h
Data Memory
0408h
0010 0002 h 0010 F002 hACC ACC
Page 29 of 136
Dr Sudhir Shelke

30. OR
2. OR *, AR0 Indirect Addressing
Before Instruction After Instruction
1111 h 1111 hData Memory
0300h
Data Memory
0300h
0000 0222 h 0000 1333 hACC ACC
1
0300h AR1
ARP
0300h
0ARP
AR1
Page 30 of 136
Dr Sudhir Shelke

31. OR
Before Instruction After Instruction
00FF 0000 h 00FF 1100hACC ACC
3. OR #8111h ,8
Page 31 of 136
Dr Sudhir Shelke

32. XOR
Syntax:-
Direct : XOR dma
Indirect : XOR {ind}[,ARn]
Long Immediate : XOR #lk [,shift]
Operands:-
d a
Ind :- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Lk :- 16 bit constant
shift
Page 32 of 136
Dr Sudhir Shelke

33. XOR
Status Bits:- Not Affected
Execution:-
Direct/Indirect Addressing
PC + → PC
ACC(15- XOR d a → ACC -0)
ACC(31- → ACC -16)
Long Immediate Addressing
PC + → PC
ACC(31-0) XOR (lk x 2shift → ACC
Page 33 of 136
Dr Sudhir Shelke

34. XOR
EXAMPLES:-
1. XOR DAT127 ; (DP = 511) Direct Addressing
Before Instruction After Instruction
F0F0 h F0F0 hData Memory
FFFFh
Data Memory
FFFFh
1234 5678h 1234 A688hACC ACC
Page 34 of 136
Dr Sudhir Shelke

35. XOR
2. XOR *+, AR0 Indirect Addressing
Before Instruction After Instruction
FFFF h FFFFhData Memory
0300h
Data Memory
0300h
1234 F0F0h 1234 0F0FhACC ACC
7
0300h AR7
ARP
0301h
0ARP
AR7
Page 35 of 136
Dr Sudhir Shelke

36. XOR
Before Instruction After Instruction
1111 1010 h 111E 1F10hACC ACC
3. XOR #0F0Fh ,4
Before Instruction
1111 1010 hACC
Page 36 of 136
Dr Sudhir Shelke

37. LACC (LOAD ACC)
Syntax:-
Direct:- LACC dma [,shift]
Indirect:- LACC {ind} [,shift[,ARn]]
Long Immediate:- LACC #lk [,shift]
Operands:-
d a
shift
k
- lk
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 37 of 136
Dr Sudhir Shelke

38. LACC
Execution:-
Direct/Indirect Addressing:-
PC + → PC
(dma) x 2shift → ACC
Long Immediate Addressing:-
PC + → PC
Lk x 2shift → ACC
Status Bits:- Affected By SXM
Page 38 of 136
Dr Sudhir Shelke

39. LACC
Examples:-
1. LACC DAT6, 4 ; (DP =8) Direct Addressing
Before Instruction After Instruction
0001 h 0001 hData Memory
0406h
Data Memory
0406h
1234 5678h 0000 0010 hACC ACC
Page 39 of 136
Dr Sudhir Shelke

40. LACC
2. LACC *, 4 Indirect Addressing
Before Instruction After Instruction
00FF h 00FFhData Memory
0300h
Data Memory
0300h
1234 5678h 0000 0FF0hACC ACC
2
0300h AR2
ARP
0300h
2ARP
AR2
Page 40 of 136
Dr Sudhir Shelke

41. LACC
Before Instruction After Instruction
1111 1010 h 0000 F000hACC ACC
3. LACC #F000h
Page 41 of 136
Dr Sudhir Shelke

42. LACL (LOAD ACC Lower Byte)
Syntax:-
Direct:- LACL dma [,shift]
Indirect:- LACL {ind} [,ARn]
Short Immediate:- LACL # k
Operands:-
d a
k
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 42 of 136
Dr Sudhir Shelke

43. LACL
Execution:-
Direct/Indirect Addressing:-
PC + → PC
→ ACC -16)
d a → ACC -0)
Short Immediate Addressing:-
PC + → PC
→ ACC -8)
k→ ACC -0)
Status Bits:- Affected By SXM
Page 43 of 136
Dr Sudhir Shelke

44. LACL
Examples:-
1. LACL DAT1 ; (DP =6) Direct Addressing
Before Instruction After Instruction
0000 h 0000 hData Memory
0301h
Data Memory
0301h
7FFF FFFFh 0000 0000 hACC ACC
Page 44 of 136
Dr Sudhir Shelke

45. LACL
2. LACL *-,AR4 Indirect addressing
Before Instruction After Instruction
00FF h 00FFhData Memory
0401h
Data Memory
0401h
7FFF FFFFh 0000 00FFhACC ACC
0
0401h AR2
ARP
0400h
4ARP
AR2
Before Instruction
Data Memory
0401h
2
0401h
ARP
AR2
Page 45 of 136
Dr Sudhir Shelke

46. LACL
Before Instruction After Instruction
7FFF FFFFh 0000 0010hACC ACC
3. LACL #10h
Page 46 of 136
Dr Sudhir Shelke

47. SACL (Store ACC Lower Byte)
Syntax:-
Direct:- SACL dma [,shift2]
Indirect:- SACL {ind} [[shiift2,ARn]]
Operands:-
d a
shift
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 47 of 136
Dr Sudhir Shelke

48. SACL
Execution:-
Direct/Indirect Addressing:-
PC + → PC
(ACC(15-0) X 2shift2 x → d a
Status Bits:- None Affected
Page 48 of 136
Dr Sudhir Shelke

49. SACL
Examples:-
1. SACL DAT11 ; (DP =4) Direct Addressing
After Instruction
0005 h 8421hData Memory
020Bh
Data Memory
020Bh
7C63 8421h 7C63 8421hACC ACC
Before Instruction
Page 49 of 136
Dr Sudhir Shelke

50. SACL
2. SACL *,0,AR7 Indirect addressing
Before Instruction After Instruction
0005 h 8421hData Memory
0300h
Data Memory
0401h
00FF 8421h 00FF 8421hACC ACC
6
0300h AR6
ARP
0300h
7ARP
AR6
Page 50 of 136
Dr Sudhir Shelke

51. LAR (LOAD AR)
Syntax:-
Direct:- LAR ARx,dma
Indirect:- LAR ARx , {ind} [,ARn]
Short Immediate:- LAR ARx,#K
Long immediate:- LAR ARx,#LK
Operands:-
d a
x
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
k
lk
Page 51 of 136
Dr Sudhir Shelke

52. LAR
Execution:-
Direct/Indirect Addressing:-
PC + → PC
d a → AR
Short Immediate Addressing:-
PC + → PC
K → AR
Long Immediate Addressing:-
PC + → PC
LK → AR
Status Bits :- None Affected
Page 52 of 136
Dr Sudhir Shelke

53. LAR
1. LAR AR0,DAT16 ; (DP = 6)
After Instruction
0018 h 0018hData Memory
0310h
Data Memory
0310h
0006h 0018hAR0 AR0
Before Instruction
Page 53 of 136
Dr Sudhir Shelke

54. LAR
2. LAR AR4,*-
Before Instruction After Instruction
0032h 0032hData Memory
0300h
Data Memory
0300h
4
0300h AR4
ARP
0032h
4ARP
AR4
Page 54 of 136
Dr Sudhir Shelke

55. LAR
3. LAR AR4,#01h
Before Instruction After Instruction
FF09h 0001hAR4 AR4
Page 55 of 136
Dr Sudhir Shelke

56. LAR
4. LAR AR4, #3FFFh
Before Instruction After Instruction
0000h 3FFFhAR4 AR4
Page 56 of 136
Dr Sudhir Shelke

57. SAR (Store AR)
Syntax:-
Direct:- SAR ARx,dma
Indirect:- SAR ARx , {ind} [,ARn]
Operands:-
d a
x
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 57 of 136
Dr Sudhir Shelke

58. SAR
Execution:-
Direct/Indirect Addressing:-
PC + → PC
AR → d a
Status Bits :- None Affected
Page 58 of 136
Dr Sudhir Shelke

59. SAR
1. SAR AR0,DAT30 ; (DP = 6)
After Instruction
0018 h 0037hData Memory
031Eh
Data Memory
031Eh
0037h 0037hAR0 AR0
Before Instruction
Page 59 of 136
Dr Sudhir Shelke

60. SAR
2. SAR AR0,*+
Before Instruction After Instruction
0000h 0401hData Memory
0401h
Data Memory
0401h
0401h AR0 0402hAR0
Page 60 of 136
Dr Sudhir Shelke

61. LDP (Load DP)
Syntax:-
Direct:- LDP dma
Indirect:- LDP {ind} [,ARn]
Short Immediate:- LDP #K
Operands:-
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
k
Page 61 of 136
Dr Sudhir Shelke

62. LDP
Execution
PC + → PC
Direct/Indirect Addressing:-
Ni e LSB’S of d a → DP its
Short Immediate Addressing:-
K → DP its
Status Bits:- Affects DP
Page 62 of 136
Dr Sudhir Shelke

63. LDP
1. LDP DAT127 ; (DP = 511)
After Instruction
FEDC h FEDC hData Memory
FFFF h
Data Memory
FFFF h
0 1111 1111 0 1101 1100DP DP
Before Instruction
Page 63 of 136
Dr Sudhir Shelke

64. LDP
2. LDP *,AR5
Before Instruction After Instruction
0006h 0006hData Memory
0300h
Data Memory
0300h
4
0300h AR4
ARP
0300h
5ARP
AR4
0 1111 1111 0 0000 0110DP DP
Page 64 of 136
Dr Sudhir Shelke

65. LDP
3. LDP #00h
Before Instruction After Instruction
0 1111 1111 0 0000 0000DP DP
Page 65 of 136
Dr Sudhir Shelke

66. LT (Load Temporary Register 0)
Syntax:-
Direct:- LT dma
Indirect:- LT {ind} [,ARn]
Operands:-
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 66 of 136
Dr Sudhir Shelke

67. LT
Execution
Direct/Indirect Addressing:-
PC + → PC
d a → TREG
Status Bits:- None Affected
Page 67 of 136
Dr Sudhir Shelke

68. LT
1. LT DAT24 ; (DP = 8)
After Instruction
0062 h 0062 hData Memory
0418 h
Data Memory
0418 h
0003h 0062hTREG0 TREG0
Before Instruction
Page 68 of 136
Dr Sudhir Shelke

69. LT
2. LT *,AR3
Before Instruction After Instruction
0062h 0062hData Memory
0418h
Data Memory
0418h
4
0418h AR4
ARP
0418h
3ARP
AR4
0003h 0062hTREG0 TREG0
Before Instruction
ARP
Page 69 of 136
Dr Sudhir Shelke

70. MPY
Syntax:-
Direct:-MPY dma
Indirect:-MPY {ind} [,ARn]
Short Immediate:- MPY #K
Long immediate:-MPY #LK
Operands:-
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
- k
- lk
Page 70 of 136
Dr Sudhir Shelke

71. MPY
Execution:-
Direct/Indirect Addressing
PC + → PC
TREG X d a → PREG
Short Immediate Addressing
PC + → PC
TREG X K → PREG
Long Immediate Addressing
PC + → PC
TREG0 X Lk → PREG
Page 71 of 136
Dr Sudhir Shelke

72. MPY
Examples:-
1. MPY DAT13 ; (DP= 8) Direct Addressing
After Instruction
0007 h 0007 hData Memory
040D h
Data Memory
040D h
0006h 0006hTREG0 TREG0
Before Instruction
0036h 002AhPREG PREG
Page 72 of 136
Dr Sudhir Shelke

73. MPY
2. MPY *,AR2 Indirect Addressing
After Instruction
0007 h 0007 hData Memory
040D h
Data Memory
040D h
0006h 0006hTREG0 TREG0
Before Instruction
0036h 002AhPREG PREG
4
040Dh AR4
ARP
040Dh
2
AR4
ARP
Page 73 of 136
Dr Sudhir Shelke

74. MPY
3. MPY #31h
After Instruction
0002h 0002hTREG0 TREG0
Before Instruction
0036h 0062hPREG PREG
Page 74 of 136
Dr Sudhir Shelke

75. MPY
3. MPY #0123h
After Instruction
0002h 0002hTREG0 TREG0
Before Instruction
0036h 0246hPREG PREG
Page 75 of 136
Dr Sudhir Shelke

76. MPYU
Syntax:-
Direct:-MPYU dma
Indirect:-MPYU {ind} [,ARn]
Operands:-
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 76 of 136
Dr Sudhir Shelke

77. MPYU
Execution:-
Direct/Indirect Addressing
PC + → PC
U sig ed TREG X U sig ed d a → PREG
Page 77 of 136
Dr Sudhir Shelke

78. MPYU
Examples:-
1. MPYU DAT16 ; (DP= 4) Direct Addressing
After Instruction
FFFF h FFFF hData Memory
210 h
Data Memory
210 h
FFFFh FFFF hTREG0 TREG0
Before Instruction
0000 0001h FFFE 0001hPREG PREG
Page 78 of 136
Dr Sudhir Shelke

79. MPYU
2. MPYU *,AR6 Indirect Addressing
After Instruction
FFFF h FFFF hData Memory
0210 h
Data Memory
0210 h
FFFFh FFFF hTREG0 TREG0
Before Instruction
0000 0001h FFFE 0001hPREG PREG
5
0210h AR5
ARP
0210h
6
AR5
ARP
Page 79 of 136
Dr Sudhir Shelke

80. MAC (Multiply & Accumulate)
Syntax:-
Direct:- MAC pma , dma
Indirect:- MAC pma , {ind} [,ARn]
Operands
pma
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 80 of 136
Dr Sudhir Shelke

81. MAC
Execution:-
(PC + → PC
ACC + Shifted PREG → ACC
d a X p a → PREG
Status Bits:-
Affected By Affects
OVM & PM C & OV
Page 81 of 136
Dr Sudhir Shelke

82. MAC
Examples:-
1. MAC 0FF00h , 02h (DP = 6 , PM =0)
After Instruction
0045h 0023hTREG0 TREG0
Before Instruction
0045 8972h 008ChPREG PREG
0X 0723 EC41h 0769 75B3hACC ACC
C C
0004 h 0004 hProg Memory
FF00 h
Prog Memory
FF00 h
0023 h 0023 hData Memory
0302 h
Data Memory
0302 h
Page 82 of 136
Dr Sudhir Shelke

83. 2. MAC 0FF00h , * , AR5
After Instruction
0045h 0023hTREG0 TREG0
Before Instruction
0045 8972h 008ChPREG PREG
0X 0723 EC41h 0769 75B3hACC ACC
C C
0004 h 0004 hProg Memory
FF00 h
Prog Memory
FF00 h
0023 h 0023 hData Memory
0302 h
Data Memory
0302 h
4
0302h AR4
ARP
0302h
5
AR4
ARP
Page 83 of 136
Dr Sudhir Shelke

84. MACD
Syntax:-
Direct:- MACD pma , dma
Indirect:- MACD pma , {ind} [,ARn]
Operands
pma
d a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 84 of 136
Dr Sudhir Shelke

85. MACD
Execution:-
(PC + → PC
ACC + Shifted PREG → ACC
d a X p a → PREG
d a → d a+
Status Bits:-
Affected By Affects
OVM & PM C & OV
Page 85 of 136
Dr Sudhir Shelke

86. MACD
1. MACD 0FF00h , 02h (DP = 6 , PM =0)
After Instruction
0045h 0023hTREG0 TREG0
Before Instruction
0045 8972h 008ChPREG PREG
0X 0723 EC41h 0769 75B3hACC ACC
C C
0004 h 0004 hProg Memory
FF00 h
Prog Memory
FF00 h
0023 h 0023 hData Memory
0302 h
Data Memory
0302 h
0001 h 0023 hData Memory
0303 h
Data Memory
0303 h
Page 86 of 136
Dr Sudhir Shelke

87. 2. MACD 0FF00h , * , AR5
After Instruction
0045h 0023hTREG0 TREG0
Before Instruction
0045 8972h 008ChPREG PREG
0X 0723 EC41h 0769 75B3hACC ACC
C C
0004 h 0004 hProg Memory
FF00 h
Prog Memory
FF00 h
0023 h 0023 hData Memory
0302 h
Data Memory
0302 h
4
0302h AR4
ARP
0302h
5
AR4
ARP
0001 h 0023 hData Memory
0303 h
Data Memory
0303 h
Page 87 of 136
Dr Sudhir Shelke

88. LST (Load Status Register)
Syntax:-
Direct:- LST #m,dma
Indirect:- LST #m,{ind} [,ARn]
Operands:-
d a
m = 0/1
Page 88 of 136
Dr Sudhir Shelke

89. LST
Execution:-
PC + → PC
d a → STm (ST0/ST1)
Dma(15- → ARP
Status Bits :-
Affected By Does Not Affect
ARB,ARP,CNF,C,TC,SXM,DP,
XF,HM,OV,OVM,PM
INTM
Page 89 of 136
Dr Sudhir Shelke

90. LST
After Instruction
2404 h 2404 hData Memory
0060h h
Data Memory
0060 h
6E00h 2604 hST0 ST0
Before Instruction
1. LST #0,60h (DP=0)
Page 90 of 136
Dr Sudhir Shelke

91. LST
2. LST #1, 00h (DP= 6)
After Instruction
E1BC h E1BChData Memory
0300h h
Data Memory
0300 h
09A0 h E1BC hST1 ST1
Before Instruction
Page 91 of 136
Dr Sudhir Shelke

92. LST
3. LST #0,*-,AR1
After InstructionBefore Instruction
1E00 h EE04 hST0 ST0
EE04 h EE04 hData Memory
03FF h
Data Memory
03FF h
4
AR4
ARP
03FEh
7ARP
AR4 03FFh
Page 92 of 136
Dr Sudhir Shelke

93. SST (Store Status Register)
Syntax:-
Direct:- SST #m,dma
Indirect:- SST #m,{ind} [,ARn]
Operands:-
d a
m = 0/1
Page 93 of 136
Dr Sudhir Shelke

94. LST
Execution:-
PC + → PC
ST /ST →d a
Status Bits :- None Affected
Page 94 of 136
Dr Sudhir Shelke

95. SST
After Instruction
000A h A408 hData Memory
0060h h
Data Memory
0060 h
A408h A408 hST0 ST0
Before Instruction
1. SST #0, DAT96 (DP=6)
Page 95 of 136
Dr Sudhir Shelke

96. SST
2. SST #1,*,AR7
After InstructionBefore Instruction
0000h 2580 h
ST1 ST12580 h 2580 h
Data Memory
0300h
Data Memory
0300 h
0
AR0
ARP
0300h
7ARP
AR0 0300h
Page 96 of 136
Dr Sudhir Shelke

97. B (Branch)
B
Syntax:- B Pma [,{ind}[,ARn]]
Operands:-
P a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 97 of 136
Dr Sudhir Shelke

98. B
Execution:-
P a → PC
Modify Current AR & ARP as Specified in Instruction.
Example:-
B 191,*+,AR1
The Value 191 is loaded into PC & Program continues execution
from that location. The Current AR is incremented by 1 & ARP is
Set to 1
Page 98 of 136
Dr Sudhir Shelke

99. BANZ Bra ch if Curre t AR ≠
Syntax:- BANZ Pma [{ind} [,ARn]]
Operands:-
P a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Execution:-
If Curre t AR ≠
P a → PC
Else
PC + → PC
Modify AR & ARP as Specified.
Page 99 of 136
Dr Sudhir Shelke

100. BANZ
1. BANZ PGM0
0 is loaded into PC & program continues execution from that
lo atio as AR ≠ .
After Instruction
0005 h 0004 hAR0 AR0
0 0ARP ARP
Before Instruction
Page 100 of 136
Dr Sudhir Shelke

101. BANZ
1. BANZ PGM0
The PC is incremented by 2 as (AR0) = 0 & execution continues
from that location.
After Instruction
0000h FFFF hAR0 AR0
0 0ARP ARP
Before Instruction
Page 101 of 136
Dr Sudhir Shelke

102. CALL
Syntax:- CALL Pma [,{ind}[,ARn]
Operands:-
P a
Ind:- {*,*+,*-,*0+,*0-,*BR0+,*BR0-}
Page 102 of 136
Dr Sudhir Shelke

103. CALL
Execution:-
PC + → Top of Sta k
P a → PC
Modify Current AR & ARP as Specified in Instruction
Page 103 of 136
Dr Sudhir Shelke

104. CALL
1. CALL PRG191 ,*+,AR0
After InstructionBefore Instruction
0100 h 0032 hTOS ST0
0030h 00BF hPC PC
1
AR1
ARP
0006h
0ARP
AR1 0005h
Page 104 of 136
Dr Sudhir Shelke

105. CC (CALL CONDITIONAL)
Syntax:- CC P a Co d[,Co d ][,…]
Operands :-
P a
Page 105 of 136
Dr Sudhir Shelke

106. ACC = 0 EQ
ACC ≠ NEQ
ACC < 0 LT
ACC 0 LEQ
ACC > 0 GT
ACC GEQ
C = 0 NC
C = 1 C
OV = 0 NOV
OV = 1 OV
TC = 0 NTC
TC = 1 TC
BIO Low BIO
Unconditionally UNC
Conditions:-
Page 106 of 136
Dr Sudhir Shelke

107. CC
Execution:-
If (Condition(s))
PC + → TOS
P a → PC
Else
PC + → PC
Page 107 of 136
Dr Sudhir Shelke

108. CC
CC PGM191 LEQ,C
If the contents of ACC are 0 & the C bit is set, then 00BF is
loaded into PC & the program continues execution from that
location also the address of next instruction is saved into TOP OF
STACK.
If the conditions are not met, execution continues from next
instruction following the CC instruction.
Page 108 of 136
Dr Sudhir Shelke

109. Page 109 of 136
Dr Sudhir Shelke

110. BY.
DR. SUDHIR N SHELKE
Programs of TMS320C5X
Page 110 of 136
Dr Sudhir Shelke

111. 1. Write an ALP to perform addition of two numbers.
Assuming the data be used for addition is present in memory location 8000h &
8001h & the result is stored in 8002h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
CLRC SXM; Clear Sign Extension Mode Bit
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
ADD 01h;
Content of ACC is added with content of Mem Location
8001h
SACL 02h; Content of ACC Lower Byte is Stored in 8002h
.end Program End
Prof. Sanjay Balwani
Page 111 of 136
Dr Sudhir Shelke

112. Before Instruction After Instruction
1234h
0X FFFF FFFF h 0000 1236 h
1234hData Memory
8000 h
Data Memory
8000 h
ACC ACC
C C
0002h 0002hData Memory
8001 h
Data Memory
8001 h
1111h 1236hData Memory
8002 h
Data Memory
8002 h
Dr. Sudhir N Shelke
Page 112 of 136
Dr Sudhir Shelke

113. 2. Write an ALP to perform subtraction of two
numbers.
Assuming the data be used for subtraction is present in memory location 8000h &
8001h & the result is stored in 8002h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
CLRC SXM; Clear Sign Extension Mode Bit
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
SUB 01h;
Content of ACC is subtracted with content of Mem
Location 8001h
SACL 02h; Content of ACC Lower Byte is Stored in 8002h
.end Program End
Dr. Sudhir N Shelke
Page 113 of 136
Dr Sudhir Shelke

114. Before Instruction After Instruction
1234h
1X FFFF FFFF h 0000 1232 h
1234hData Memory
8000 h
Data Memory
8000 h
ACC ACC
C C
0002h 0002hData Memory
8001 h
Data Memory
8001 h
1111h 1232hData Memory
8002 h
Data Memory
8002 h
Dr. Sudhir N Shelke
Page 114 of 136
Dr Sudhir Shelke

115. 3. Write an ALP to perform ANDING of two numbers.
Dr. Sudhir N Shelke
Assuming the data be used for ANDing is present in memory location 8000h &
8001h & the result is stored in 8002h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
AND 01h;
Content of ACC is ANDed with content of Mem Location
8001h
SACL 02h; Content of ACC Lower Byte is Stored in 8002h
.end Program End
Page 115 of 136
Dr Sudhir Shelke

116. Before Instruction After Instruction
FFFF h
ABCD EF12 h 0000 1234 h
FFFF hData Memory
8000 h
Data Memory
8000 h
ACC ACC
1234 h 1234 hData Memory
8001 h
Data Memory
8001 h
1111h 1234hData Memory
8002 h
Data Memory
8002 h
Dr. Sudhir N Shelke
Page 116 of 136
Dr Sudhir Shelke

117. 4. Write an ALP to perform ORING of two numbers.
Dr. Sudhir N Shelke
Assuming the data be used for ORing is present in memory location 8000h &
8001h & the result is stored in 8002h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
OR 01h;
Content of ACC is ORed with content of Mem Location
8001h
SACL 02h; Content of ACC Lower Byte is Stored in 8002h
.end Program End
Page 117 of 136
Dr Sudhir Shelke

118. Before Instruction After Instruction
FFFF h
ABCD EF12 h 0000 FFFF h
FFFF hData Memory
8000 h
Data Memory
8000 h
ACC ACC
1234 h 1234 hData Memory
8001 h
Data Memory
8001 h
1111h FFFF hData Memory
8002 h
Data Memory
8002 h
Dr. Sudhir N Shelke
Page 118 of 136
Dr Sudhir Shelke

119. 5. Write an ALP to perform Ones Complement of a
number.
Dr. Sudhir N Shelke
Assuming the data be used is present in memory location 8000h the result is
stored in 8001h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
CMPL Content of ACC are complemented by one
SACL 01h; Content of ACC Lower Byte is Stored in 8001h
.end Program End
Page 119 of 136
Dr Sudhir Shelke

120. Before Instruction After Instruction
FFFF h
1234 5678h FFFF 00000h
FFFF hData Memory
8000 h
Data Memory
8000 h
ACC ACC
1111h 0000 hData Memory
8001 h
Data Memory
8001 h
Dr. Sudhir N Shelke
Page 120 of 136
Dr Sudhir Shelke

121. 6. Write an ALP to perform Two’s Complement of a
number.
Dr. Sudhir N Shelke
Assuming the data be used is present in memory location 8000h the result is
stored in 8001h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h Load ACC With content of Mem Location 8000h
CMPL Content of ACC are complemented by one
ADD #01h Add one with content of ACC
SACL 01h; Content of ACC Lower Byte is Stored in 8001h
.end Program End
Page 121 of 136
Dr Sudhir Shelke

122. Before Instruction After Instruction
FFFF h
1234 5678h FFFF 00001h
FFFF hData Memory
8000 h
Data Memory
8000 h
ACC ACC
1111h 0001hData Memory
8001 h
Data Memory
8001 h
Dr. Sudhir N Shelke
Page 122 of 136
Dr Sudhir Shelke

123. 7. Write an ALP to perform Multiplication of two
numbers.
Dr. Sudhir N Shelke
Assuming the data be used is present in memory location 8000h & 8001h ,the
result is stored in 8002h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LT 00h Load TREG0 With content of Mem Location 8000h
MPY 01h
Multiply Content of TREG0 with Content of Mem Location
8001h
SPL 02h; Content of PREG Lower Byte is Stored in 8002h
.end Program End
Page 123 of 136
Dr Sudhir Shelke

124. Before Instruction After Instruction
0002 h
1234h 0002 h
FFFF hData Memory
8000 h
Data Memory
8000 h
TREG0
0003 h 0001hData Memory
8001 h
Data Memory
8001 h
Dr. Sudhir N Shelke
PREG
TREG0
PREG1352 5687 h 0000 0006 h
0055 h 0006 h
Data Memory
8002 h
Data Memory
8002 h
Page 124 of 136
Dr Sudhir Shelke

125. 8. Write an ALP to perform division of 16 bit data
by 8 bit data.
Assuming that dividend is present in memory location 8000h, divisor is present in memory location
8001h & we are storing the quotient in memory location 8002h,remainder in 8003h.
Program Comments
.mmregs Include Memory Mapped Registers
.entry Initialize PC with Starting Address of this Program
LDP #100h; Load Data Pointer with 1 0000 0000
LACC 00h; Load ACC With content of Mem Location 8000h
RPT #15; Repeat the next instruction 16 times
SUBC 01h; Perform conditional subtraction of divisor algorithm
SACL 02h; The content of ACC lower byte is stored Mem Location 8002h
SACH 03h The content of ACC higher byte is stored Mem Location 8003h
.end Program End
Dr. Sudhir N Shelke
Page 125 of 136
Dr Sudhir Shelke

126. Before Instruction After Instruction
0008 h
1234 5678 h 0000 0004 h
0008 hData Memory
8000 h
Data Memory
8000 h
ACC ACC
0002 h 0002 hData Memory
8001 h
Data Memory
8001 h
1111h 0000 hData Memory
8003 h
Data Memory
8003 h
ABCD h 0004 h
Data Memory
8002 h
Data Memory
8002 h
Dr. Sudhir N Shelke
Page 126 of 136
Dr Sudhir Shelke

127. SUBC
Dr. Sudhir N Shelke
Page 127 of 136
Dr Sudhir Shelke

128. THANK YOU
Page 128 of 136
Dr Sudhir Shelke

129. Dr. Sudhir N Shelke
PIPELINING structure
Page 129 of 136
Dr Sudhir Shelke

130. 1.
ZAP
B PGM1250h
ADD *
SACL *+
MAC 4500h, 25h
1250h: LACC *+
Page 130 of 136
Dr Sudhir Shelke

131. Pipeline Structure
CYCLE PC FETCH DECODE READ EXECUTE
1 [B] ZAP
2 [1250h] B ZAP
3 [ADD] 1250h B ZAP
4 [SACL] ADD DUMMY B ZAP
5 LACC SACL ADD DUMMY B
6 LACC SACL ADD DUMMY
7 LACC SACL ADD
8 LACC SACL
9 LACC
Page 131 of 136
Dr Sudhir Shelke

132. 2.
ZAP
BD PGM1250h
ADD *
SACL *+
MAC 4500h, 25h
1250h: LACC *+
Page 132 of 136
Dr Sudhir Shelke

133. Pipeline Structure
CYCLE PC FETCH DECODE READ EXECUTE
1 [BD] ZAP
2 [1250h] BD ZAP
3 [ADD] 1250h BD ZAP
4 [SACL] ADD DUMMY BD ZAP
5 LACC SACL ADD DUMMY BD
6 LACC SACL ADD DUMMY
7 LACC SACL ADD
8 LACC SACL
9 LACC
Page 133 of 136
Dr Sudhir Shelke

134. 3.
SACL *+
CC PGM 1250H ,GT,NOV
LDP 127
SUB 20H
MAC 4500H,25H
1250H: LACC *+
Page 134 of 136
Dr Sudhir Shelke

135. Pipeline Structure
(CONDITION NOT SATISFIED)
CYCLE PC FETCH DECODE READ EXECUTE
1 [CC] SACL
2 [1250h] CC SACL
3 [LDP] 1250H CC SACL
4 [SUB] LDP DUMMY CC SACL
5 MAC SUB LDP DUMMY CC
6 MAC SUB LDP DUMMY
7 MAC SUB LDP
8 MAC SUB
9 MAC
Page 135 of 136
Dr Sudhir Shelke

136. Pipeline Structure
(CONDITION SATISFIED)
CYCLE PC FETCH DECODE READ EXECUTE
1 [CC] SACL
2 [1250h] CC SACL
3 [LDP] 1250H CC SACL
4 [SUB] LDP DUMMY CC SACL
5 [LACC] SUB DUMMY DUMMY CC
6 LACC DUMMY DUMMY DUMMY
7 LACC DUMMY DUMMY
8 LACC DUMMY
9 LACC
Page 136 of 136
Dr Sudhir Shelke