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Microprocessor-Based Systems
Dr. Randa Elanwar
Lecture 4
Lecture Content
• 8086/8088 microprocessor registers
• 8086/8088 microprocessor instruction set
2Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (CMP)
Arithmetic and Logical Instructions:
• CMP: This instruction compares the source operand,
which may be a register or an immediate data or a
memory location, with a destination operand that may
be a register or a memory location.
• For comparison, it subtracts the source operand from
the destination operand but does not store the result
anywhere.
• The flags are affected depending upon the result of the
subtraction:
– If both of the operands are equal, zero flag is set.
– If the source operand is greater than the destination
operand, carry flag is set or else, carry flag is reset.
3Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (CMP)
• Example
• CMP BX, 0100H Immediate
• CMP 0100 Immediate [AX implicit]
• CMP [5000H],0100H Direct
• CMP BX, [SI] Register indirect
• CMP BX, CX Register
4Microprocessor-Based Systems Dr. Randa Elanwar
8086 Flag register
• 8086 has a 16-bit flag register which is divided into two parts, (a)
condition code or status flags and (b) machine control flags.
• The condition code flag register is the lower byte of the 16-bit flag
register along with the overflow flag. This part of the flag register
of 8086 reflects the results of the operations performed by ALU.
• The control flag register is the higher byte of the flag register of
8086. It contains three flags, direction flag (D), interrupt flag (1)
and trap flag (T).
5Microprocessor-Based Systems Dr. Randa Elanwar
8086 Flag register
• S-Sign Flag: Is equal to the MSB of the result. Since in 2's
complement negative numbers have a 1 in the MSB and for
nonnegative numbers this bit is 0, this flag indicates whether
the previous result was negative or nonnegative.
• Z-Zero Flag: This flag is set to 1, if the result of the
computation or comparison performed by the previous
instruction is zero and reset to 0 if the result is nonzero
• P-Parity Flag: This flag is set to 1, if the lower byte of the
result contains even number of 1’s.
6Microprocessor-Based Systems Dr. Randa Elanwar
8086 Flag register
• Ac-Auxiliary Carry Flag: This is set, if there is a carry from the
lowest nibble, i.e. bit 3, during addition or borrow for the
lowest nibble, i.e. bit 3, during subtraction. This flag is used
exclusively for BCD arithmetic.
• C-Carry Flag: An addition causes this flag to be set if there is a
carry out of the MSB, and a subtraction causes it to be set if a
borrow is needed. In case, no carry is generated, it will be '0'.
• T-Trap Flag: If this flag is set, the processor enters the single
step execution mode. In other words, a trap interrupt is
generated after execution of each instruction. The processor
executes the current instruction and the control is transferred
to the Trap interrupt service routine.
7Microprocessor-Based Systems Dr. Randa Elanwar
8086 Flag register
• D-Direction Flag: This is used by string manipulation
instructions. If this flag bit is '0', the string is processed
beginning from the lowest address to the highest address, i.e.
autoincrementing mode. Otherwise, the string is processed
from the highest address towards the lowest address, i.e.
autodecrementing mode.
• I-lnterrupt Flag: If this flag is set, the maskable interrupts are
recognised by the CPU, otherwise, they are ignored.
• O-Overflow Flag: This flag is set, if an overflow occurs, i.e. if
the result is out of range of 7 bits (the MSB or 8th bit has a
Carry instead of the result sign).
8Microprocessor-Based Systems Dr. Randa Elanwar
8086 Flag register
• Examples
9Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set
Flag manipulation instructions
• The flag manipulation instructions directly modify
some of the flags of 8086.
CLC - Clear carry flag
CMC - Complement carry flag
STC - Set carry flag
CLD - Clear direction flag
STD - Set direction flag
CLI - Clear interrupt flag
STI - Set interrupt flag
10Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (AND)
Arithmetic and Logical Instructions:
• AND: Logical AND: This instruction bit by bit ANDs the source
operand that may be an immediate, a register or a memory
location to the destination operand that may be a register or a
memory location.
• The result is stored in the destination operand. At least one of the
operands should be a register or a memory operand.
• Both the operands cannot be memory locations or immediate
operands. An immediate operand cannot be a destination
operand.
• Example:
• AND AX, 0008 H
• AND AX, BX
• AND AX, [5000H]
• AND [5000H], DX
11Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (OR)
Arithmetic and Logical Instructions:
• OR: Logical OR: The OR instruction carries out the OR
operation in the same way as described in case of the AND
operation.
• The limitations on source and destination operands are also
the same as in case of AND operation.
• Example:
• OR AX, 0008 H
• OR AX, BX
• OR AX, [5000H]
• OR [5000H], 0008 H
12Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (NOT-XOR)
Arithmetic and Logical Instructions:
• NOT: Logical Invert: The NOT instruction complements (inverts) the
contents of an operand register or a memory location, bit by bit.
• Example:
• NOT AX
• NOT [5000H]
• XOR: Logical Exclusive OR: The XOR operation is again carried out in a
similar way to the AND and OR operation. The constraints on the
operands are also similar.
• The XOR operation gives a high output, when the 2 input bits are
dissimilar. Otherwise, the output is zero.
• Example:
• XOR AX, 0098 H
• XOR AX, BX
• XOR AX, [5000H]
13Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (TEST)
Arithmetic and Logical Instructions:
• TEST: Logical Compare Instruction: The TEST instruction
performs a bit by bit logical AND operation on the two
operands.
• Each bit of the result is then set to 1, if the corresponding bits
of both operands are 1, else the result bit is reset to 0.
• The operands may be registers, memory or immediate data.
• Example
• TEST AX, BX
• TEST [0500], 06H
• TEST [BX] [Dl], CX
14Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (SHL-SAL)
Arithmetic and Logical Instructions:
• SHL/SAL: Shift logical/Arithmetic Left: These instructions shift the
operand word or byte bit by bit to the left and insert zeros in the
newly introduced least significant bits.
• In case of all the SHIFT and ROTATE instructions, the count is either
1 or specified by register CL. The operand may reside in a register
or a memory location but cannot be an immediate data.
• Immediate operand is not allowed in any of the shift instructions
15Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (SHR)
Arithmetic and Logical Instructions:
• SHR: Shift Logical Right: This instruction performs bit-wise right
shifts on the operand word or byte that may reside in a register
or a memory location, by the specified count in the instruction
and inserts zeros in the shifted positions.
• The result is stored in the destination operand. This instruction
shifts the operand through carry flag.
16Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (SAR)
Arithmetic and Logical Instructions:
• SAR: Shift Arithmetic Right: This instruction performs right shifts
on the operand word or byte, that may be a register or a
memory location by the specified count in the instruction and
inserts the most significant bit of the operand in the newly
inserted positions. The result is stored in the destination
operand.
• This shift operation shifts the operand through carry flag.
17Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (ROR)
Arithmetic and Logical Instructions:
• ROR: Rotate Right without Carry: This instruction rotates the contents
of the destination operand to the right (bit-wise) either by one or by
the count specified in CL, excluding carry.
• The least significant bit is pushed into the carry flag and
simultaneously it is transferred into the most significant bit position
at each operation. The remaining bits are shifted right by the
specified positions.
• The operand may be a register or a memory location but it cannot be
an immediate operand.
18Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (ROL)
Arithmetic and Logical Instructions:
• ROL: Rotate Left without Carry: This instruction rotates the content of
the destination operand to the left by the specified count (bit-wise)
excluding carry.
• The most significant bit is pushed into the carry flag as well as the
least significant bit position at each operation. The remaining bits are
shifted left subsequently by the specified count positions.
• The operand may be a register or a memory location.
19Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (RCR)
Arithmetic and Logical Instructions:
• RCR: Rotate Right through Carry: This instruction rotates the contents
(bit-wise) of the destination operand right by the specified count
through carry flag (CF).
• For each operation, carry flag is pushed into the MSB of the operand,
and the LSB is pushed into carry flag. The remaining bits are shifted
right by the specified count positions.
• The operand may be a register or a memory location
20Microprocessor-Based Systems Dr. Randa Elanwar
8086/8088 instruction set (RCL)
Arithmetic and Logical Instructions:
• RCL: Rotate Left through Carry: This instruction rotates (bit-wise) the
contents of the destination operand left by the specified count
through the carry flag (CF).
• For each operation, the carry flag is pushed into LSB, and the MSB of
the operand is pushed into carry flag. The remaining bits are shifted
left by the specified positions.
• The operand may be a register or a memory location. The count for
rotation or shifting is either 1 or is specified using register CL, in case
of all the shift and rotate instructions.
21Microprocessor-Based Systems Dr. Randa Elanwar

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Microprocessors-based systems (under graduate course) Lecture 4 of 9

  • 2. Lecture Content • 8086/8088 microprocessor registers • 8086/8088 microprocessor instruction set 2Microprocessor-Based Systems Dr. Randa Elanwar
  • 3. 8086/8088 instruction set (CMP) Arithmetic and Logical Instructions: • CMP: This instruction compares the source operand, which may be a register or an immediate data or a memory location, with a destination operand that may be a register or a memory location. • For comparison, it subtracts the source operand from the destination operand but does not store the result anywhere. • The flags are affected depending upon the result of the subtraction: – If both of the operands are equal, zero flag is set. – If the source operand is greater than the destination operand, carry flag is set or else, carry flag is reset. 3Microprocessor-Based Systems Dr. Randa Elanwar
  • 4. 8086/8088 instruction set (CMP) • Example • CMP BX, 0100H Immediate • CMP 0100 Immediate [AX implicit] • CMP [5000H],0100H Direct • CMP BX, [SI] Register indirect • CMP BX, CX Register 4Microprocessor-Based Systems Dr. Randa Elanwar
  • 5. 8086 Flag register • 8086 has a 16-bit flag register which is divided into two parts, (a) condition code or status flags and (b) machine control flags. • The condition code flag register is the lower byte of the 16-bit flag register along with the overflow flag. This part of the flag register of 8086 reflects the results of the operations performed by ALU. • The control flag register is the higher byte of the flag register of 8086. It contains three flags, direction flag (D), interrupt flag (1) and trap flag (T). 5Microprocessor-Based Systems Dr. Randa Elanwar
  • 6. 8086 Flag register • S-Sign Flag: Is equal to the MSB of the result. Since in 2's complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0, this flag indicates whether the previous result was negative or nonnegative. • Z-Zero Flag: This flag is set to 1, if the result of the computation or comparison performed by the previous instruction is zero and reset to 0 if the result is nonzero • P-Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s. 6Microprocessor-Based Systems Dr. Randa Elanwar
  • 7. 8086 Flag register • Ac-Auxiliary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e. bit 3, during addition or borrow for the lowest nibble, i.e. bit 3, during subtraction. This flag is used exclusively for BCD arithmetic. • C-Carry Flag: An addition causes this flag to be set if there is a carry out of the MSB, and a subtraction causes it to be set if a borrow is needed. In case, no carry is generated, it will be '0'. • T-Trap Flag: If this flag is set, the processor enters the single step execution mode. In other words, a trap interrupt is generated after execution of each instruction. The processor executes the current instruction and the control is transferred to the Trap interrupt service routine. 7Microprocessor-Based Systems Dr. Randa Elanwar
  • 8. 8086 Flag register • D-Direction Flag: This is used by string manipulation instructions. If this flag bit is '0', the string is processed beginning from the lowest address to the highest address, i.e. autoincrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e. autodecrementing mode. • I-lnterrupt Flag: If this flag is set, the maskable interrupts are recognised by the CPU, otherwise, they are ignored. • O-Overflow Flag: This flag is set, if an overflow occurs, i.e. if the result is out of range of 7 bits (the MSB or 8th bit has a Carry instead of the result sign). 8Microprocessor-Based Systems Dr. Randa Elanwar
  • 9. 8086 Flag register • Examples 9Microprocessor-Based Systems Dr. Randa Elanwar
  • 10. 8086/8088 instruction set Flag manipulation instructions • The flag manipulation instructions directly modify some of the flags of 8086. CLC - Clear carry flag CMC - Complement carry flag STC - Set carry flag CLD - Clear direction flag STD - Set direction flag CLI - Clear interrupt flag STI - Set interrupt flag 10Microprocessor-Based Systems Dr. Randa Elanwar
  • 11. 8086/8088 instruction set (AND) Arithmetic and Logical Instructions: • AND: Logical AND: This instruction bit by bit ANDs the source operand that may be an immediate, a register or a memory location to the destination operand that may be a register or a memory location. • The result is stored in the destination operand. At least one of the operands should be a register or a memory operand. • Both the operands cannot be memory locations or immediate operands. An immediate operand cannot be a destination operand. • Example: • AND AX, 0008 H • AND AX, BX • AND AX, [5000H] • AND [5000H], DX 11Microprocessor-Based Systems Dr. Randa Elanwar
  • 12. 8086/8088 instruction set (OR) Arithmetic and Logical Instructions: • OR: Logical OR: The OR instruction carries out the OR operation in the same way as described in case of the AND operation. • The limitations on source and destination operands are also the same as in case of AND operation. • Example: • OR AX, 0008 H • OR AX, BX • OR AX, [5000H] • OR [5000H], 0008 H 12Microprocessor-Based Systems Dr. Randa Elanwar
  • 13. 8086/8088 instruction set (NOT-XOR) Arithmetic and Logical Instructions: • NOT: Logical Invert: The NOT instruction complements (inverts) the contents of an operand register or a memory location, bit by bit. • Example: • NOT AX • NOT [5000H] • XOR: Logical Exclusive OR: The XOR operation is again carried out in a similar way to the AND and OR operation. The constraints on the operands are also similar. • The XOR operation gives a high output, when the 2 input bits are dissimilar. Otherwise, the output is zero. • Example: • XOR AX, 0098 H • XOR AX, BX • XOR AX, [5000H] 13Microprocessor-Based Systems Dr. Randa Elanwar
  • 14. 8086/8088 instruction set (TEST) Arithmetic and Logical Instructions: • TEST: Logical Compare Instruction: The TEST instruction performs a bit by bit logical AND operation on the two operands. • Each bit of the result is then set to 1, if the corresponding bits of both operands are 1, else the result bit is reset to 0. • The operands may be registers, memory or immediate data. • Example • TEST AX, BX • TEST [0500], 06H • TEST [BX] [Dl], CX 14Microprocessor-Based Systems Dr. Randa Elanwar
  • 15. 8086/8088 instruction set (SHL-SAL) Arithmetic and Logical Instructions: • SHL/SAL: Shift logical/Arithmetic Left: These instructions shift the operand word or byte bit by bit to the left and insert zeros in the newly introduced least significant bits. • In case of all the SHIFT and ROTATE instructions, the count is either 1 or specified by register CL. The operand may reside in a register or a memory location but cannot be an immediate data. • Immediate operand is not allowed in any of the shift instructions 15Microprocessor-Based Systems Dr. Randa Elanwar
  • 16. 8086/8088 instruction set (SHR) Arithmetic and Logical Instructions: • SHR: Shift Logical Right: This instruction performs bit-wise right shifts on the operand word or byte that may reside in a register or a memory location, by the specified count in the instruction and inserts zeros in the shifted positions. • The result is stored in the destination operand. This instruction shifts the operand through carry flag. 16Microprocessor-Based Systems Dr. Randa Elanwar
  • 17. 8086/8088 instruction set (SAR) Arithmetic and Logical Instructions: • SAR: Shift Arithmetic Right: This instruction performs right shifts on the operand word or byte, that may be a register or a memory location by the specified count in the instruction and inserts the most significant bit of the operand in the newly inserted positions. The result is stored in the destination operand. • This shift operation shifts the operand through carry flag. 17Microprocessor-Based Systems Dr. Randa Elanwar
  • 18. 8086/8088 instruction set (ROR) Arithmetic and Logical Instructions: • ROR: Rotate Right without Carry: This instruction rotates the contents of the destination operand to the right (bit-wise) either by one or by the count specified in CL, excluding carry. • The least significant bit is pushed into the carry flag and simultaneously it is transferred into the most significant bit position at each operation. The remaining bits are shifted right by the specified positions. • The operand may be a register or a memory location but it cannot be an immediate operand. 18Microprocessor-Based Systems Dr. Randa Elanwar
  • 19. 8086/8088 instruction set (ROL) Arithmetic and Logical Instructions: • ROL: Rotate Left without Carry: This instruction rotates the content of the destination operand to the left by the specified count (bit-wise) excluding carry. • The most significant bit is pushed into the carry flag as well as the least significant bit position at each operation. The remaining bits are shifted left subsequently by the specified count positions. • The operand may be a register or a memory location. 19Microprocessor-Based Systems Dr. Randa Elanwar
  • 20. 8086/8088 instruction set (RCR) Arithmetic and Logical Instructions: • RCR: Rotate Right through Carry: This instruction rotates the contents (bit-wise) of the destination operand right by the specified count through carry flag (CF). • For each operation, carry flag is pushed into the MSB of the operand, and the LSB is pushed into carry flag. The remaining bits are shifted right by the specified count positions. • The operand may be a register or a memory location 20Microprocessor-Based Systems Dr. Randa Elanwar
  • 21. 8086/8088 instruction set (RCL) Arithmetic and Logical Instructions: • RCL: Rotate Left through Carry: This instruction rotates (bit-wise) the contents of the destination operand left by the specified count through the carry flag (CF). • For each operation, the carry flag is pushed into LSB, and the MSB of the operand is pushed into carry flag. The remaining bits are shifted left by the specified positions. • The operand may be a register or a memory location. The count for rotation or shifting is either 1 or is specified using register CL, in case of all the shift and rotate instructions. 21Microprocessor-Based Systems Dr. Randa Elanwar