- The document proposes improved methods for accelerating bilateral filters using FPGAs by modifying the bilateral grid technique and implementing a fully pipelined architecture. - It proposes allowing the window radius on the original image to vary rather than just on the grid, and fully pipelines the processing to minimize hardware resource increases with window radius. - An evaluation on an FPGA board shows the proposed method achieves faster speeds and smaller circuit sizes than other methods while maintaining noise removal quality even with large images and window radii.