Lane Dectection

1. 2017 Progress In Electromagnetics Research Symposium — Spring (PIERS), St Petersburg, Russia, 22–25 May
Digital Beamforming Based on FPGA for Phased Array Radar
Wenjing Shang, Zheng Dou, Wei Xue, and Yingsong Li
College of Information and Communications Engineering
Harbin Engineering University, Harbin 150001, China
Abstract— Beamforming is a significant signal processing technique which can achieve high
gain and low sidelobe. It has been widely studied and integrated into various radar systems. In
this paper, we mainly focus on the realization of high-speed data sampling, storage and multi-
beam forming realizing on FPGA platform. The designed scheme can be integrated with RF
circuit to construct a joint test system for evaluating high speed radar systems through Ethernet
interfaces. The FPGA based DBF system with low cost can facilitate the design flexibility and
reliability, which is also easy to upgrade in practical engineering.
1. INTRODUCTION
Digital beamforming can simultaneously obtain multiple beams, which has been widely investigated
and applied in various communication systems. With the development of radar technologies, the ca-
pability of radar is becoming more and more complex. Computational requirements to process the
data obtained from increased number of receivers are also growing sharply. The signal acquisition
rate, transfer rate and high-speed signal processing for radar are becoming more and more inter-
esting in recent decades. Using the FPGA in beamforming could enhance the flexibility and might
overcome many issues that are existing in traditional analog systems [1]. FPGA is a programmable
logic device with good programmability, repeatable configuration, its flexibility greatly reduces
hardware development cycle, and enhances the commissioning phase of the adjustable. FPGA can
carry out complicated algorithm processing, and can be used to implement high-speed serial trans-
mission in high speed serial transceiver. Thus, multi-channel high-speed data acquisition, storage,
transmission and processing system based on the FPGA are in wide range of applications. As
the requirement for building high directivity radar increases, the higher data rate and the number
of antennas also bring huge amount of data of high-speed transmission pressure. In this paper,
we bring out a digital beamforming architecture based on Xilinx Kintex-7 series FPGA, including
multi-channel high-speed signal acquisition, storage, processing and transmission for phased array
radar receiving system. Benefit from the high effective programmable and flexibility FPGA, this
architecture can realize the multi-channel synchronous data acquisition of high speed signal to meet
the requirements of the large capacity data storage and high-speed transmission.
2. SYSTEM ARCHITECTURE
In digital beamforming receiver, the phase shifting and amplitude scaling of antenna elements are
numerically controlled, and the signal from each antenna elements are digitalized by A/D converters,
which will be processed by digital processing platform. Generally, analog RF translators known as
down-conversion is required before the signal processing is transformed to the A/D converters.
Figure 1 gives the detailed configuration of the highly flexible, easily expandable architecture of
digital beamforming solution. In this system, high directivity radars with large amount of receive
antennas output analog signals, which contain the information including phase, velocity and posi-
tion of an object. The analog signals are sampled, quantified and converted into digital data using
12 bit, 65 MS/s high speedA/D converters. Series digital data are delivered to FPGA via LVDS
interfaces for further processing. For raw radar data transmission, high speed cache module and
Ethernet protocols module are embedded on the FPGA platform [3]. However, the raw data might
result in high data transmission pressure in Ethernet channel and high demanding for background
processing system, which would increase the hardware cost. In order to decrease the transmission
and processing pressure, high throughput preprocessing modules such as digital down converter,
digital filters and multipliers can be integrated into the FPGA before the transmission via Eth-
ernet channel. All the raw data or pre-processed data in FPGA are processed with appropriate
packet headers and communicated with background processing system using Ethernet protocol via
Ethernet channel. High throughput router or switch acts as a bridge between sample module and
processing module, which can reduce coupling between the front-end and back-end and enhance
the scalability of the system. The digital beamforming and other complex signal processing can be
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2. 2017 Progress In Electromagnetics Research Symposium — Spring (PIERS), St Petersburg, Russia, 22–25 May
implemented on computing platform behind the router or switch. According to budget, applica-
tions, and real time requirement, we can mount various types of computing platforms on the router
or switch via cables, such as computers, local high performance server, FPGA/DSP platforms, or
public computing clouds.
Figure 1: Architecture of DBF system.
3. REALIZATION OF SYSTEM
In this paper, a DBF system is realized. We use TI AFE5851 EVM as the A/D converter which
can provide at most 8 channels for analog input with 12-bit resolution and up to 65 MS/s. Kintex-
7 FPGA Evaluation Kit is used for data conversion, which is developed based on Vivado-2016
environment. Since the system operates in LAN network, a TL-SG1024DT 1000M-switch is used.
The computing platform is a personal computer with Intel Core (TM) i5-4460 CPU and 4 GB RAM,
installed Windows 10 64 bit operating system.
In this DBF system, a 2-channel A/D converter configuration at 20 MS/s sampling rate is used.
It results in a transfer rate of 480 Mbps. We define a non-standard frame protocol to format the
data from each channel for data transmission and synchronization in back-end. The data structure
is shown in Figure 2. One Ethernet frame only contains data from one of the channels, the channel
number is tagged at the first 8 bits of the Ethernet frame, and time stamp stands at the second
8 bits. The rests are filled with sample data. From Figure 3, we can see that raw data from one
channel have been converted to Ethernet transmission standard. This non-standard protocol leads
to less redundant data and achieves more useful data, improving the transfer efficient.
For 4-channel A/D converter configuration at 20 MS/s sampling rate, it results in a data transfer
rate of 960 Mbps, which is close to the 1000 M-Ethernet transmission capacity for one cable. To
maximumly make use of the band in LAN network, the Jumbo Frame mode can be used, which
means that there are more useful data in one frame, increasing the throughput. Jumbo Frame
mode may cause error in large amount numbers of data transmission [4]. Thus, software Wireshark
is used to test the network quality with special test data. It can be seen from Figure 4 that in
Jumbo Frame mode configuration the receiving data are in successive increasing mode, indicating
that Jumbo Frame mode is useful in LAN network for beamforming transforming.
As Xilinx Kintex-7 series FPGA in this realization can provide enough I/O ports to connect more
channel from A/D converters and increase receiving sampling data, it is very easy to introduce new
receiver units. When sampling rate or A/D receiver elements increases, the data rate would exceed
the transmission capacity. By adding more 1000 M-Ethernet network cables without changing other
modules,the system can easily adopt an economical and flexible solution to expand the transmission
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3. 2017 Progress In Electromagnetics Research Symposium — Spring (PIERS), St Petersburg, Russia, 22–25 May
channel.
i
Number of Bytes
Ti
Channel Label
Data j Tj
1~N 1 1 1~N
Timestamp
1 1
Data
Figure 2: The frame structure of data transferred.
Figure 3: The test of formatted data transferring to Ethernet network.
Figure 4: Test packets captured in Jumbo Frame mode configuration.
4. CONCLUSION
In this paper, we have developed a multi-beam forming system for phased array radar. We mainly
focus on the performance of large amounts of data transmission and processing for the entire system.
The Kintex-7 FPGA is used to transform data from A/D converters and package the sampling data
with Ethernet protocol. Through 1000M-Ethernet, sampling digital signal could be transferred to
multi-beam forming processing units such as PC, server, FPGA/DSP, and cloud. The proposed
scheme enjoys advantages of reconfigurable design and low hardware cost. The system can achieve
high-speed data sampling storage and easy to carry out multiple beamforming at the same time.
ACKNOWLEDGMENT
This paper is funded by the International Exchange Program of Harbin Engineering University
for Innovation-oriented Talents Cultivation. This work was also partially supported by the Na-
tional Key Research and Development Program of China-Government Corporation Special Pro-
gram (2016YFE0111100), the Science and Technology Innovative Talents Foundation of Harbin
(2016RAXXJ044), International Science and Technology Cooperation Program of China (2014
DFR10240), and Science Foundation of Heilongjiang Province QC2015075.
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4. 2017 Progress In Electromagnetics Research Symposium — Spring (PIERS), St Petersburg, Russia, 22–25 May
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