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Verilog code for decoder
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verilog coder for decoder 3*8
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Verilog code for decoder
1.
Verilog code for
3*8 decoder module decoder(a,b,c, z); input a,b,c; output [7:0] z; wire abar, bbar,cbar ; assign abar =~ a; assign bbar =~ b; assign cbar =~ c; assign z[0] = abar & bbar & cbar ; assign z[1] = abar & bbar & c ; assign z[2] = abar & b & cbar ; assign z[3] = abar & b & c ; assign z[4] = a & bbar & cbar ; assign z[5] = a & bbar & c ; assign z[6] = a & b & cbar ; assign z[7] = a & b & c ; endmodule
2.
Verilog code for
3*8 decoder( alternate style of coding) module decoder(a,b,c, z); input a,b,c; output [7:0] z; wire abar, bbar,cbar ; not inv1 ( abar, a); not inv2 ( bbar, b); not inv3 ( cbar, c); and a0 ( z[0],abar,bbar,cbar); and a1 ( z[1],abar,bbar,c); and a2 ( z[2],abar,b,cbar); and a3 ( z[3],abar,b,c); and a4 ( z[4],a,bbar,cbar); and a5 ( z[5],a,bbar,c); and a6 ( z[6],a,b,cbar); and a7 ( z[7],a,b,c); endmodule
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