International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET)
6545(Print), ISSN 0976 – 6553(Online) Volume 4, Iss...
International Journal of Electrical Engineering and Technology (IJEET)
6545(Print), ISSN 0976 – 6553(Online) Volume 4, Iss...
International Journal of Electrical Engineering and Technology (IJEET)
6545(Print), ISSN 0976 – 6553(Online) Volume 4, Iss...
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 –
6545(Print), ISSN 0976 – 6553(Online) ...
International Journal of Electrical Engineering and Technology (IJEET)
6545(Print), ISSN 0976 – 6553(Online) Volume 4, Iss...
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Performance evaluation of reversible logic based cntfet demultiplexer 2

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Performance evaluation of reversible logic based cntfet demultiplexer 2

  1. 1. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 53 PERFORMANCE EVALUATION OF REVERSIBLE LOGIC BASED CNTFET DEMULTIPLEXER Y.Varthamanan1 , V.Kannan2 1 Research scholar, Sathyabama University, Chennai, Tamilnadu, India - 600119 2 Principal, Jeppiaar Institute of Technology, Kunnam, Tamilnadu, India -631604 ABSTRACT This paper discuss about the design and analysis of a demultiplexer that is realized using carbon nano tube transistor using reversible logic. Reversible logic realization of the digital circuits offers numerous advantages then the conventional circuit design. Power analysis has been performed using HSPICE simulation software and the results are obtained for the 1:2 and 1:4 demultiplexer transient behavior and the power consumption obtained is 0.8 and 1.6 nano watts respectively. Comparative analysis has been performed with the conventional demultiplexer design to validate the proposed design performance. Keywords: CNTFET, Demultiplexer, Power, Reversible Logic I. INTRODUCTION The nano electronic is one of the greatest emerging fields of Nano Technology for developing such kinds of computer systems and other electronic gadgets. The Nano technology is being introducing in every fields of the Science and Technology such as in Bio technology, Bio Medical Science, Medical Science, Research, Aerospace and education etc. Nanotechnology is increasingly being used in consumer products across the globe. Nanoelectronics encompass nanoscale circuits and devices including (but not limited to) ultra-scaled FETs, quantum SETs, RTDs, spin devices, super lattice arrays, quantum coherent devices, molecular electronic devices, and carbon nanotubes. INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET) ISSN 0976 – 6545(Print) ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), pp. 53-62 © IAEME: www.iaeme.com/ijeet.asp Journal Impact Factor (2013): 5.5028 (Calculated by GISI) www.jifactor.com IJEET © I A E M E
  2. 2. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 54 In designing of computer depends upon the fundamental components as AND, NAND, OR, NOR, NOT and XOR gates. The designing of combinational circuits, memory and registers also depends upon these basic gates. To develop these logic gates at nano scale (10-9 ), the whole computer can be developed with nano electronics components. [8]. CNT as a channel in the Field Effect Transistors (FET) of both n-CNFET and p- CNFET types that are used. Because of its very small size, it has been s that a CNT-based FET switches reliably using much less power than a silicon-based device, and thus the new device will consume less power than traditional t-gate multiplexer. CNT device uses the fundamental Lorentz magnetic force from the basic laws of Electromagnetic as a switching mechanism between two conducting CNTs. Since a demultiplexer is a fundamental logic block, the new devices can have a wide range of applications in a wide variety of nano circuits. The most desirable future work involved in CNTFETs will be the transistor with higher reliability, cheap production cost, or the one with more enhanced performances. II. CARBON NANO TUBE FET Carbon nano tube structures are prominent in reducing the packaging density of the very large scale integrated circuits. The exceptional electrical properties of carbon nanotubes arise from the unique electronic structure of graphene itself that can roll up and form a hollow cylinder. The circumference of such carbon nanotube can be expressed in terms of a chiral vector: Ĉh=nâ1+mâ2 which connects two crystallographically equivalent sites of the two-dimensional graphene sheet. Here n and m are integers and â1 and â2 are the unit vectors of the hexagonal honeycomb lattice. Therefore, the structure of any carbon nanotube can be described by an index with a pair of integers (n,m) that define its chiral vector. A carbon Nanotube’s band gap is directly affected by its chirality and diameter. If those properties can be controlled, CNTs would be a promising candidate for future nano- scale transistor devices. Moreover, because of the lack of boundaries in the perfect and hollow cylinder structure of CNTs, there is no boundary scattering. CNTs are also quasi- 1D materials in which only forward scattering and back scattering are allowed, and elastic scattering mean free paths in carbon nanotubes are long, typically on the order of micrometers. As a result, quasi-ballistic transport can be observed in nanotubes at relatively long lengths and low fields.[1]. Multi walled carbon nanotubes (MWCNTs) have huge potential for applications in electronics because of both their metallic and semiconducting properties and their ability to carry high current. CNTs can carry current density of the order 10 µA/nm2, while standard metal wires have a current carrying capability of the order 10 nA/nm2. Semiconducting CNTs have been used to fabricate CNTFETs, which show promise due to their superior electrical characteristics over silicon based MOSFETs.[7].
  3. 3. International Journal of Electrical Engineering and Technology (IJEET) 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May Fig..1 Ballistic model of CNTFET has numerous advantages over other models. Carbon nano tube is embedded between the insulator and the sio role in deciding the electrical characteristics. Fig. 2. Ballistic Carbon Nano Tube Field Effect Transistor The valence and conduction bands of the carbon nanotube are symmetric, which allows complementary structures in appli implies the possibility of deriving carbon nanotube transistors. Both the metallic and semi conducting nanotubes can be exploited in integrated circuits as interconnection and act devices respectively [3-6]. Carbon nanotubes have shown reliability issues when operated under high electric field or temperature gradients.[7]. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 55 Multi-Walled Nanotube Transistor Ballistic model of CNTFET has numerous advantages over other models. Carbon nano tube is embedded between the insulator and the sio2 layers. Chirality plays an important role in deciding the electrical characteristics. Ballistic Carbon Nano Tube Field Effect Transistor The valence and conduction bands of the carbon nanotube are symmetric, which allows complementary structures in applications. The nearly ballistic transport at low bias implies the possibility of deriving carbon nanotube transistors. Both the metallic and semi conducting nanotubes can be exploited in integrated circuits as interconnection and act Carbon nanotubes have shown reliability issues when operated under high electric [7]. , ISSN 0976 – June (2013), © IAEME Ballistic model of CNTFET has numerous advantages over other models. Carbon hirality plays an important The valence and conduction bands of the carbon nanotube are symmetric, which cations. The nearly ballistic transport at low bias implies the possibility of deriving carbon nanotube transistors. Both the metallic and semi conducting nanotubes can be exploited in integrated circuits as interconnection and active Carbon nanotubes have shown reliability issues when operated under high electric
  4. 4. International Journal of Electrical Engineering and Technology (IJEET) 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May III. REVERSIBLE LOGIC IN DIGITAL CIRCUITS A Reversible circuit has the facility to generate a unique output vector from each input vector, and vice versa .The gate/ circuit does not loose information is called Number of inputs is equal to the number of outputs. input to other gate or as a primary output is called garbage. gate are called “garbage”. Fig.3 represents reversible logic gate with garbage. represents typical Feynman gate. Table I represents the truth table of 2X2 Feynman Gate. Fig. 3. A typical reversible logic component Table I: Use as many outputs of every gate as possible, and thus minimize the garbage outputs. Do not create more constant inputs to gates that are absolutely necessary. Use as less number of reversible gates as possible to achieve the goal. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 56 REVERSIBLE LOGIC IN DIGITAL CIRCUITS A Reversible circuit has the facility to generate a unique output vector from each put vector, and vice versa .The gate/ circuit does not loose information is called equal to the number of outputs. Every gate output that is not used as input to other gate or as a primary output is called garbage. The unutilized outputs from a Fig.3 represents reversible logic gate with garbage. represents typical Feynman gate. Table I represents the truth table of 2X2 Feynman Gate. A typical reversible logic component Fig. 4. Feynman gate Table I: 2 x 2 Feynman Gate truth table Use as many outputs of every gate as possible, and thus minimize the garbage outputs. Do not create more constant inputs to gates that are absolutely necessary. Use as less number of s as possible to achieve the goal. , ISSN 0976 – June (2013), © IAEME A Reversible circuit has the facility to generate a unique output vector from each put vector, and vice versa .The gate/ circuit does not loose information is called reversible. Every gate output that is not used as lized outputs from a Fig.3 represents reversible logic gate with garbage. Fig.4 represents typical Feynman gate. Table I represents the truth table of 2X2 Feynman Gate. Use as many outputs of every gate as possible, and thus minimize the garbage outputs. Do not create more constant inputs to gates that are absolutely necessary. Use as less number of
  5. 5. International Journal of Electrical Engineering and Technology (IJEET) 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May Table II is the truth table of the 4X4 Feynman gate. Table II: IV. REVERSIBLE LOGIC IMPLEMENTATION IN CNTFET Logically reversible process is that the output can b input of a logic gate, and the converse is true. A one to one mapping exists between the input string and output string. Mathematically speaking the function is bijective. An example of the logically reversible gate is NOT Realization of the reversible logic using CNTFET is shown in the Fig.6 and Fig.7 for the proposed 1X2 and 1X4 demultiplexer circuits respectively. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 57 Fig. 5. Fredkin gate Table II is the truth table of the 4X4 Feynman gate. Table II: 4x 4 Feynman Gate truth table REVERSIBLE LOGIC IMPLEMENTATION IN CNTFET Logically reversible process is that the output can be obtained by knowing the binary input of a logic gate, and the converse is true. A one to one mapping exists between the input string and output string. Mathematically speaking the function is bijective. An example of the logically reversible gate is NOT gate. Realization of the reversible logic using CNTFET is shown in the Fig.6 and Fig.7 for the proposed 1X2 and 1X4 demultiplexer circuits respectively. , ISSN 0976 – June (2013), © IAEME e obtained by knowing the binary input of a logic gate, and the converse is true. A one to one mapping exists between the input string and output string. Mathematically speaking the function is bijective. An example of the Realization of the reversible logic using CNTFET is shown in the Fig.6 and Fig.7 for
  6. 6. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 58 Fig. 6. 1:2 DEMUX Realization Demultiplexer realization using ballistic model of CNTFET is a novel approach in the digital circuit designing. This model has electrical and physical properties that are superior to other models. Fig. 7. 1:4 DEMUX Realization M9 41 M2 3 B=0 2 B=0 M8 3 2 4 S'A 5 A 2 DEMUX 1:2 M1 SA 5 M5 A 2 S' M4 M7 6 S' Vdd S 7 M3 S S S M6 M10
  7. 7. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 59 V. RESULTS AND CONCLUSION Fig. 8 and Fig.9 represents the 1X2 and 1X4 demultiplexer transient response using reversible logic respectively. Fig.8 Transient Response of Reversible Logic 1:2 Demultiplexer Fig.9 Transient Response of Reversible Logic 1:4 Demultiplexer Fig.10 and Fig.11 represents the 1X2 and 1X4 CNTFET demultiplexer transient response using reversible logic respectively.
  8. 8. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 60 Fig. 10Transient Response of Reversible Logic based CNTFET 1:2 Demultiplexer Fig.11 Transient Response of Reversible Logic based CNTFET 1:4 Demultiplexer Table III gives the details of the number of transistors that have been used for reversible CNTFET and other models. Table IV elaborates the power consumption of 1X2 and 1X4 demultiplexer circuits using CNTFET reversible implementation and CMOS implementation.
  9. 9. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 61 Table III: No. of transistors for Different Demultiplexer design Table 1V: Power Analysis of Different Demultiplexer Design Fig.12 represents the comprehensive analysis of power consumed by CMOS, Reversible and Reversible realized CNTFET. Fig. 12 Comparative analysis of Power Consumption Demultiplexer has been designed using CNTFET with reversible logic. Comparison table of power dissipation shows a greatest amount of power reduction has been achieved with the standard CNTFET model over a conventional CMOS. The dynamically reconfigurable universal cells exhibit the possibility to realize dense, regular and highly reconfigurable circuits in platform-based system on chip design. The unwanted growth of metallic tubes during the fabrication of CNTs is a major challenge that will affect the fabrication of robust CNT-based circuits. Description No. of Transistors CMOS Reversible Reversible CNTFET 1:2 DEMUX 14 10 10 1:4 DEMUX 36 22 22 Description Total Power Dissipation in nano watts CMOS Reversible Reversible CNTFET 1:2 DEMUX 6.473 3.176 0.860 1:4 DEMUX 9.782 6.353 1.765
  10. 10. International Journal of Electrical Engineering and Technology (IJEET) 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 3, May REFERENCES [1] H. Dai, A. Javey, E. Pop, D. Mann, Y. Lu, "Electrical Properties and Field Transistors of Carbon Nanotubes," Nano: Brief Reports and Reviews 1, 1 (2006). [2] Anisur Rahman, Jing Guo, Su nanotransistors. Electron Devices, IEEE [3] Dafeng Zhou, Tom J Kazmierski and Bashir M Al of a numerical ballistic CNT model for Specification and Design Languages 2008, [4] I. O’Connor, J. Liu, F. Gaffiot. “CNTFET [5] Bipul C. Paul, Shinobu Fujita, Masaki Ok analysis of circuit performance of ballistic CNFET. In San Francisco, CA, USA, 24-28 July 2006. [6]www.siemens.com/innovation/en/about_fande/corp_technology/partnerships_experts/uc_b erkeley.htm [7] www.wikipedia.org [8] Comparative Study: MOSFET and CNTFET and the Effect of Length Modulation Kuldeep Niranjan, Sanjay Srivastava, Jaikaran Singh, Mukesh Tiwari Recent Technology and Engineering (IJRTE) ISSN: 2277 2012 [9] Kavita L.Awade and Dr .Babasaheb Ambedkar in Biomedical Engineering”, International Engineering & Technology (IJECET), Volume 0976- 6464, ISSN Online: 0976 AUTHORS Y.Varthamanan Master Degree in Applied Electronics from Sathyabama University in the year 2007. Currently he is doing PhD in Sathyabama University. He is work Assistant Professor in Department Chennai. His interested areas of research are Nano Electronic and Mixed Signal circuits. V.Kannan was born in Ariyalore, Tamilnadu, India in 1970. He received Bachelor Degree in Electronics and Kamarajar University in the year1991, control from BITS, Pilani in the ye University, Chennai, in the year 2006. His interested areas of research are Optoelectronic Devices, VLSI Image Processing. He has 170 Conferences to his credit. He has 20 Principal, Jeppiaar Institute of Technology, Kunnam, Tamilnadu, India. He is a life member of ISTE. International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6553(Online) Volume 4, Issue 3, May - June (2013), © IAEME 62 A. Javey, E. Pop, D. Mann, Y. Lu, "Electrical Properties and Field Transistors of Carbon Nanotubes," Nano: Brief Reports and Reviews 1, 1 (2006). Anisur Rahman, Jing Guo, Supriyo Datta, and Mark S. Lundstrom. Theory of ballistic Electron Devices, IEEE, 50(9):1853–1864, September 2003. Dafeng Zhou, Tom J Kazmierski and Bashir M Al-Hashimi, VHDL-AMS implementation of a numerical ballistic CNT model for logic circuit simulation - In IEEE Specification and Design Languages 2008, Southampton, SO17 1BJ, UK, 2008. I. O’Connor, J. Liu, F. Gaffiot. “CNTFET-based logic circuit design. IEEE-June 2006. Bipul C. Paul, Shinobu Fujita, Masaki Okajima, and Thomas Lee.Modeling and analysis of circuit performance of ballistic CNFET. In 2006 Design Automation Conference 28 July 2006. www.siemens.com/innovation/en/about_fande/corp_technology/partnerships_experts/uc_b [8] Comparative Study: MOSFET and CNTFET and the Effect of Length Modulation Kuldeep Niranjan, Sanjay Srivastava, Jaikaran Singh, Mukesh Tiwari International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-1, Issue Dr .Babasaheb Ambedkar, “Emerging Trends of Nanotechnology International Journal of Electronics and Communication Technology (IJECET), Volume 1, Issue 1, 2010, pp. 25 - 32, ISSN Print: 976 –6472. Y.Varthamanan was born in Arani, Tamilnadu, India in 1967. He received Master Degree in Applied Electronics from Sathyabama University in the year 2007. Currently he is doing PhD in Sathyabama University. He is work Assistant Professor in Department of ECE in Jeppiaar Engineering College, Chennai. His interested areas of research are Nano Electronics, VLSI Design was born in Ariyalore, Tamilnadu, India in 1970. He received Bachelor Degree in Electronics and Communication Engineering from Madurai Kamarajar University in the year1991, Masters Degree in Electronics and control from BITS, Pilani in the year 1996 and Ph.D., from Sathyabama University, Chennai, in the year 2006. His interested areas of research are Design, Nano Electronics, Digital Signal Processing and Research publications in National / International Journals / has 20 years of experience in teaching and presently working as Principal, Jeppiaar Institute of Technology, Kunnam, Tamilnadu, India. He is a life member , ISSN 0976 – June (2013), © IAEME A. Javey, E. Pop, D. Mann, Y. Lu, "Electrical Properties and Field-Effect Transistors of Carbon Nanotubes," Nano: Brief Reports and Reviews 1, 1 (2006). priyo Datta, and Mark S. Lundstrom. Theory of ballistic AMS implementation IEEE Forum on Southampton, SO17 1BJ, UK, 2008. June 2006. ajima, and Thomas Lee.Modeling and 2006 Design Automation Conference, www.siemens.com/innovation/en/about_fande/corp_technology/partnerships_experts/uc_b [8] Comparative Study: MOSFET and CNTFET and the Effect of Length Modulation International Journal of 1, Issue-4, October f Nanotechnology ournal of Electronics and Communication , ISSN Print: was born in Arani, Tamilnadu, India in 1967. He received Master Degree in Applied Electronics from Sathyabama University in the year 2007. Currently he is doing PhD in Sathyabama University. He is working as in Jeppiaar Engineering College, s, VLSI Design was born in Ariyalore, Tamilnadu, India in 1970. He received his from Madurai Masters Degree in Electronics and ., from Sathyabama University, Chennai, in the year 2006. His interested areas of research are Design, Nano Electronics, Digital Signal Processing and nal / International Journals / years of experience in teaching and presently working as Principal, Jeppiaar Institute of Technology, Kunnam, Tamilnadu, India. He is a life member

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