SystemVerilog Assertions (SVA) in the Design/Verification Process


Published on

  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

SystemVerilog Assertions (SVA) in the Design/Verification Process

  1. 1. DVClub - SVSystemVerilog Assertions (SVA)in the Design/Verification ProcessEric DealPresident, Cyclic Design
  2. 2. Benefits of Using AssertionsI have found that adding assertions shortenverification time and improve the quality of mydesigns:● Less time to identify and debug failures● Improve designer/verification communication● Document design behavior● Detect unobservable faults● Ease integration of reused/IP modulesIncorporate them early in the design cycle (during RTLcreation) to benefit throughout the verification process
  3. 3. BackgroundI began using OVL assertions when they werestandardized by Accellera:● Simple, but fairly inflexible● Made the design “messy” since instantiated asmodulesLearned SVA when evaluating formal tools● Provided power, flexibility, concise syntax● Clean way of creating simple assertions● Inlined in RTL, but less messy than OVL
  4. 4. Problems using SVASVA presented its own set of problems:● Difficult to construct anything besides relativelysimple assertions● Didnt use the more complex operators● Attempts to create moderately complex assertions,often resulted in them triggering incorrectly;subsequently I would remove these since the timeto debug them was not worth the effort.
  5. 5. Zocalo ZazzApproached by Zocalo to provide feedback on theirnew tool Zazz● Visual SVA addressed the creation issues, allowingme to create complex assertions without becoming anexpert in SVA syntax● More importantly, Zazz provides a methodology todebug assertions at the time of creationDebugging assertions prior to use is critical● This is why most companies use predefined assertiontemplates (like OVL) – not flexible, but debugged.
  6. 6. Visual SVAZazz solves the creation problem by representing assertionsgraphically on a 2-dimensional canvas which conveys thetemporal (left to right) as well as the concurrent (top to bottom)nature of assertions.This mimics the way that I like to think and makes it easy tocreate assertions and understand the relationships between theoperatorsTemporalConcurrency
  7. 7. Visual SVAVisual SVA also helps in creating structurally andsyntactically correct SVAs:syntax error (incorrect signal name)structural error – unterminated sequence
  8. 8. Debugging AssertionsVisual SVA closes the loop between design intent andactual SVA behavior by creating a constrained-randomtestbench around each assertion.Assertion BehaviorDoes NotMatch Intent.Designer IntentCreatedAssertionActual BehaviorAllowed by AssertionDebug AssertionsBeforeThey Fail inSimulation
  9. 9. Ability to create quality assertions has a two-foldimpact on Cyclic Design:● Improved my internal verification and debug byquickly identifying both time and location oferrors in simulation. Assertions also identifiedcorner-case errors that do not propagate totestbench failures.● More importantly, they improve my customersexperience when using the IP.Impact to Cyclic Design
  10. 10. Example: FPGA RegressionDuring regression of Cyclic Designs ECC IP, I use anFPGA to run billions of correction operations.When a test fails, I replay the vector in simulation.In nearly all cases, an assertion fired indicating the rootcause of the failure, saving a tremendous amount ofdebug time and effort.assertion failuresimulationreplayIt should be noted that these were extreme corner-casebugs found only after billions of correction operations
  11. 11. Example: Assertions in IPCyclic Designs BCH ECC IP is parametrized to supportdifferent maximum ECC levels.A customer configured the logic for their application for60-bit ECC and ran the included testbench, whichresulted in an error. The problem was that the testbenchwas running a test using 64-bit ECC.Once assertions were enabled, three unrelatedassertions immediately flagged this particular problem.End-users should be educated of the values ofassertions already present in the design and beinstructed on how to enable them.
  12. 12. Customer FeedbackDid the assertions provide additional insights into the use of thesignals that was not covered in the Users Guide?“We had some assertion violations after integration, so we havemodified design to clear those violations.”Did the assertions flag real violations on the port interfaces orinternals?"We had at least one real violation flagged by assertion.”“We fixed some issues that might have created failure at a later stagein regression.”Overall, did you feel that the inclusion of the assertionsrepresented additional value in the IP?“Assertions are very powerful. It’s very effective to have in IP;apart from less debugging time, they give us more confidence.”