This document describes designing and simulating a 4-bit comparator using VHDL. It explains the theory of how a comparator works by comparing two binary numbers and determining if one is greater than, less than, or equal to the other. It provides the VHDL code to implement a 4-bit comparator and test bench code to simulate it by inputting different combinations of 4-bit numbers and observing the output. The simulation was successful in comparing the inputs as expected and generating the appropriate output signals to indicate less than, equal, or greater than.

1. Experiment–5
Objective: Design and simulate 4- bit Comparator using VHDL.
Requirement: Computer Software Requirement: XILINX 8.2 Software
Theory:
A digital comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number
is greater than, less than or equal to the other number.
A comparator used to compare two binary numbers each of four bits
is called a 4-bit magnitude comparator. It consists of eight inputs
each for two four bit numbers and three outputs to generate less
than, equal to and greater than between two binary numbers.
In a 4-bit comparator the condition of A>B can be possible in the
following four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
Similarly the condition for A<B can be possible in the following four
cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
The condition of A=B is possible only when all the individual bits of
one number exactly coincide with corresponding bits of another
number.

2. Circuit:
Truth Table:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

3. entity comparator_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
eq : out STD_LOGIC;
ag : out STD_LOGIC;
bg : out STD_LOGIC);
end comparator_4bit;
architecture Behavioral of comparator_4bit is
begin
ag <= '1' when (a> b)
else '0';
eq <= '1' when (a = b)
else '0';
bg <= '1' when (a < b)
else '0';
end Behavioral;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY comparator_tb IS
END comparator_tb;
ARCHITECTURE behavior OF comparator_tb is
COMPONENT comparator_4bit

4. PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
eq : OUT std_logic;
ag : OUT std_logic;
bg : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal eq : std_logic;
signal ag : std_logic;
signal bg : std_logic;
BEGIN
uut: comparator_4bit PORT MAP (
a => a,
b => b,
eq => eq,
ag => ag,
bg => bg
);

5. -- Stimulus process
stim_proc: process
begin
A<="0100";
B<="0010";
wait for 100 ns;
A<="0101";
B<="0010";
wait for 100 ns;
A<="1100";
B<="0011";
wait for 100 ns;
A<="0100";
B<="0100";
wait for 100 ns;
A<="0101";
B<="1100";
wait for 100 ns;
A<="1100";
B<="1100";
wait for 100 ns;
end process;
END;

6. OUTPUT:
RTL Schematic:
Wave From:

7. Result:
VHDL program to implement 4 bit comparator has been
successfully simulated.