Unit 1 Computer Architecture & Organization.pptx

MODULE I OVERVIEW OF COMPUTER
ARCHITECTURE & ORGANIZATION
Dr. Chandrashekhar Goswami
Associate Professor,
ASET-CSE,
Amity University, Gwalior
Madhya Pradesh

Suggested Text/Reference Books:
• Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer
Organization”, Fifth Edition, Tata McGraw-Hill.
• John P. Hayes, “Computer Architecture and Organization”, Third
Edition.
• William Stallings, “Computer Organization and Architecture: Designing
for Performance”, Eighth Edition, Pearson.

Components A CT S/V/Q/HA EE
Weightage (%) 5 15 10 70
Examination Scheme:

Computer
• A computer can be defined as a fast electronic calculating machine
that accepts the (data) digitized input information process it as per
the list of internally stored instructions and produces the resulting
information.
• List of instructions are called programs & internal storage is called
computer memory.

Computer types
The different types of computers are
• 1. Personal computers: - This is the most common type found in homes, schools,
Business offices etc.
• 2. Note book computers: - These are compact and portable versions of PC.
• 3. Work stations: - These have high resolution input/output (I/O) graphics
capability, but with same dimensions as that of desktop computer.
• These are used in engineering applications of interactive design work.
• 4. Enterprise systems: - These are used for business data processing in medium
to large corporations that require much more computing power and storage
capacity than work stations.
• 5. Super computers: - These are used for large scale numerical calculations
required in the applications like weather forecasting etc.

Functional unit
A computer consists of five functionally independent main parts:
• input,
• memory,
• arithmetic and logic,
• output, and
• control units.

Fig : Functional units of computer

• Input device accepts the coded information as source program i.e.
high level language.
• This is either stored in the memory or immediately used by the
processor to perform the desired operations.
• The program stored in the memory determines the processing steps.
• Basically the computer converts one source program to an object
program. i.e. into machine language.
• Finally the results are sent to the outside world through output
device.
• All of these actions are coordinated by the control unit.

Input unit: -
• The source program / high level language program / coded
information / simply data is fed to a computer through input
devices (keyboard) is a most common type.
• Whenever a key is pressed, one corresponding word or number is
translated into its equivalent binary code over a cable & fed either
to memory or processor.
• Joysticks, trackballs, mouse, scanners etc are other input devices.

Memory unit: -
• Its function into store programs and data.
• It is basically to two types
• 1. Primary memory
• 2. Secondary memory

1. Primary memory: - This is exclusively associated with the
processor and operates at the electronics speeds.
• Programs must be stored in this memory while they are being
executed.
• The memory contains a large number of semiconductors storage
cells.
• Each capable of storing one bit of information.
• These are processed in a group of fixed size called word.

• To provide easy access to a word in memory, a distinct address is
associated with each word location.
• Addresses are numbers that identify memory location.
• Number of bits in each word is called word length of the computer.
• Programs must reside in the memory during execution.
• Memory in which any location can be reached in a short and fixed
amount of time after specifying its address is called random-access
memory (RAM).

• The time required to access one word is called memory access time.
• Memory which is only readable by the user and contents of which
can’t be altered is called read only memory (ROM).
• Caches are the small fast RAM units, which are coupled with the
processor and are often contained on the same IC chip to achieve
high performance.

2. Secondary memory: -
• It is used where large amounts of data & programs have to be
stored, particularly information that is accessed infrequently.
• Examples: - Magnetic disks & tapes, optical disks (ie CD-ROM’s),
floppies etc.

Arithmetic logic unit (ALU):-
• Most of the computer operations are executed in ALU like addition,
subtraction, division, multiplication, etc.
• The operands are brought into the ALU from memory and stored in
high speed storage elements called register.
• Then according to the instructions, the operation is performed in
the required sequence.
• The control and the ALU are many times faster than other devices
connected to a computer system.
• This enables a single processor to control a number of external
devices such as key boards, displays, magnetic and optical disks,
sensors and other mechanical controllers.

Output unit:-
• Its basic function is to send the processed results to the outside
world.
• Examples:- Printer, speakers, monitor etc.
Control unit:-
• It effectively is the nerve center that sends signals to other units and
senses their states.
• The actual timing signals that govern the transfer of data between
input unit, processor, memory and output unit are generated by the
control unit.

BASIC OPERATIONAL CONCEPTS
• To perform a given task an appropriate program consisting of a list
of instructions is stored in the memory.
• Individual instructions are brought from the memory into the
processor, which executes the specified operations.
• Data to be stored are also stored in the memory.
• Examples: - Add LOCA, R0
• This instruction adds the operand at memory location LOCA, to
operand in register R0 & places the sum into register.

• This instruction requires the performance of several steps,
• 1. First the instruction is fetched from the memory into the processor.
• 2. The operand at LOCA is fetched and added to the contents of R0
• 3. Finally the resulting sum is stored in the register R0

• The preceding add instruction combines a memory access operation with an
ALU Operations.
• In some other type of computers, these two types of operations are performed
by separate instructions for performance reasons.
• Load LOCA, R1
• Add R1, R0
• Transfers between the memory and the processor are started by sending the
address of the memory location to be accessed to the memory unit and issuing
the appropriate control signals.
• The data are then transferred to or from the memory.

• Figure shows how the memory and the processor can be connected.
Fig : Connections between the processor and the memory

• In addition to the ALU & the control circuitry, the processor contains a
number of registers used for several different purposes.
• The instruction register (IR):- Holds the instructions that is currently being
executed.
• Its output is available for the control circuits which generates the timing
signals that control the various processing elements in one execution of
instruction.
• The program counter PC:-
• This is another specialized register that keeps track of execution of a program.
• It contains the memory address of the next instruction to be fetched and
executed.
• Besides IR and PC, there are n-general purpose registers R0 through Rn-1.

• The other two registers which facilitate communication with memory are: -
• 1. MAR – (Memory Address Register):- It holds the address of the location
to be accessed.
• 2. MDR – (Memory Data Register):- It contains the data to be written into or
read out of the address location.
Operating steps are
1. Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first
instruction of the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to
the memory.

4. After the time required to access the memory elapses, the address word is read
out of the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready
to be decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain
the required operands.
7. An operand in the memory is fetched by sending its address to MAR &
Initiating a read cycle.
8. When the operand has been read from the memory to the MDR, it is
transferred from MDR to the ALU.

9. After one or two such repeated cycles, the ALU can perform the desired
operation.
10. If the result of this operation is to be stored in the memory, the result is sent
to MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle
is initiated.
12. The contents of PC are incremented so that PC points to the next instruction
that is to be executed.

Interrupt:
• Normal execution of a program may be preempted (temporarily interrupted) if
some devices require urgent servicing, to do this one device raises an Interrupt
signal.
• An interrupt is a request signal from an I/O device for service by the processor.
• The processor provides the requested service by executing an appropriate
interrupt service routine.
• The Diversion may change the internal stage of the processor its state must be
saved in the memory location before interruption.
• When the interrupt-routine service is completed the state of the processor is
restored so that the interrupted program may continue.

BUS STRUCTURES
• The simplest and most common way of interconnecting various parts of the
computer.
• To achieve a reasonable speed of operation, a computer must be organized so
that all its units can handle one full word of data at a given time.
• A group of lines that serve as a connecting port for several devices is called a
bus.
• In addition to the lines that carry the data, the bus must have lines for address
and control purpose.

• Simplest way to interconnect is to use the single bus as shown
Fig: Single bus structure

• Since the bus can be used for only one transfer at a time, only two units can
actively use the bus at any given time.
• Bus control lines are used to arbitrate multiple requests for use of one bus.
• Single bus structure is
•  Low cost
•  Very flexible for attaching peripheral devices
• Multiple bus structure certainly increases, the performance but also increases
the cost significantly.

• All the interconnected devices are not of same speed & time, leads to a bit of a
problem.
• This is solved by using cache registers (i.e. buffer registers).
• These buffers are electronic registers of small capacity when compared to the
main memory but of comparable speed.
• The instructions from the processor at once are loaded into these buffers and
then the complete transfer of data at a fast rate will take place.

MULTIPLE-BUS ORGANIZATION:
• Most commercial processors provide multiple internal paths that enable several
transfers to take place in parallel.
• Figure depicts a three-bus structure used to connect the registers and the ALU
of a processor.
• All general-purpose registers are combined into a single block called the
register file.
• In VLSI technology, the most efficient way to implement a number of registers
is in the form of an array of memory cells similar to those used in the
implementation of random-access memories (RAMs).
• The register file in Figure is said to have three ports.

• There are two outputs, allowing the contents of two different registers to be
accessed simultaneously and have their contents placed on buses A and B.
• The third port allows the data on bus C to be loaded into a third register during
the same clock cycle.
• Buses A and B are used to transfer the source operands to the A and B inputs of
the ALU, where an arithmetic or logic operation may be performed.
• The result is transferred to the destination over bus C.
• If needed, the ALU may simply pass one of its two input operands unmodified
to bus C.
• We will call the ALU control signals for such an operation R=A or R=B.

Von Neumann architecture
• Historically there have been 2 types of Computers:
1.Fixed Program Computers – Their function is very specific and they
couldn’t be reprogrammed, e.g. Calculators.
2.Stored Program Computers – These can be programmed to carry out many
different tasks, applications are stored on them.
• Modern computers are based on a stored-program concept introduced by John
Von Neumann.
• In this stored-program concept, programs and data are stored in a separate
storage unit called memories.
• This novel idea meant that a computer built with this architecture would be
much easier to reprogram.

• The basic structure is like this,

• It is also known as ISA (Instruction set architecture) computer and is having three
basic units:
1.The Central Processing Unit (CPU)
2.The Main Memory Unit
3.The Input/Output Device
• Let’s consider them in detail.
• Control Unit –
A control unit (CU) handles all processor control signals. It directs all input and
output flow, fetches code for instructions, and controls how data moves around the
system.
• Arithmetic and Logic Unit (ALU) –
The arithmetic logic unit is that part of the CPU that handles all the calculations the
CPU may need, e.g. Addition, Subtraction, Comparisons.
• It performs Logical Operations, Bit Shifting Operations, and Arithmetic operations.
•

Figure – Basic CPU structure

1.Main Memory Unit (Registers) – Accumulator: Stores the results of
calculations made by ALU.
2.Program Counter (PC): Keeps track of the memory location of the next
instructions to be dealt with. The PC then passes this next address to the
Memory Address Register (MAR).
3.Memory Address Register (MAR): It stores the memory locations of
instructions that need to be fetched from memory or stored in memory.
4.Memory Data Register (MDR): It stores instructions fetched from memory
or any data that is to be transferred to, and stored in, memory.
5.Current Instruction Register (CIR): It stores the most recently fetched
instructions while it is waiting to be coded and executed.
6.Instruction Buffer Register (IBR): The instruction that is not to be executed
immediately is placed in the instruction buffer register IBR.

• Input/Output Devices – Program or data is read into main memory from
the input device or secondary storage under the control of CPU input
instruction.
• Output devices are used to output information from a computer.
• If some results are evaluated by the computer and it is stored in the computer,
then with the help of output devices, we can present them to the user.
• Registers – Registers refer to high-speed storage areas in the CPU. The data
processed by the CPU are fetched from the registers.
• There are different types of registers used in architecture.
• MAR (Memory Address Register) – This register holds the memory location
of the data that needs to be accessed.
MDR (Memory Data Register) – This register holds the data that is being
transferred to or from memory.

• AC (Accumulator) – This register holds the intermediate arithmetic and logic
results.
PC (Program Counter) – This register contains the address of the next
instruction to be executed.
CIR (Current Instruction Register) – This register contains the current
instruction during processing.
• Buses – Data is transmitted from one part of a computer to another, connecting
all major internal components to the CPU and memory, by the means of Buses.
Types:
• Data Bus: It carries data among the memory unit, the I/O devices, and the processor.
• Address Bus: It carries the address of data (not the actual data) between memory and
processor.
• Control Bus: It carries control commands from the CPU (and status signals from other
devices) in order to control and coordinate all the activities within the computer.

BASIC PROCESSING UNIT:
• The heart of any computer is the central processing unit (CPU).
• The CPU executes all the machine instructions and coordinates the activities
of all other units during the execution of an instruction.
• By looking at its internal structure, we can understand how it performs the
tasks of fetching, decoding, and executing instructions of a program.
• An high-performance processor can be built by making various functional
units operate in parallel.
• High-performance processors have a pipelined organization where the
execution of one instruction is started before the execution of the preceding
instruction is completed.
• In another approach, known as superscalar operation, several instructions are
fetched and executed at the same time.
• Pipelining and superscalar architectures provide a very high performance for
any processor.

• A typical computing task consists of a series of steps specified by a sequence
of machine instructions that constitute a program.
• A program is a set of instructions performing a meaningful task.
• An instruction is command to the processor & is executed by carrying out a
sequence of sub-operations called as micro-operations.
• Figure 1 indicates various blocks of a typical processing unit.
• It consists of PC, IR, ID, MAR, MDR, a set of register arrays for temporary
storage, Timing and Control unit as main units.

FUNDAMENTAL CONCEPTS:
• Execution of a program by the processor starts with the fetching of instructions
one at a time, decoding the instruction and performing the operations specified.
• From memory, instructions are fetched from successive locations until a
branch or a jump instruction is encountered.
• The processor keeps track of the address of the memory location containing the
next instruction to be fetched using the program counter (PC) or Instruction
Pointer (IP).
• After fetching an instruction, the contents of the PC are updated to point to the
next instruction in the sequence.
• But, when a branch instruction is to be executed, the PC will be loaded with a
different (jump/branch address).

Figure Main hardware components of a processor

• Instruction register, IR is another key register in the processor, which is used to
hold the op-codes before decoding.
• IR contents are then transferred to an instruction decoder (ID) for decoding.
• The decoder then informs the control unit about the task to be executed.
• The control unit along with the timing unit generates all necessary control
signals needed for the instruction execution.
• Suppose that each instruction comprises 2 bytes, and that it is stored in one
memory word.
• To execute an instruction, the processor has to perform the following three
steps:

• 1. Fetch the contents of the memory location pointed to by the PC. The
contents of this location are interpreted as an instruction code to be executed.
Hence, they are loaded into the IR/ID. Symbolically, this operation can be
written as IR←[[PC]]
• 2. Assuming that the memory is byte addressable, increment the contents of the
PC by 2, that is, PC←[PC] + 2
• 3. Decode the instruction to understand the operation & generate the control
signals necessary to carry out the operation. Carry out the actions specified by
the instruction in the IR.

• In cases where an instruction occupies more than one word, steps 1 and 2 must
be repeated as many times as necessary to fetch the complete instruction.
• These two steps together are usually referred to as the fetch phase; step 3
constitutes the decoding phase; and constitutes the execution phase.
• The main building blocks of a processor are interconnected in a variety of
ways.
• A very simple organization is shown in Figure.

• Figure shows an organization in which the arithmetic and logic unit (ALU) and all the
registers are interconnected through a single common bus, which is internal to the
processor.
• The data and address lines of the external memory bus are connected to the internal
processor bus via the memory data register, MDR, and the memory address register,
MAR, respectively.
• Register MDR has two inputs and two outputs.
• Data may be loaded into MDR either from the memory bus or from the internal
processor bus.
• The data stored in MDR may be placed on either bus.
• The input of MAR is connected to the internal bus, and its output is connected to the
external bus.
• The control lines of the memory bus are connected to the instruction decoder and
control logic block.
• This unit is responsible for issuing the signals that control the operation of all the
units inside the processor and for interacting with the memory bus.

• Registers may be provided for general-purpose use by the programmer.
• Three registers, Y, Z, and TEMP in Figure.
• They are used by the processor for temporary storage during execution of
some instructions.
• These registers are never used for storing data generated by one instruction for
later use by another instruction.
• The multiplexer MUX selects either the output of register Y or a constant value
4 to be provided as input A of the ALU.
• The constant 4 is used to increment the contents of the program counter.
• We will refer to the two possible values of the MUX control input Select as
Select4 and Select Y for selecting the constant 4 or register Y, respectively.

• As instruction execution progresses, data are transferred from one register to
another, often passing through the ALU to perform some arithmetic or logic
operation.
• The instruction decoder and control logic unit is responsible for implementing
the actions specified by the instruction loaded in the IR register.
• The decoder generates the control signals needed to select the registers
involved and direct the transfer of data.
• The registers, the ALU, and the interconnecting bus are collectively referred to
as the data path.

EXECUTION OF A COMPLETE INSTRUCTION:
• Let us now put together the sequence of elementary operations required to
execute one instruction.
• Consider the instruction
• Add (R3), R1
• which adds the contents of a memory location pointed to by R3 to register R1.
Executing this instruction requires the following actions:
• 1. Fetch the instruction.
• 2. Fetch the first operand (the contents of the memory location pointed to by
R3).
• 3. Perform the addition.
• 4. Load the result into Rl.

• Instruction execution proceeds as follows.
• In step 1, the instruction fetch operation is initiated by loading the contents of
the PC into the MAR and sending a Read request to the memory.
• The Select signal is set to Select4, which causes the multiplexer MUX to select
the constant 4.
• This value is added to the operand at input B, which is the contents of the PC,
and the result is stored in register Z.
• The updated value is moved from register Z back into the PC during step 2,
while waiting for the memory to respond.
• In step 3, the word fetched from the memory is loaded into the IR.

• Steps 1 through 3 constitute the instruction fetch phase, which is the same for all
instructions.
• The instruction decoding circuit interprets the contents of the IR at the beginning of
step 4.
• This enables the control circuitry to activate the control signals for steps 4 through 7,
which constitute the execution phase.
• The contents of register R3 are transferred to the MAR in step 4, and a memory read
operation is initiated.
• Then the contents of Rl are transferred to register Y in step 5, to prepare for the
addition operation.
• When the Read operation is completed, the memory operand is available in register
MDR, and the addition operation is performed in step 6.
• The contents of MDR are gated to the bus, and thus also to the B input of the ALU,
and register Y is selected as the second input to the ALU by choosing Select Y.
• The sum is stored in register Z, then transferred to Rl in step 7.
• The End signal causes a new instruction fetch cycle to begin by returning to step 1.

HARDWIRED CONTROL
• To execute instructions, the processor must have some means of generating the
control signals needed in the proper sequence.
• Computer designers use a wide variety of techniques to solve this problem.
• The approaches used fall into one of two categories:
• hardwired control and micro programmed control.
• We discuss each of these techniques in detail, starting with hardwired control
in this section.
• Consider the sequence of control signals given in Figure 7.
• Each step in this sequence is completed in one clock period.
• A counter may be used to keep track of the control steps, as shown in Figure
11.
• Each state, or count, of this counter corresponds to one control step.

• The required control signals are determined by the following information:
• 1. Contents of the control step counter
• 2. Contents of the instruction register
• 3. Contents of the condition code flags
• 4. External input signals, such as MFC and interrupt requests

• To gain insight into the structure of the control unit, we start with a simplified
• view of the hardware involved.
• The decoder/encoder block in Figure 11 is a combinational circuit that
generates the required control outputs, depending on the state of all its inputs.
• By separating the decoding and encoding functions, we obtain the more
detailed block diagram in Figure 12.
• The step decoder provides a separate signal line for each step, or time slot, in
the control sequence.
• Similarly, the output of the instruction decoder consists of a separate line for
each machine instruction.
• For any instruction loaded in the IR, one of the output lines INS1 through INSm
is set to 1, and all other lines are set to 0.

MICROPROGRAMMED CONTROL:
• ALU is the heart of any computing system, while Control unit is its brain.
• The design of a control unit is not unique; it varies from designer to designer.
• Some of the commonly used control logic design methods are;
• • Sequence Reg & Decoder method
• • Hard-wired control method
• • PLA control method
• • Micro-program control method

• The control signals required inside the processor can be generated using a
control step counter and a decoder/ encoder circuit.
• Now we discuss an alternative scheme, called micro programmed control, in
which control signals are generated by a program similar to machine language
programs.

• A control word (CW) is a word whose individual bits represent the various control signals.
• Each of the control steps in the control sequence of an instruction defines a unique
combination of 1s and 0s in the CW.
• We have assumed that Select Y is represented by Select = 0 and Select4 by Select = 1.
• A sequence of CWs corresponding to the control sequence of a machine instruction constitutes
the micro routine for that instruction, and the individual control words in this micro routine are
referred to as microinstructions.
• The micro routines for all instructions in the instruction set of a computer are stored in a
special memory called the control store.
• The control unit can generate the control signals for any instruction by sequentially reading the
CWs of the corresponding micro routine from the control store.
• To read the control words sequentially from the control store, a micro program counter (μPC)
is used.
• Every time a new instruction is loaded into the IR, the output of the block labeled "starting
address generator" is loaded into the μPC.
• The μPC is then automatically incremented by the clock, causing successive microinstructions
to be read from the control store.
• Hence, the control signals are delivered to various parts of the processor in the correct
sequence.

• One important function of the control unit cannot be implemented by the
simple organization.
• This is the situation that arises when the control unit is required to check the
status of the condition codes or external inputs to choose between alternative
courses of action.
• In the case of hardwired control, this situation is handled by including an
appropriate logic function, in the encoder circuitry.
• In micro programmed control, an alternative approach is to use conditional
branch microinstructions.
• In addition to the branch address, these microinstructions specify which of the
external inputs, condition codes, or, possibly, bits of the instruction register
should be checked as a condition for branching to take place.

Thank you all………..
64

Unit 1 Computer Architecture & Organization.pptx

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