This document discusses minimizing energy consumption for TCP over low-power and lossy networks. It presents a mathematical model to predict the energy used for bulk data transfers over multi-hop networks. The model estimates energy based on bit error rate, maximum retransmissions, number of hops, forward error correction amount, and TCP maximum segment size. The model allows studying the tradeoffs of sending short versus long TCP segments to improve energy efficiency over 6LoWPAN and IEEE 802.15.4 networks.
This MATLAB section of source code covers MATLAB based projects.
Download free source code viz. FIR,IIR,scrambler,interleaver,FFT,convolution,correlation,interpolation,decimation,CRC,impairments,data type conversions and more.
RS encoder,convolutional encoder,viterbi decoder,OFDM,OFDMA,MIMO is also covered.WiMAX,WLAN,LTE source codes are also provided.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This MATLAB section of source code covers MATLAB based projects.
Download free source code viz. FIR,IIR,scrambler,interleaver,FFT,convolution,correlation,interpolation,decimation,CRC,impairments,data type conversions and more.
RS encoder,convolutional encoder,viterbi decoder,OFDM,OFDMA,MIMO is also covered.WiMAX,WLAN,LTE source codes are also provided.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
Design of Adjustable Reconfigurable Wireless Single Core CORDIC based Rake Re...IOSR Journals
In wireless communication system transmitted signals are subjected to multiple reflections,
diffractions and attenuation caused by obstacles such as buildings and hills, etc. At the receiver end, multiple
copies of the transmitted signal are received that arrive at clearly distinguishable time instants and are faded by
signal cancellation. Rake receiver is a technique to combine these so called multi-paths [2] by utilizing multiple
correlation receivers allocated to those delay positions on which the significant energy arrives which achieves a
significant improvement in the SNR of the output signal. This paper shows how the rake, including dispreading
and descrambling could be replaced by a receiver that can be implemented on a CORDIC based hardware
architecture. The performance in conjunction with the computational requirements of the receiver is widely
adjustable which is significantly better than that of the conventional rake receiver
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
50 billion connected wireless devices... IPv6, anyone?: Fredrik Garneij, Syst...IPv6no
50 billion connected wireless devices... IPv6, anyone?: Fredrik Garneij, Systems Manager, Ericsson
IKT-Norge IPv6 forum IPV6 konferanse 23 & 24 mai 2011
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Mobility, traffic engineering and redundancy using RPLMaxime Denis
Master thesis presentation. Design and implementation of a solution to improve mobility between two physical WSNs using RPL. Based on the 6LBR implementation of the CETIC.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
Design of Adjustable Reconfigurable Wireless Single Core CORDIC based Rake Re...IOSR Journals
In wireless communication system transmitted signals are subjected to multiple reflections,
diffractions and attenuation caused by obstacles such as buildings and hills, etc. At the receiver end, multiple
copies of the transmitted signal are received that arrive at clearly distinguishable time instants and are faded by
signal cancellation. Rake receiver is a technique to combine these so called multi-paths [2] by utilizing multiple
correlation receivers allocated to those delay positions on which the significant energy arrives which achieves a
significant improvement in the SNR of the output signal. This paper shows how the rake, including dispreading
and descrambling could be replaced by a receiver that can be implemented on a CORDIC based hardware
architecture. The performance in conjunction with the computational requirements of the receiver is widely
adjustable which is significantly better than that of the conventional rake receiver
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
50 billion connected wireless devices... IPv6, anyone?: Fredrik Garneij, Syst...IPv6no
50 billion connected wireless devices... IPv6, anyone?: Fredrik Garneij, Systems Manager, Ericsson
IKT-Norge IPv6 forum IPV6 konferanse 23 & 24 mai 2011
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Mobility, traffic engineering and redundancy using RPLMaxime Denis
Master thesis presentation. Design and implementation of a solution to improve mobility between two physical WSNs using RPL. Based on the 6LBR implementation of the CETIC.
El síndrome de Crouzon, también llamado disostosis craneofacial congénita, es una rara enfermedad de origen genético que se caracteriza por malformaciones del cráneo y de la cara. Se transmite de padres a hijos según un patrón de herencia autosómico dominante.
Jamming aware traffic allocation for multiple-path routing using portfolio se...Saad Bare
Multiple-path source routing protocols allow a data source node to distribute the total traffic among available paths. we consider the problem of jamming-aware source routing in which the source node performs traffic allocation based on empirical jamming statistics at individual network nodes. We formulate this traffic allocation as a lossy network flow optimization problem using portfolio selection theory from financial statistics. We show that in multisource networks, this centralized optimization problem can be solved using a distributed algorithm based on decomposition in network utility maximization (NUM). We demonstrate the network's ability to estimate the impact of jamming and incorporate these estimates into the traffic allocation problem. Finally, we simulate the achievable throughput using our proposed traffic allocation method in several scenarios.
These slides are used in the presentation at https://vimeo.com/156386656 .
In that video, Daan Pareit (iMinds / Ghent University) explains how to calculate Wi-Fi throughput ("your Wi-Fi speed") based on the theory for WLAN medium access. It is a good starting point before doing their online lab which uses live actual Wi-Fi hardware remotely and which is explained at https://vimeo.com/152678614. That online lab itself is accessible at forge.test.iminds.be/wlan .
More information about the FORGE project which enabled the succeeding lab session: at ict-forge.eu .
Advanced TCP/IP-based Industrial Networking for Engineers & TechniciansLiving Online
This manual is for engineers and technicians who need a practical and extensive knowledge of the design and troubleshooting of Industrial Ethernet networks, as well as the selection, installation, and configuration of components such as routers and switches.
It deals in-depth with the underlying TCP/IP protocols, and specifically addresses both design and configuration issues related to IPv4 and the more recent IPv6.
It also covers the more advanced aspects and applications of Ethernet such as advanced switching and routing, CCTV over IP, OPC and Modbus/TCP over Ethernet, industrial security, intrinsically safe applications, switched rings (included the latest IEC 62439-3 redundant ring standard), and highly-deterministic Ethernet-based field buses (e.g. for servo control) capable of 1 millisecond repetition rates and jitter of less than 1 microsecond.
http://www.idc-online.com/content/advanced-tcpip-based-industrial-networking-engineers-and-technicians-21
The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgradesthemperek
Novel pixel readout system-on-chip (SoC) has been designed to meet the ever increasing demands of the present and future generation of LHC pixel detectors. The FE-I4 architecture has higher luminosity and rate capability as well as a smaller single pixel area compared to its predecessors and is currently the most complex chip designed for particle physics applications. The IC has been designed in 130nm CMOS technology. The state of the art of the FE-I4 will be presented, including the architecture overview, simulation results, preliminary measurements and a global design flow.
Improving Performance of TCP in Wireless Environment using TCP-PIDES Editor
Improving the performance of the transmission
control protocol (TCP) in wireless environment has been an
active research area. Main reason behind performance
degradation of TCP is not having ability to detect actual reason
of packet losses in wireless environment. In this paper, we are
providing a simulation results for TCP-P (TCP-Performance).
TCP-P is intelligent protocol in wireless environment which
is able to distinguish actual reasons for packet losses and
applies an appropriate solution to packet loss.
TCP-P deals with main three issues, Congestion in
network, Disconnection in network and random packet losses.
TCP-P consists of Congestion avoidance algorithm and
Disconnection detection algorithm with some changes in TCP
header part. If congestion is occurring in network then
congestion avoidance algorithm is applied. In congestion
avoidance algorithm, TCP-P calculates number of sending
packets and receiving acknowledgements and accordingly set
a sending buffer value, so that it can prevent system from
happening congestion. In disconnection detection algorithm,
TCP-P senses medium continuously to detect a happening
disconnection in network. TCP-P modifies header of TCP
packet so that loss packet can itself notify sender that it is
lost.This paper describes the design of TCP-P, and presents
results from experiments using the NS-2 network simulator.
Results from simulations show that TCP-P is 4% more
efficient than TCP-Tahoe, 5% more efficient than TCP-Vegas,
7% more efficient than TCP-Sack and equally efficient in
performance as of TCP-Reno and TCP-New Reno. But we can
say TCP-P is more efficient than TCP-Reno and TCP-New
Reno since it is able to solve more issues of TCP in wireless
environment.
Similar to TCP over low-power and lossy networks: tuning the segment size to minimize energy consumption (20)
Improving Performance of TCP in Wireless Environment using TCP-P
TCP over low-power and lossy networks: tuning the segment size to minimize energy consumption
1. TCP over low-power and lossy networks: tuning the
segment size to minimize energy consumption
Ahmed Ayadi, Patrick Maill´, David Ros
e
IT/TELECOM Bretagne
Rennes, France
8-9 February 2011
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 1 / 22
2. Motivation
The IETF Working Group 6LoWPAN has recently introduced an adaptation
layer that provides header compression and fragmentation/reassembly
mechanisms to allow sending/receiving IPv6 packets over LLNs (e.g., IEEE
802.15.4),
The 6LoWPANs have given more chance for TCP to be deployed in the
Low-power and Lossy Networks such as Wireless Sensor Networks.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 2 / 22
3. Motivation
The IETF Working Group 6LoWPAN has recently introduced an adaptation
layer that provides header compression and fragmentation/reassembly
mechanisms to allow sending/receiving IPv6 packets over LLNs (e.g., IEEE
802.15.4),
The 6LoWPANs have given more chance for TCP to be deployed in the
Low-power and Lossy Networks such as Wireless Sensor Networks.
However, the IPv6 MTU is 1280 bytes while an 802.15.4 frame can have a
payload limited to 74 bytes,
A TCP segment might end up fragmented into as many as 18 fragments at
the 6LoWPAN layer,
If a single one of those fragments is lost in transmission, all fragments must
be resent,
Sending long TCP segments increases the packet error rate, while sending
short TCP segments increases the overhead.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 2 / 22
4. Outline
1 Introduction
2 TCP energy consumption model
TCP energy consumption model: Notations
Link layer: one-hop model
Multi-hop model
TCP Model
3 Results and discussion
Model assessment
FEC redundancy ratio and energy consumption
Selecting the TCP MSS to minimize energy consumption
4 Conclusion and perspectives
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 3 / 22
5. Introduction
Focus on the energy cost when TCP is used in multi-hops LLNs.
Present a simple mathematical model aimed at predicting the energy
consumed by the wireless nodes of an LLN in a bulk-data transfer scenario.
The model estimates TCP energy performance based on the bit error rate,
the maximum number of retransmissions at link layer, the number of hops
between the sender and the receiver, the amount of FEC, and the TCP
maximum segment size.
The proposed model allows us to study the tradeoffs involved in sending
short versus long TCP segments.
Applying the model, we study the energy efficiency of TCP over an LLN
using 6LoWPAN and IEEE 802.15.4 protocols.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 4 / 22
6. Notations
We assume that the energy consumed by a TCP transmission in a wireless
LLN mainly corresponds to the data emission and reception, and thus
directly depends on the number of bits sent by all nodes.
The following table lists most of the variables used in the model.
Variable Definition
D Link-layer data frame size
A Link-layer acknowledgement frame size
h Number of hops between source and destination
r Maximum number of link-layer transmission attempts
m Number of fragments corresponding to a single TCP segment (due
to link layer fragmentation)
α FEC redundancy ratio
B Bit error rate
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 5 / 22
7. Link Layer Modeling
Automatic Repeat reQuest (ARQ)
ARQ uses the cyclic redundancy check (CRC) error-detecting code that
is added to the data: the receiver uses the error-detecting code number
to check the integrity of the received data
After receiving a correct frame, the receiver replies by an ACK.
If the sender does not receive an ACK before the timeout, it
re-transmits the frame/packet until the sender receives an
acknowledgment or exceeds a predefined number of re-transmissions.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 6 / 22
8. Link Layer Modeling
Automatic Repeat reQuest (ARQ)
ARQ uses the cyclic redundancy check (CRC) error-detecting code that
is added to the data: the receiver uses the error-detecting code number
to check the integrity of the received data
After receiving a correct frame, the receiver replies by an ACK.
If the sender does not receive an ACK before the timeout, it
re-transmits the frame/packet until the sender receives an
acknowledgment or exceeds a predefined number of re-transmissions.
Forward Error Correction (FEC)
The main idea of FEC is to add redundancy to the original frame, to
allow the destination node to detect and correct some bit errors.
The FEC algorithm adds (α × K) redundancy bits to form a frame of
length D.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 6 / 22
9. Link Layer Modeling
ACKs are sent without FEC.
Sender Receiver Sender Receiver Sender Receiver
Data frame Data Data
. frame frame
Ack frame e
. Ack fram
(a) Failure. (b) Partial failure. (c) Success.
c
D
Pfail = 1 − B i (1 − B)D−i ,
i
i=0
Ppartial = (1 − Pfail )(1 − (1 − B)A )
Psucc = (1 − Pfail )(1 − B)A
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 7 / 22
10. Link Layer Modeling
F i : Probability that a destination node does not receive a link layer data frame
after r attempts (i th hop)
r
F = Pfail .
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 8 / 22
11. Link Layer Modeling
F i : Probability that a destination node does not receive a link layer data frame
after r attempts (i th hop)
r
F = Pfail .
Hf : Expected number of bits sent after r attempts knowing that the (one-hop)
transmission has failed
Hf = r × D.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 8 / 22
12. Link Layer Modeling
F i : Probability that a destination node does not receive a link layer data frame
after r attempts (i th hop)
r
F = Pfail .
Hf : Expected number of bits sent after r attempts knowing that the (one-hop)
transmission has failed
Hf = r × D.
Hs : Expected number of bits sent within r attempts knowing that the
(one-hop) transmission has succeeded
r
1 r i r −i
Hs = ( Ppartial Pfail (r D + iA)
1 − F i=1 i
r k−1
k −1 i k−1−i
+ Psucc Ppartial Pfail (kD + (i + 1)A))
i
k=1 i=0
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 8 / 22
13. Multi-hop model
Sender Receiver Sender Receiver
. .
.
.
(d) End-to-end failure scenario: the (e) End-to-end success scenario:
frame cannot be forwarded after r the frame arrives at the destination.
unsuccessful retransmissions. This scenario may also include par-
tial failures over one or more hops
(not depicted).
Figure: Failure and success scenarios in a multi-hop transmission.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 9 / 22
14. Multi-hop model
Q s : Probability of an end-to-end packet transmission success
h
Qs = (1 − F i )
i=1
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 10 / 22
15. Multi-hop model
Q s : Probability of an end-to-end packet transmission success
h
Qs = (1 − F i )
i=1
Es : Expected number of bits sent for a successful end-to-end packet transmission
knowing that it has succeeded
h
Es = Hsi
i=1
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 10 / 22
16. Multi-hop model
Q s : Probability of an end-to-end packet transmission success
h
Qs = (1 − F i )
i=1
Es : Expected number of bits sent for a successful end-to-end packet transmission
knowing that it has succeeded
h
Es = Hsi
i=1
Ef : Expected number of bits sent for an end-to-end packet transmission knowing
that it has failed
h k−1 k−1
k=1 ( i=1 Hsi + Hfk ) j=1 (1 − F j )F k
Ef = h
1− i=1 (1 − Fi)
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 10 / 22
17. TCP Model
Ps : The success probability of a TCP segment transmission attempt is simply the
probability that all m data fragments be correctly sent to the destination, and the
TCP ACK be successfully sent back to the source:
Ps = Q m × Q s,ack ,
s
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 11 / 22
18. TCP Model
Ps : The success probability of a TCP segment transmission attempt is simply the
probability that all m data fragments be correctly sent to the destination, and the
TCP ACK be successfully sent back to the source:
Ps = Q m × Q s,ack ,
s
Knowing that a transmission is successful at the TCP level (i.e., the TCP ACK is
correctly received by the TCP source, which implies that all m fragments correctly
reached the destination), the expected total number of bits sent by all nodes
equals:
Ss = Es × m + Es,ack
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 11 / 22
19. TCP Model
Knowing that a TCP transmission attempt has failed, the expected number of
bits sent end-to-end by all nodes is:
1
Sf = If (1 − Q m )
s + (Es × m + Ef ,ack )Q m (1 − Q s,ack )
s ,
1 − Ps
end-to-end transmission failure end-to-end transmission failure of the TCP ACK
of one or more of the m fragments
m
m
If = kEf +(m−k)Es (1−Q s )k (Q s )m−k = m(1−Q s )Ef +mEs Q s (1−Q m ).
s
k
k=1
This therefore corresponds to a total number of bits sent (per segment) of
S = Sf (1/Ps − 1) + Ss .
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 12 / 22
20. Scenario & Parameters
TCP Sender n-1 n n+1 TCP Receiver
Figure: Chain Topology
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 13 / 22
21. Scenario & Parameters
TCP Sender n-1 n n+1 TCP Receiver
Figure: Chain Topology
Parameter Value
h 5
r 3
α 0
BER B 3 × 10−4
Link-layer Ack frame size 40 bits
Link-layer data frame header 120 bits
IP header 160 bits
TCP header 160 bits
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 13 / 22
22. Model assessment (1/2)
103
MSS = 512 (model)
MSS = 512 (simulation)
MSS = 64 (model)
Consumed energy (J) MSS = 64 (simulation)
102
101
10−6 10−5 10−4 10−3
BER
Figure: Energy consumption with long or short TCP segments, as a function of
the BER B.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 14 / 22
23. Model assessment (2/2)
102
MSS = 512 (simulation)
MSS = 512 (model)
MSS = 64 (simulation)
Consumed energy (J)
MSS = 64 (model)
101
2 3 4 5 6 7
Maximum link layer attempts
Figure: Energy consumption with short or long TCP segments, as a function of
the number of link layer attempts r (with B = 5 × 10−4 ).
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 15 / 22
24. FEC redundancy ratio and energy consumption (1/2)
103
MSS = 512, r =1
MSS = 512, r =3
MSS = 64, r =1
Consumed energy (J)
MSS = 64, r =3
102
101
100 −3
10 10−2 10−1 100
Redundancy ratio (α)
Figure: Consumed energy using short or long TCP segment, as a function of the
redundancy ratio α (B = 3 × 10−4 , h = 5).
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 16 / 22
25. FEC redundancy ratio and energy consumption (2/2)
103
MSS = 512, B = 10−3
MSS = 512, B = 10−4
MSS = 64, B = 10−3
Consumed energy (J) 102 MSS = 64, B = 10−4
101
100
10−2 10−1 100
Redundancy ratio (α)
Figure: Consumed energy using short or long TCP segment, as a function of the
redundancy ratio α (r = 1, h = 5).
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 17 / 22
26. Selecting the TCP MSS to minimize energy consumption
102
MSS = 512, B = 4 × 10−4
MSS = 64, B = 4 × 10−4
Consumed energy (J)
101
100
2 4 6 8 10
Number of Hops (h)
Figure: Energy consumption for short and long TCP segment sizes, as a function
of the network size (r = 3).
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 18 / 22
27. Selecting the TCP MSS to minimize energy consumption
Depending on the transmission distance and the BER. We remark that for a given
BER, short MSSs tend to outperform long MSSs when the distance grows: it is
more and more interesting to use short MSS values instead of long ones.
10−1
MSS=64
MSS=512
−2
10
BER
10−3
10−4
10−5
2 4 6 8
Number of Hops (h)
Figure: Long (MSS=512 bytes) versus short (MSS=64 bytes) in a multi-hop
transmission (r = 3).
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 19 / 22
28. The impact of ARQ max attempts
10−3 r =7
r =5
r =4
r =3
BER
r =2
10−4
r =1
10−5
2 4 6 8
Number of Hops (h)
Figure: Long (MSS=512 bytes) versus short (MSS=64 bytes) in a multi-hop TCP
transmission: prefer the short MSS above the curves, the long one below.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 20 / 22
29. The effect of FEC mechanisms
Not surprisingly (the FEC reducing the effect of transmission errors), redundancy
makes large MSSs outperform small MSSs due to the overhead reduction they
allow.
10−1
α = 10−1
10−2
α = 10−2
BER
−3
10
α = 10−3
10−4
10−5
2 4 6 8
Number of Hops (h)
Figure: Long (MSS=512 bytes) versus short (MSS=64 bytes) in a multi-hop TCP
transmission: prefer the short MSS above the curves, the long one below.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 21 / 22
30. Conclusion and perspectives
Conclusion
We have proposed an analytical model to estimate the number of bits
sent by all wireless nodes in a TCP session in a Low power and Lossy
Network, in order to evaluate the overall energy consumption,
We have shown that using a large TCP segment size is less
energy-consuming in small, low-error networks, while it becomes
interesting to reduce the MSS when the network is large or very lossy,
Perspectives
A first interesting direction would be to model the collision process,
that has been observed in our simulations for large MSS values,
We would also like to consider the case when duplicate frames are not
detected at the link layer; likewise, the transport layer modeling could
be extended to encompass TCP’s delayed acknowledgement
mechanism, and also larger TCP windows,
We are currently investigating an adaptation algorithm which
dynamically adjusts the TCP segment size to the optimal MSS value.
Ahmed Ayadi (IT/TELECOM Bretagne) NTMS Wireless Sensor Networks 2011 Paris, 8-9 February 2011 22 / 22