This document provides an overview of using Xilinx ISE to synthesize a VHDL design unit. It begins with copyright information and objectives. It then outlines the basic synthesis flow, including creating a new project, setting project options, importing files, running synthesis, viewing the RTL schematic, and reviewing the synthesis report. The document provides step-by-step instructions on performing each step of the synthesis flow and analyzing results.

1. VHDL 360©by: Amr Ali

2. CopyrightsCopyright © 2010/2011 to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2

3. ObjectiveUsing Xilinx ISE* to Synthesize a given design unitSkills gained:Identify basic Synthesis flowVHDL 360 ©3*All snapshots were taken using Xilinx version 11.4…They might vary based on the version you use. Please refer to www.xilinx.com for more info. Xilinx ISE is a registered trademark of Xilinx Corporation

4. OutlineNew ProjectProject SettingsImport FilesSynthesizeView RTL SchematicSynthesis ReportVHDL 360 ©4

5. New ProjectOpen ISEFile  "New Project"Specify project's name and location on diskVHDL 360 ©5

6. Project SettingsChoose the target devicepress next  next  next  finishVHDL 360 ©6

7. Import Files to ISERMB on the project node  Add copy of SourceBrowse the design files location on disk  select your files and press OKRMB on the design unit you want to synthesize and choose "Set as Top"VHDL 360 ©7

8. Synthesize Design UnitSelect the design unit you want to synthesizedouble click on "Synthesize – XST" nodeVHDL 360 ©8

9. View RTLAfter synthesis finishes double click on "View RTL Schematic" nodeChoose "Start with a schematic" option and press OKVHDL 360 ©9

10. View RTLDouble click on the top level diagram to see the RTLExplore the RTL netlist by hovering the mouse and double clicking on different blocksVHDL 360 ©10

11. Synthesis ReportSwitch to "Design Summary" tab and select the "Synthesis Report" nodeThe Synthesis report is divided into sections includingArea utilized by the designEstimate of the maximum operating frequencyVHDL 360 ©11

12. Synthesis ReportThe "Synthesis Options Summary" section lists all the synthesis options used in this synthesis runTo change synthesis options; RMB on the "Synthesis-XST" node  "Process Properties"VHDL 360 ©12

13. ContactsYou can contact us at:http://www.embedded-tips.blogspot.com/VHDL 360 ©13