This document provides an overview of using ModelSim to simulate VHDL designs. It discusses compiling and simulating designs from the command line as well as interactively within ModelSim. Key steps covered include compiling VHDL files with vcom, simulating with vsim, adding signals to the waveform window, applying inputs, running simulations, generating makefiles, and creating and simulating designs within the ModelSim GUI. The document aims to teach basic ModelSim simulation commands and workflow.