2. 2
Scope (1)
● Demonstrates LE1200 analog tester features
showcased in testing an analog subtractor
circuit.
● Test pattern oriented analog test programming.
It can be easily integrated with that of digital
test and boundary scan test.
● Incremental analog test methodology - prior
DUT analog input voltage driven by the analog
tester won't be changed until the next overriding
test instruction to the same input.
3. 3
Scope (2)
● Validating DUT analog output voltage by
comparing to the test program specified range
of expected voltage levels.
● Incorporating test interface circuits to handle
out-of-range DUT output voltage levels.
● Analog tester logging files reporting DUT input
driving voltage, measured DUT output voltage,
and the output voltage test results.
● Fault insertion test demonstrating analog tester
capability for the go/no-go test.
5. 5
Test Setup (1)
● As shown in page 4, analog tester pins: ain5
and ain6, are connected to the DUT input nodes
v1 and v2 respectively. Another analog tester
pin, aout7, is used to measure DUT output v3.
● On Test interface circuit, a voltage inverter will
be used in case that DUT output voltage v3
turns negative. In that, analog tester pin aout8
will be used to measure v4 inverted from v3.
● Reed relay switches, sw1 & sw2, are devised to
turn on/off the nodes, v3 & v4, to/from analog
tester measurement.
6. 6
Test Setup (2)
● Digital Tester pins: 231 & 232 will be used,
under test program control, to toggle Reed
relays sw1 and sw2.
● With analog circuit node names and their
voltage levels used interchangeably, following
equations hold.
v3 = v2 – v1
v4 = -v3 (sw2 turned on)
7. 7
Assigning tester pins: Pindef (1)
● P.9 is the snippet of the LE1200 tester pins
defined for use in this analog subtractor test.
● Digital tester pins 231 & 232 are designated as
input ports (to drive DUT). d231 and d232 are
user defined signal name for test programming.
● Analog tester pins ain5 & ain6 are driving DC
voltages into DUT while analog tester pins
aout7 & aout8 are used to measure DUT output
voltages. The in/out designations are referred
from DUT standpoint.
8. 8
Assigning tester pins: Pindef (2)
● In pindef spreadsheet, aout8 tester pin has an
entry: -1 in its column C. That designates
measured DUT output (v3) voltage level has
passed through a voltage inverter. LE1200 will
take that into account in determining the test
result.
● Other analog tester pins, with their column C
fields left blank, are indications of direct
connection between tester pins and the DUT.
10. 10
Test operations (1)
● Sweeping voltage levels in the 2 DUT input pins
to be verified by the 2 analog tester pins: aout7
& aout8.
● Overall test is divided into 2 groups, one with
positive Subtractor output voltage (v3), and
other with negative Subtractor output voltage.
● Only one of the two reed relay switches will be
turned on during the test. That will prevent the
aliasing errors with the A/D converters built in
the analog tester.
11. 11
Test operations (2)
● Sysout trace file listed on P.13 shows the
running test instruction source lines along with
the associated source file line numbers and test
pattern numbers.
● e.g. source file line number 12, test pattern #3,
analog tester pin ain6 will drive 0.2v toward
DUT node v2.
● In the next test pattern, aout7, is instructed to
measure DUT node v3 voltage, and validate if it
falls within the range between 0.19v and 0.21v.
12. 12
Test operations (3)
● With rising ain6 driving voltage, tester is
expected to measure the same upswing in the
aout7 voltage.
● In pattern #16, digital tester pins are instructed
to turn off sw1 and turn on sw2.
● In the follow on test patterns, DUT node v3 will
have negative voltage and thus not testable by
aout7. However, tester pin aout8 should be
able to measure inverted v3.
13. 13
Sysout Trace Files
( 9-00001) sel = 1;
( 11-00002) force ain5 0;
( 12-00003) force ain6 0.2;
( 13-00004) measure aout7 0.19 0.21;
( 15-00005) force ain6 0.6;
( 16-00006) measure aout7 0.59 0.61;
( 18-00007) force ain6 1.2;
( 19-00008) measure aout7 1.19 1.21;
( 21-00009) force ain6 1.8;
( 22-00010) measure aout7 1.79 1.81;
( 24-00011) force ain5 0.6;
( 25-00012) measure aout7 1.19 1.21;
( 27-00013) sel = 0;
( 29-00014) force ain5 0.2;
( 30-00015) force ain6 0;
( 31-00016) sel = 2;
( 33-00017) measure aout8 -0.21 -0.19 ;
( 35-00018) force ain5 0.6;
( 36-00019) measure aout8 -0.61 -0.59 ;
( 38-00020) force ain5 1.2;
( 39-00021) measure aout8 -1.21 -1.19 ;
( 41-00022) force ain5 1.8;
( 42-00023) measure aout8 -1.81 -1.79 ;
( 44-00024) force ain6 0.6;
( 45-00025) measure aout8 -1.21 -1.19 ;
15. 15
Fault Insertion Test (1)
● As shown in P.16, DUT OpAmp pin 3 is
connected to GND and same test sequence is
repeated.
● Some DUT output measurements failed. In test
patterns 17, 19, 21, and 23, tester input ain6 is
0v, no failed condition can be detected.
● In test pattern 13, as shown in P.18 CSV file,
the reported voltage is 0.000v instead of the
actual -0.6v probed. That is due to tester AD
converter's lowest input voltage limitation.
