Assignment 1 Description Marks out of Wtg() Due date .docx

Assignment 1
Description Marks out of Wtg(%) Due date
Assignment 1 200 20 28 August 2015
Part A: Comparators and Switching (5%)
(1) Signal limit detector
Use a 339 comparator, a single 74LS02 quad NOR gate and a
+5V power supply only to
design a circuit which will detect when a voltage goes outside
the range +2.5V to +3.5V
and such that an LED lights and stays lit. Provide a manual
reset to extinguish the LED.
Design hints
1. The circuit has an analog input and a digital output so some
form of comparator circuit
is required. There are two thresholds so two comparators are
required, with the analog
input applied to both. This arrangement is sometimes known as
a window detector.

2. Arrange the output of the comparators to be +5V logic
levels, and combine the two
outputs logically to produce one signal which is for example,
high for out-of-range, and
low for within-range.
3. Latch the change from in-range to out-of-range.
Design procedure
1. Start at the output and work backwards.
2. Select a latch circuit (flip-flop) and determine what
combinations of inputs are needed to
latch and then reset it, ensuring that the LED is connected
correctly with regard to both
logic and current flow.
3. Determine the logic needed to combine two comparator
outputs in such a way as to
correctly operate the latch.
4. Choose comparator outputs which will correctly drive the
logic. Remember that the
reference voltage at the input of the comparator may be at either
the + or – input.
5. Choose resistors to provide the correct reference voltages.

Note: You will need to consult data for both the 74LS02 and the
339 (see data sheets).
Test
It is strongly recommended that you assemble and test your
circuit.
(2) MOSFET Switching
Find out information on the operation of, and configuring of,
MOSFETs to be used in
switching circuits. In particular note the differences between
BJTs and MOSFETs in this
role. Draw up a table to highlight the differences and hence the
pros and cons on each
device for particular situations (eg. Switching high-to-low or
low-to-high (ie. P or N type),
high or low current switching, low or high voltage switching).
Consider the following BJT switching circuit. Analyse the
operation of the circuit to
understand the parameters involved. Choose suitable
replacement MOSFETs to be used
ELE2504 – Electronic design and analysis 2
instead of the output switching BJTs in the given circuit.
Include any necessary circuit
changes for the new devices to operate so as to maintain the
circuit’s required parameters.

Where Vcc = 12V and Relay resistance = 15Ω .

Part B: Transistor amplifier design (6%)
Design and test a common emitter amplifier using the circuit
shown and the selected
specifications.
Specifications
Get your own specifications provided on the StudyDesk
Bandwidth > 100Hz → 20kHz
Design
(Example follows)
1. Allow about half VCC across the transistor;
VCE = 0.5 VCC
2. So the voltage across RC and RE is VCC – VCE
IC (RE + RC) = VCC – VCE
3. Since the voltage gain will be very close to RC / RE,

RC / RE = AV
Hence RC and RE can be determined, choosing appropriate
preferred values.
E
4. Determine:
VE = ICRE and hence
VB = VE + VBE
5. Choose R1 and R2. The maximum value of base current is:
IB (max) = IC / hfe (min)
Now let the current in R1 and R2 (IDIV) be about 5 to 10 times
IB, so
IDIV = VCC / (R1 + R2) = say 10 IB (max)

(1)
and since IB can now be neglected relative to IDIV,
VB = R2 / (R1 + R2) × VCC
(2)
Hence R1 and R2 can be chosen using the nearest preferred
values.
6. Check the design using the nominal preferred values to
ensure that VCE ≈ 0.5VCC. If not,
modify R1 and R2 slightly, remembering that their ratio is
important (equation (2) above)
but their absolute magnitude is not (equation (1) above).
Example
1. VCE = 0.5 VCC
= 5v

2. IC (RE + RC) = VCC – VCE
2.5 × 10–3 (R + RC ) = 5
3. RC / RE = Av
= 7
So RE + RC = 2k
RC / RE = 7
∴ RE = 250 → 270Ω
RC = 1750 → say 1800Ω
4. VE = IC RE
= 2.5 × 10–3 × 270
= 0.68v
VB = VE + 0.7
≈ 1.4v

5. IB (max) = IC / hfe (min)
= 2.5 × 103/130
= 19.2µA
IDIV = say 10 × IB
= 192µA
R1 + R2 = VCC / IDIV
= 10/192µA
= 52kΩ
VB = R2 / (R1 + R2) ×
VCC
R2 / (R1 + R2) = 1.4 / 10 = 0.14
or the voltage across R2 = 1.4v, and
the voltage across R1 = 8.6v.
∴ R2 = 0.14 × 52k
= 7.3kΩ say 6.8kΩ (reducing ≈ 7%)
and R1 = 0.86 + 52k
= 44.7kΩ, say 39kΩ (reducing ≈ 12.8%)
6. Check:
VB = 6.8k / (39k +
6.8k) × 10v
= 1.5v
VE = 0.8v
IC = 0.8270
= 3.0mA
VC = 10 – 3.0 × 1.8k

= 4.6v
∴ VCE = 4.6 – 0.8
= 3.68v
This is significantly less than 5v but could be acceptable. If not,
select another R1 and R2
by trial and error. Try 8.2k and 56k which gives VB = 1.3v
which is about as far off in the
opposite direction. This may be satisfactory if the amplifier is
not required to handle
large signals. If not satisfactory, repeat until some satisfactory
values are found.
Simulation
Use the circuit simulation programme MICROCAP (or similar)
to analyse your design:
(Help is given on the following page.)
1. Determine the d.c. voltages at all points. This will check
your design – if these are

correct, the circuit should amplify an a.c. signal. Check choice
of C1 for specification.
2. Determine the frequency response (voltage gain and phase
versus frequency) over the
range 1Hz to 1MHz.
3. Bypass RE with a capacitance of 0.47 µF and again
determine the frequency response
over the same frequency range.
For example:
MICROCAP analysis of the example circuit above using
transistor Q1, gives the frequency
response graph on the following page, using the analysis limits
on the page after that.
Help using MICROCAP
The following may help to get the required results using
MICROCAP:
● draw the circuit
● select VIEW, show node numbers and note the node numbers
of the input before the

capacitor, and the output (collector)
● select RUN, Transient Analysis and set the Analysis Limits
● select AC Run and the result will be a frequency response
graph.
Transient response – (time base)
Sample Analysis setup ...
Note that the node numbers in the ‘Y expression’ pertain to the
nodes on the schematic
shown overleaf. Your numbers for these nodes may be different.
Transient Analysis plots of input and output ...

Note use of scope cursors to determine peak-to-peak voltage of
output.
Circuit schematic showing node voltages (quiescent) post
analysis ....
Note that the Transient Analysis plot and node voltages show
whether biasing is
correct/optimal.
Frequency responses – (Bode plot)
Sample setup for AC Analysis ...
Sample plot of AC Analysis
Note use of scope cursors to determine the –3dB break point at
approximately 22 Hz.

Test (Optional)
Note that the measurements taken here are not expected to be
accurate since it is assumed
they will be done with a digital voltmeter only, and waveforms
may not be sinusoidal. In
building the circuit you may use a BC547 in place of the
2N22222.
1. Connect your circuit and measure the d.c. voltages around
the circuit. If they are not as
expected, find the cause and rectify it.
2. Connect the test oscillator (shown below) to the input. It
should be producing an
approximately sinusoidal signal of about 100kHz frequency and
you can add an attenuator
to produce a small size of say 0.2v p/p. Measure, using a DVM,
the magnitude of the
voltage gain at 100kHz.
3. Bypass RE with a capacitance of 0.47μF and again measure

the voltage gain. You will
need to reduce the size of the signal input in order to keep the
output sinusoidal. Reduce
it to an estimated 20mV.
4. Remove the bypass capacitor. Estimate the input resistance
(at 100kHz) by adding a 1kW
resistor (R) in series with the oscillator to monitor base a.c.
current. Measure the a.c.
voltage across this resistor, v. The input current is then iin =
v/R, and the input resistance
Rin of the amplifier is Rin = Vin/iin – R.
5. Repeat 3 and 4 with the 0.47μF capacitor bypassing RE.
Note:
If using 4093, parallel all 6 gates to
provide maximum output current
capability.
Test oscillator to act as a source for the amplifier.
Report
● Show all design calculations.

● Show full cct design with all component values.
● Provide either –
o MCap plots for AC analysis, transient analysis and schematic
showing node voltages
and/or
o Test results from testing built circuit.
● Comparison of results (measured or simulated) with
specifications, drawing inferences and
conclusions.
Part C: Voltage controlled oscillator design (5%)
Circuit
The circuit given below generates a rectangular wave and a
triangular wave whose frequency
is determined by a voltage applied to the input.

Circuit operation
Assume the transistor is off, i.e. Vo2 is LOW. Vo1 ramps
downwards due to the integrator R3C.
Meanwhile, since V+2 is a positive voltage, when Vo1 passes
V+2, Vo2 changes to HIGH, the
transistor turns on and C discharges via R4 and the transistor.
Hence Vo1 ramps up and the
cycle repeats.
Design task
Design a VCO (voltage controlled oscillator) using an LM324
quad op. amp.or
LM741 op. amp.s with the specifications provided uniquely to
each student on StudyDesk
(refer to the data sheets):
Example Design specification
VDD 9V
Vin range 2V to 6V
Frequency range 100Hz – 300Hz
Duty cycle D:1 (high to low) 3:1
Vo1 range 2 to 7V

A full analysis of the circuit operation and a design example
follow.
1
1
2
2
Test
Assemble your design and check that it works. An LM324
(single supply) op. amp. and any
small transistor should work. You will also need to provide
VDD / 2 with a voltage divider of
two 1k ohm resistors or similar.
If you have access to equipment, measure the performance of
your circuit in regard to each of
the design specifications.
Analysis

Op. amp. A1 operates an integrator with an input voltage Vin /
2 set by the voltage divider
R1 and R2. When TR1 is off, A1 integrates by charging C via
R3 (pushing current into the left
hand side of C for positive Vin). When TR1 is on, C discharges
to ground via R4.
By the principle that for an active op. amp., V+ = V–, and since
V+ is held at Vin / 2:
a. When TR1 is off, current into C, = I1:
/ 2
R3
2R3
and hence Vo1 ramps downwards at a rate of:
2R3C
b. When TR1 is on, current out of C via:

2R4
but in this case since V– is still at Vin / 2, current is still also
charging C via R3. So we
have:
2R4
So the net current outflow from C is I2 – I1.
Now A2 acts as a comparator and its output switches TR1 when
Vo1 reaches some fraction
(say β) of Vo2 which can be assumed to switch between zero
and VDD.

R5
VDD
2
2
2
2
and these two voltages are the thresholds at which Vo1 causes
switching.
The voltage Vo1 thus ramps up and down at different rates as
shown:

So in order to achieve a duty cycle of D:1,
D
2R4
R
2R3
2
Timing

2R3C 2
V
Hence
2 2R3C 2
V
2R C
2
Vin
Vin
Vin
Vin

Vin
Design example
Choose R5 and R6
Vo1 range is 2 to 7V
2
2
Choose resistors to be as large as possible consistent with the
assumption that the current
into V2+ is negligible, say:
R5 = 100k Ω
R6 = 82k Ω

Frequency
Choose R3 and C as a pair by trial and error until practical
values of both are found.
Vin (min)

Say
So
Transistor
Maximum current in transistor
R4
8.3

Note this resistor is impractically large. So allow more base
overdrive and choose
R7 = 1 MΩ.
(The 33pF capacitor is to aid switching speed.)
Report
● Show all design calculations
● Show full circuit diagram with all component values
● Results from testing or simulation
● Comparison of results with specifications with observations
and conclusions.
Part D: Semiconductor devices (4%)
Select two devices and submit a short report for each, covering

the following details:
● what the device is (name, type)
● explanation of the devices’ features and how it works
● sample circuit application making use of its feature(s) with a
circuit operation
explanation (include any relevant calculations).
Device list:
2N4871
QED223
BPV11
1N6276CA (or 1.5KEI6CA)
BTV58-1000
BUK854-500
V33ZA7 (GE-MOV)
BD333

Design assignment A
Design assignment A 0 0 Week 5
This assignment does not have to be submitted for marking.
However it may be the subject of
a question in the examination.
Part A: Logic design
(1) Astable

Use a single 4528 dual monostable to construct an astable
circuit with a mark-space ratio of
0.5 and times of the order of 1 to 2 seconds. Put indicating
LEDs on the circuit to indicate
both times.
Design hints
1. The final transition of the times pulse from one monostable
may be used to trigger the
other monostable, producing waveforms as shown:
2. Mark-space means high time to low time.
3. You will need to look up the data for the I.C. you are using
since details of timing
relationships are different for each (see data sheets).
Test
Assemble the circuit and check that your design works.
Design a logic interface circuit to allow the connection of data
from either of the two specific
logic gates shown (one TTL and one CMOS), to either of two
other specific logic gates (TTL
and CMOS) as shown in the sketch.

(2) Logic Design & Family Compatibility
Specifications
1. Five volt power supplies are used on both source and
destination circuits.
2. The signal must not be inverted in passing through the
interface. (It may of course be
inverted within the interface, but must emerge the same as it
went in.)
3. The interface is to contain an LED (with current between
5mA and 10mA) to indicate the
state of the data (at point X), as well as any extra gates (of any
type) needed to provide the
interface function. (Use gates only, not transistors.)
4. The interface must be properly designed to ensure that it
takes into account the worst
case specifications of the logic gates involved. D.C. design only
is required.
Steps

1. Assemble the relevant worst case data on all gates and
organise in a table of the
following form, using data @ 25°C.
Gate VOH IOH VOL IOL VIH IIH VIL IIL
74HC00 – – – –
74S02 – – – –
4001 – – – –
74LS00 – – – –
2. Design the circuit by carefully considering each possible
position of the switches, both
voltage and current and both high and low states, and choosing
a combination of gates to
form the interface circuit.
Report
Submit a report containing at least the following:

1. Data for the gates in a table as above. (Data sheets at the
end of this book.)
2. For the simple case of the interface being a direct
connection, give clear consideration of
each possible combination of gates and logic levels, and
identification of any problems.
Give reasons.
3. Your solution to the problems, including a sketch of the
interface circuit and justification
of any resistor values.
Note
There is no need to assemble and test the circuit since most
individual I.C.s
will perform better than the worst case figures indicate, and so a
simple test
of operation would prove nothing.

Part B: Differential amplifier exercise
The circuit
Simulation
Use MICROCAP (or similar) to analyse the circuit. Leave out
the voltage divider network
(47k, 10k, 47k) for this.
1. Determine the d.c. voltages at both collectors and at the
common emitter, by grounding
the base of Q1 and running a d.c. analysis.
2. Determine the d.c. response at either collector to a varying
input voltage over the range
–0.3v to +0.3v by adding a 1mV d.c. source as shown above and
running a d.c. analysis.
Use limits as shown on next page.

3. Add a 1μf capacitor to the input and so determine a.c.
voltage gain, Ad (single collector
to ground).
4. Connect the two bases together at the bias network and
determine the a.c. common mode
gain (single collector to ground). Change sine source to 1V.
5. Add the constant current source shown below in place of the
common emitter resistor RE
and again determine the single ended a.c. common mode gain.
(i.e., repeat 4 above).
Notice that it is very frequency dependent, but for frequencies
less than about 1MHz, it
is very much less than it was for the single resistor case. Hence
common mode rejection
ratio is very much improved.
Help using MICROCAP
For determining the d.c. response at the collectors, try these
analysis limits:

Sample plot ....
Test
1. Construct the circuit shown on the previous page.
2. Vary the potentiometer over its entire range and at about
nine evenly spaced intervals
measure the voltage on the base and the voltage at both
collectors.
You will need to take additional points at the cross-over to get a
good representation
of the shape of the curves.
The following values of base voltage are suggested: –0.3, –0.1,

–0.06, –0.03, 0, +0.03,
+0.06, +0.1, +0.3 volts.
3. Calculate the corresponding collector circuits.
4. Plot on the one set of axes, graphs of each collector current
and the sum of the two,
versus input voltage.
Your graph should appear as sketched below.
Report
● Submit MCap schematic (with node numbers) and DC analysis
plot.
● Submit table of results from practical testing with graph.
Part C: Power amplifier design exercise

Design
Design a push-pull amplifier to the circuit arrangement given
and with the following
specifications:
Supply voltages ± 9v
Output power 360mW
Voltage gain > 5
Simulation
Use MICROCAP (or similar) to simulate your design, using any
suitable transistors
(e.g. Q1).
1. Plot d.c. out versus d.c. in on the base of Q3. You should
expect to see a voltage gain >5.
(Note that the base of Q3 is biased at a fairly large negative
voltage, so the input voltage
range will need to be around that value.)
2. Short out the two diodes and repeat the d.c. analysis.
Crossover should be clearly visible.

3. Determine the d.c. bias values at the base, collector and
emitter of Q3 and at the common
emitter of the output stage. If your circuit does not work as
expected, this should point to
the errors.
Design assignment B
Design assignment B 0 0 Week 10
This assignment does not have to be submitted for marking.
However it may be the subject of
a question in the examination.
Part A: Active filter design exercise (Part 1)
Design

Design a 3 pole high pass filter with a Butterworth response
having a cut-off frequency of
160 kHz. The filter is to use the second order circuit
arrangement given below, and first order
section with LM108 or equivalent op. amps.
Theory
From the theoretical pole positions, compute and plot the
following:
● the magnitude and phase of the normalised frequency
response
● the group delay (–dϕ/dω) as a function of frequency.
Note that this will be a normalised plot with a cut-off frequency
of 1 rad/sec.
remember that a 3-pole
1
low pass response is in the
c)
complex poles.

where a, b, c are the
The use of MathCAD or a similar programme makes this simple,
but do it manually if
necessary. Six or eight points on a plot should be enough.
Simulation
Using MICROCAP simulate your circuit and plot gain, phase
and group delay versus
frequency over the range 1 Hz to 10 kHz. This will also tell you
if your design is correct.
Build and test
Using an LM324, build your filter and test it by taking about 7
readings from 20 kHz to 2kHz
using an oscilloscope (if you have access to one) or multimeter.
If you feel your multimeter
cannot take accurate AC voltage measurements at these
frequencies, go to the course website
for an alternative.

Part B: Active filter design exercise (Part 2)
This is entirely optional and no examination questions will be
based on it. It is however a
practical way to design a filter.
Specifications
Design a 4th order low pass filter with a Butterworth response
having a cut-off frequency of
20 kHz, and a stop-band frequency of 80 kHz as shown in the
filter specification diagram of
figure 1. The filter is to have a gain of 1 and use a Maxim
MAX265 universal active filter in
mode 3. A block diagram of one of the required stages and
simple design equations are given
in figure 2. Use the Maxim filter design programme supplied on
disc.
Figure 1: Filter specification

Figure 2: Mode 3 second order filter
ELE2504- Electronic design and analysis 46
Design
1. Type ‘README’ and follow the instructions.
2. Run the MAXIM filter design programme filter by typing
‘FILTER’, select PZ and
specify the following when asked:
● lowpass
● Butterworth
● 3dB passband ripple
● fc = 10 000

● order = 3
● fstopband = 80 000
The Q values given by the programme can be checked against
the values calculated from
the previous theory in the study modules, based on the given
tables of poles.
3. At this stage in the programme, it is possible to do a plot of
frequency response on the
screen. Note that to do this it is necessary to flag the file
containing the frequency
response data, called PZ1A or a similar name.
4. Now it is necessary to run the PR programme which
calculates the resistor values
required to implement the filter. This must be done for each of
the two second order
sections separately.
Run PR and specify the following when asked:
● clock ratio 100–200 (for MAX265)
● lowpass

● order = 3
● mode 3
● fclock = 2 000 000
● fc = 10 000
● Q as given by the first programme
● gain = 1
This gives resistor values and clock ratio. The latter must be set
by a code to the I.C. and
the programme also specified this code.
Part C: Logarithmic amplifier design exercise
Design
Given any of the following transistor arrays, find the collector
current versus base-emitter
voltage characteristic of the transistors from the data sheet
which follows. Typical figures are
acceptable. Note that it is logarithmic over two decades of

current:
LM or CA 3045, 3046 or 3086.
All of these are similar electrically and are readily available
from suppliers. All are in
14 pin DIL packages and contain five similar transistors.
Design a logarithmic amplifier of the two-transistor type
described in the Study Book based
on this device and LM108 op. amps. whose characteristic is to
approximate the relationship:
Vout = –5 log (2Vin/2Vref)
as closely as possible at room temperature, over a two decade
range of Vin from 0.1V to 10V.
Arrange for Vout to always be > 0V. Data for the LM108 is
attached. Use to +/– 15 volt
supplies.
Simulation
Using MICROCAP simulate your circuit (using LM108 and
transistor 2N2222 in
MICROCAP) and plot Vout versus Vin. Do this at three
different temperatures, 0, 30 and

60 degree C. (Try various values for the lower limit in
MICROCAP (0.2 or above until it
works.)
Also simulate the simple logarithmic amplifier given in the
notes with the same op. amp. and
transistor and R = 10k ohms. (Specify MICROCAP Vin range at
10, 0.2, 0.1 for rapid results.)
Note that its variation with temperature is much greater than
that of the other circuit.
Test
Assemble the circuit. Spurious oscillation will probably occur
causing incorrect operation
and will need to be suppressed with capacitors such as fairly
large values (4.7 µF or more)
from the output to ground. Do not forget to use compensation
capacitors on the 308
according to the data sheet. If necessary, extra large values may
help stop oscillation.
Measure the characteristics of your amplifier using a digital
multimeter over its allowed
range of input voltages at room temperature.
Note: If you do not succeed in getting this circuit to work, it
may be because of spurious
oscillations which are very common. The use of an oscilloscope
would help to
identify and thus avoid these oscillations. However if you do
not have access to an

oscilloscope, try adding capacitance in other places or ring the
lecturer for advice.
a
National
Semiconductor
cD
Transistor/Diode Arrays
:E LM3045, LM3046, LM3086 Transistor Arrays
...I
General Description Features
The LM3045. LM3046. and LM3086 each cons;st
of five general purpose silicon NPN transistors on
a common monolithic substrate. Two of the tran·
sistors are internally connected to form a differ·
entially-connected pair. The transistors are well
suited to a wide variety of applications in low
power system in the DC through VHF range. They
may be used as discrete tran$istors in conventional
circuits however. in addition, they provide the
very significant inherent integrated circuit advan·

tages of close electrical nd thermal matchinq. The
LM3045 is supplied in a 14·1ead cavity dual·in·line
package rated for operation over the ful l military
temperature range. The LM3046 and LM3086 are
electrically identica l to the LM3045 but are
supplied ion a 14-lead molded dual-in-line package
for applications requiring only a limited tem per·
ature range.
• Two matched pairs of transistors
V11e matched :!:5 mV
Input offset current 2!JA maK at lc E 1 mA
• Five general purpose monolithic tran5istors
• Operation from DC to 120 MHz
• Wide operating current range
• Low noise figure 3.2 dB IYP at 1 kHz
• Full military
temperat ure range (LM3045) -55°C to +125°C
Applications
• General use in all types of signal proce$$ing
systems operating anywhere in the f requency
range from DC to VHF
• Custom designed differential amplif iers
• Temperature compensated amplifiers
Schematic and Connection Diagram

SUBST RATE
14 ll 12 11 10
Q)
TOHI!W
Otde·t Number LM3045J
S.o NS Pack-eo J14A
Order Numr LM3046N
or LM3088N
See NS Packogo N14A
(Source: National Semiconductor 1982, Linear databook,vol. 2,
p. 12-18. Reproduced with permission from
National Semiconductor.)
UNIVERSITY
Ill:SOUTHERN
QUEE
© University of Southern Queensland

(Source: National Semiconductor 1982, Linear databook, vol. 2,
(Source: National Semiconductor 1982, Linear databook, vol. 2,

[(Source: Texas Instruments 1989, Linear circuits data
book,vol.l, p. 2·23. Reproduced with pemrission from
Texas Instruments Ltd) ]
lM108,LM108A
OPERATIONAL AMPLIFIERS
electrical characteristics at specified free-air temperature, Vee±
= ±5 V to ±20 v (unless
otherwise noted)
PARAMETER TEST CONDmONS TAt LMTOBA LMTOB UNrr
MIN TYP MAX MIN TYP MAX
vlo lnpu1offset voltage Rs. soo 25'C 0.3 0.5 0.7 2 mV Fullrange
I 3
Temperature c:oeffi'cient
avto of inpu1offset voltage Fuilrange 1 5 3 15 JJ.Vl'C

llo Input offset current 25'C 0.05 0.2 0.05 0.2 nA Full range
0.4 0.4
Temperature coefficient
auo of lnptrt offset current Full range 0.5 2.5 0.5 2.5 pN'C
ltB Input bias current 25'C 0.5 2 0.5 2 nA Full range 3 3
Common·mode lnpu1
VtCR vohage range Vee± • ±t5V Fullrange tt3.5 :1:13.5 v
M111<imym pe!!k QYtp!1
VoM vohage swing
Vee±;.;t v.
Rt • 101<0 Full range :t13 ±13 v
Large·signal differential
Avo vohage amplillcation
Vee± :ttsv.
Vo•t10V,RL 101<0
25'C 80 300 50 300
V/mV Fullrange 40 25
r; Input resistance 25'C 30 70 30 70 MO
CMRR
Common-mode
rejectionratio
Fullrange 96 85 dB
Supply·vollage rejeclion
ksvR ratio (6Vcct /&V1o) Fullrange 96 80 dB

1cc Supply current 25'C 0.3 0.6 0.3 0.6 mA 125'C 0.15 0.4
0.15 0.4
1Fullrange is -ss•c to t2s•c.
TEXAS
INSTRUMENTS
POST <WFIC!£ BOX 055012• DAllAS.TEXAS 75265
2·2

Assignment 2
Assignment 2 200 20 12 October 2015
Part A: Switching regulator design exercise (9%)
Theoretical design
Note: This design is entirely theoretical. You will not be
expected to assemble the circuit
and test it.
Collect information
Data on the TL497AI switching voltage regulator is provided
from the Texas Instruments
1989 Linear circuits data book, volume 3, pages 2-135 to 2-141.
From this data assemble the
following:
● a table showing

● allowable input voltage range
● allowable output voltage range
● V ref (typical)
● switching transistor maximum current
● diode maximum current
● A sketch of the power dissipation rating curve.
Data on ferrite cores suitable for construction of inductors is
also provided.
Design
Using this data and the typical application data (use the basic
configuration even if current
values fall slightly outside the specified range), design a
regulator to meet the specifications
below. Include component ratings in your design and choose the
inductor core, wire size and
number of turns. Your design should also include thermal
considerations by estimating the

heat loss. If necessary, specify heat sink thermal resistance.
Specifications:
Type of regulator : Step down
Input voltage Vi : 24
Output voltage Vo : +5V
Output current Io : 300 mA
Maximum output ripple Vr : 50 mv
Ambient temperature Ta : 50 deg C
Report
Present a report containing the following:
● assembled data
● design calculations, including inductor core choice/details
● a circuit sketch using the same schematic layout as in the
data, and showing all
component values including ratings.

TL497AM, TL497AI, Tl497AC
SWITCHING VOlTAGE REGULATORS
• High Efficiency .•• 60% or Greater
• Output Current . . • 500 mA
• Input Current Umit Protection
• TTL Compatible Inhibit
• Adjustab e Output Voltage
• Input Regulation • .. 0.2% Typ
02225. JUNE 1976-REVISEO OCT06ER 1988
Tl497AM ... J PACKAGE n497AI.
TL497AC ... D.J, OR N PACKAGE (TOP
VIEW!
COMPINPUT VCC
INHISI-:- CUR LIM SENS
FREQ CONTROL BASE DRIVEt
SUBSTRATE BASE1
GNO COL OUT
• Output Regulation .•• 0.4% Typ
• Soft Start-up Capability

descrpi tion
CATHODE NC
ANODE '-1..: -J-' EMIT OUT
NC-No intcrn;..l conncct10n
1TheBospi(#111anll lhse Olive pin (#121 are used for devi ce
te$ting only. They are nolnormally 1.1sed in circ:uit
applications
of the device.
The TL497A incorporates on a single monol thic chip all the
active functions required in the construction
of a switching voltage regulator. t can also be used as the
controlelement to drive externalcomponents
for high-power-output appilcations.The TL497A was designed
for ease of use in step-up•, step-down, or
voltage inversion appHcations requiring high efficiency.
The TL497A is a fixed-on-time variable-frequency switching
voltage regulator controlcircuit.The on-time
is programmed by a single externalcapacitor connected between
the frequency controlpin and ground.
This capacitor,cr.is charged by an internalconstant-current
generator to a predetermined threshold.The
charging current and the threshold vary proportionally with
Vee.thus the one time remains constant over
the specified range of input voltage (5 to 12 V). Typicalon-
times for various values of CT are as follows:

The output voltage is controlled by an externalresistor ladder
network (R1 and R2 in Figures t, 2,
and 3) that provides a feedback voltage to the comparator
input.This feedback voltage is compared to
the reference voltage of 1.2 V (relative to the substrate pin) by
the high-gain comparator.When the output
voltage decays below the value required to maintain 1.2 Vat the
comparator input,the comparator enables
the oscillator circuit, which charges and discharges CT as
described above. The internalpass transistor
is driven on during the charging of Cr.The internal transistor
may be used driectly for switching currents
up to 500 mA. Its collector and emitter are uncommitted and it
is current driven to allow operation from
the positive supply voltage or ground. An internalSchottky
diode matched to the current characteristics
of the internaltransistor is also available for blocking or
commutating purposes. The TL497A also has
on-chip current-limit circuitry that senses the peak currents in
the switching regulator and protects the
inductor against saturation and the pass transistor against
overstress. The current limit is adjustable and
is programmed by a single sense resistor, RcL. connected
between pi'n 14 and pin 13.lihe current-limit
circuitry is activated when0.7 V is developed across
RCL·Externalgatingis provided by the inhibit input.
When the inhibit input is high, the output is turned off.
Simplicity of design is a primary feature of the TL497A.With
only six externalcomponents (three resistors,
two capacitors,and one inductor),the TL497A will operate in
numerous voltage conversion applications
(step-up,step-down,invert) with as much as 85% of the source
power delivered to the load.The TL497A
replaces the TL497 in all applications.

The TL497AMis characterized for operation over the full
military temperature range of - 55 °C to 125 °C,
the TL497AIis characterized for operation from -25°C to 85
°C,and! the TL497AC from 0°C to 70°C.
TEXAS "J1
INSTRUMENlS
POST OFFICE SOX 6S5012 • CALLAS, TEXAS 75255
Copvright (0 1983. Texas ln·struments lncorpotlttd
2-135
(Source: Texas lnsiTuments 1989, Linear circuits data book,vol.
3, p. 2-135. Reproduced with permission
from Texas lnsiTuments Ltd)
UNIVERSITY
Ill:SOUTHERN
QUEE

(Source: Texas Instruments 1989, Linear circuits data book, vol.
from Texas Instruments Ltd.)
PARAMETER TEST CONDITIONSI Tl497AM, TL497AI
TL497A C UNIT
MIN TYP' MAX MIN TYP1 MAX
High·level inhibit input cu rrent Vl(ll • 5 V Full range 0.8 1.5
0.8 1.5 mA
Low-levelmhltlll onput current Yl(l) "O V Full range s 20 5
10 A
Comparator reference volt g:u VI • 4.8 v 10 6 v Full range 1.14
1.20 1.26 1.08 1.20 1.32 v
Comparator input bias CLJrrent VI- 6 v Full range 40 100 40
100 A
Switch on-state voltage VI• 4.5 v 25 0. 13 0.2 0. 13 0.2 v llo-
SOD mA Full range 1 0.85
Sw tch off·state cunent v1 - 4. 5 v,v0 Jo v 25 10 50 10 50 A
Full range 500 200
Currem·lfmlt sense voltage VI • 6 v 2s•c 0.45 1 0.45 1 v
Diode forward voltage
10 • lOrnA Full range 0.78 0.95 0.75 0.85
v IO • 100 mA Full range 0.9 1.1 0.9 1
lo • 500 mA Full range 1.33 1.75 1.33 1.55

DiOde reven:e vol,age
IO a 500 ,.A Full range 30 v lo • 200 ,.A Full range 30
On-state supply c1.1rrent 2s•c 11 14 11 14 mA Fullrange 16
15
011-stata supply current 25•c 6 9 6 9 mA Fu range 11 10
TL497AM. Tl497AI,TL497AC
SWITCHING VOLTAGE REGULATORS
recommended operat ng conditions
MIN MAX UNIT
Input voltage,V1
4.5 12 v
H gh-levelinhibit input voltage,V1H
2. 5 v
Lowlevellnhlblt Input voltage,V;L
0. 8 v
I Step-up configuration (aee Figure 1) v1+2 30
Output voltage I Step-down configuration (see Figure 21
Vref Vt 1 v
I lnvening regulator (aee Figure 31 -Vref -25
Power switch currant
500 mA
Diode forward curront
500 mA

electrical characteristi'cs at specified free-air temperature, VJ -
6 v (unless otherwise notedl
fll
,1'0 - 100 mA
11'ul,.nge for TL497AM is -ss•c to t25°C, for TL497AIis -
25°C to 85°C. and for TL497AC is 0°C to 70"C.
1Alltypical values are at TA = 25•c.
TEXAS .
INSTRUMENTS
POST OFRC( 10)( f5fi012 • OAll.AS, TEXAS 7S2U

2-137
(Source: Texas Instruments 1989, Linear circuits data book,vol.
3, p.2·137. Reproduced with pennission
from Texas InstrumentsLtd)
UNIVERSITY
!It SOUTHERN
QUEE ,
® University of Southern Queensland
l
1 T I r-
TYPICAL APPLICATOI N DATA
Vo
DESIGN EQUATIONS
• IPK a 2 IO max [: j
14 13 10 8 R1

Tl 497 r-- c
1 2 3 4 s e 7 R2 •
v,
• L (#IH) • IPK ton(l.lsl
Choose l (50 to 500 J.IH l.calculate
ton (25 to ISOo sl
I cr+ f I I 1.2 kll
L I 1
• CTCPFI ..
t 2 toniiJSI
• A t • (VO- 1.2) kfl
BASIC CONFIGURATION
IIPK < 600 mAl
0.5V
• RcL•--
IPK
[.::L IPK + 10]
• CF ().IF) Qo toniJ.Isl.>:..v_o

Vripple (PKl
R1
TL497
R2 •
1.2 k{l
EXTENDED POWER CONFIGURATION
(USNI G EXTERNATl RANSISTOR!
FIGURE 1. POSITIVE REGULATOR, STEP-UP
CONFIGURATIONS

2-138 TEXAS .J./1 INSlRUMENTS
P OST OffiCE 80X G$5012 • DAlLAS.TfXAS 11211
(Source: Texas Instruments 1989, linear circuits data book,vol.
3, p. 2-138. Reproduced with pennission
from Texas Instruments Ltd)
UNIVERSITY
!If SOUTHERN
QUEE
©University of Southern Queensland
ELE2504 -Electronic design and analysis 44
L

1 1
E
TYPICAL APPLICATION DATA
Rt •
1.2 kll
Vo
• IPK • 2 IO max [1+ : ]
v,
• L (IJH) "' - t0n11Js)
lPK
Choose L (50 to 500 JH),calculate
ton (25 to 150 ps)
• Cr(pF) ""' 12 t00(1Js)
0
.Q...).
Q.)

en
BASIC CONAGURATION
llpK < 600 mAl
• R2 • !Vo - 1.21kn
0.5 v
• RcL • -
lpK ar v. r- t()r---------- ---- -- +
.(.D.. en 10 8 RZ
TL497 *
R1 •
1.2 k!l
.L-+-------------vo
VI IPK + lo]
• CF (pF) "'toniiJs) ..:..V.;:o :_
Vripple (PK)
•u$t ex1ernlil eelch-dlode,e.g., 1N4001, when building en
;nven;ng •upply ,.;th the TL497A.

EXTENDED POWER CONAGURATION
{USING EXTERNAL TRAIIISISTORI
FIGURE 3. NVERTING APPLICATIONS
2-140 TEXAS I
NSTRUMENTS
POST OFFICE 80X 6S!i012 • DAlLAS, TEXAS 75.285
(Somce: Texas Instruments1989,Linear circuits data book,vol.
3,p.2-140. Reproduced with permission
from Texas Instruments Ltd)
UNIVERSITY
!It SOUTHERN
QUEE, :
® University of Southern Queensland
Proper t es of core assemblei s at 25°C (without adjusters)
Stock number
RM6 RM6 RMl RM10 RMIO

228-214 228-220 228-236 228-242 221-268
Inductance factor ""'-
Tumsfactor a
(turns for 1mH)
Effect ve permeability JJ.
Temp.coeft.of "•
(+25 to50"C) ppmi"C
Adjuster range
Max.residualplus eddy current coreloss
Tengenttand,+,111:JOkllz
at lOOkHz
Recommended frequency range (kHz)
Energy storagecapabtkty (mJ) UJ.,.,
B... mT
160 250 250 250 400
79.06 63.25 63.25 63.25 50.00
±1% ±1% ±1% ±1% ±1%
109.5 171.1 146.0 99.67 159.5
51min. SOmin 73min. 50min. SOmin.
t54max. 241max. 219max. 149max. 239max.
+20% +14% +15% +17% +20%
0.34 X 10 ' 0.53 X 10' 0.47 X 1()-0 0.32 X 10" 0.51 X 10'
0.58 X 10" 0.91 X 1(}-' 0.82x 10"' 0.60X 1(}-' 0.96 X 10
5.5 to800 3.5to700 3to650 2to650 1.2 to500
0.383 0.245 MOo 1.731 10. 82
250 250 250 250 250
RM
Data Library

Issued July 1985 5n4
RM series ferrite cores
Stock numbers 228-214 to 228-258
A range of 5 of the most popular pcb mounting
ferrite cores covering three sizes.Of square design
which 11llows moximum boord ut lisation, this
series enables transformers or inductors to be
constructed to meet exact customer requirements.
The core material is equivael nt to the commonly
known grades:A13-0.3-N28.Each core is
supplied
Inkit formandcon"slsts of the folloWing:one pair of
matched half cores,one single section bobbin with
Integralpins on an 0.1in grid,one pair of retani
ing clips with earth spikes andone core adjuster.
To determine the number of turns required for a
particularinductance use the following formula:
No,turns = vi""
Where L = inductance in nH (1 H).
For frequencies in excess of 30kHz, the use of stranded

wire is beneficial when maximum a is
Features
e 5 versions available in three popular szi es e PCB mounting e
Compact design e Mountni g pinshave 2.64mm (0.11n) spocing
•l . •
required.
(nH/tum3') ±2% :t2% :!:2% ±2% :t2%
Magnetic propertie$ of c:ores
Effective path l ength
Effective patharea
Effective volume

symbol RM6
I, 26.9mm
A., 31.3mm'
V0 840mm'
RM7
29.6mm
40.3mm'
1100mm'
RM JO
41.7mm
83.2mm'
3470mm'
Maximum turns acmmodated on bobbin
wiredia.(mm} RM6 RM7 RMJO wiredia.(mmJ RM6 RM7
RM10
0.2 205 306 612 0.56 25 36 87
0.224 160 250 484 0.71 19 33 59
0.25 127 209 402 0.8 13 19 44
0.315 87 131 246 1.0 9 11 25
0.4 47 76 160 1.25 4 9 19
0.5 36 50 98 1.5 3 7 11
(Source: RS Components 1985, Data sheet no. 5774,July.
Reproduced with permission from
RS Components Pty Ltd.)

UNIVERSITY
!If SOUTHERN
QUEE,'!'.
©University of Southern OJeensland
Part B: Oscillator design exercise (7%)
Measure/simulate
Measure the voltage-controlled resistance characteristic of a 2N
5484 (sim: 2N 3822)
N-channel JFET, by the following procedure:
1. Set up the following circuit, noting that the gate voltage is
of the opposite polarity to the
drain voltage. If you do not have access to both these voltages,
it is easy to put a voltage
divider (say a pot of value several k ohms) across almost any
voltage to supply the gate
because it is a low current input.
2.

● Set VGS to 0V.
● Vary RD over a range and at a variety of points, record VDS
and VR in a table.
● Set VGS to –1V, –2V, –3V, –4V in turn and for each, repeat
the procedure above.
(simulate: –0.5, –1, –1.5, –2, –2.5).
3. Convert the VR value to ID, by dividing by the R value
(120Ω).
4. Plot a series of curves, one for each value of VGS on ID
versus VDS axes.
5. For each curve identify the linear region around the origin,
and evaluate:
RDS
6. Finally plot RDS versus VGS.

Design
Design a Wein Bridge Oscillator using a 741 operational
amplifier as the active element.
Amplitude stabilisation is to be achieved using the JFET as a
voltage controlled resistance.
Follow the procedure given in the study modules.
The oscillator specifications are to be individualised as supplied
on the StudyDesk:
Power supply voltage: ______
Frequency: ______
Amplitude: ______
Test/simulate
The following test may be performed using any equipment you
have access to. Results from
a moving coil multimeter or a digital multimeter are
satisfactory, but an oscilloscope is
desirable.
Check the correct operation of your oscillator by measuring
operating voltages at significant
nodes. These will need to be compared with design values in

your report. These should
include the following points: + terminal of op. amp, output of
op. amp., voltage across C1,
voltage on gate.
NB: If you suspect the oscillator is operating but is clipping,
replace R3 and R4 with a pot,
say 10 k. This will act as an amplitude control, and will allow
you to reduce the
amplitude below clipping level.
Report
Submit a written report which should contain only the
following:
● a sketch of the final circuit
● a comparison in a table of design and measured voltages, both
a.c. and d.c. at significant
nodes
● include your plots of the JFET characteristics
● any comments you may wish to make.
UNIVERSITY

Ill:SOUTHERN
QUEE
Part C: Electronic integrated circuits ICs (4%)
Select two ICs and submit a short report for each, covering the
following details:
● what the IC is (name, type)
● explanation of the IC’s features and how it works
● sample circuit application making use of its feature(s) with a
circuit operation
explanation (include any relevant calculations).
IC list:
4052

LM 135
NE 567
4028
LM 3914
LM 723
4N 27
LM 331

Data sheets
(Source: Texas Instruments 1988, The TTL logic data book, p.
2-5. Reproduced with permission from Texas
Instruments Ltd.)
Instruments Ltd.)

Instruments Ltd.)
--------------
--------------

--------------
--------------
--------------

(Source: Fairchild Semiconductor Corporation 1999. Available
from: <http://www.fairchildsemi.com>.
Reproduced with permission from Fairchild Semiconductor
Corporation.)
http://www.fairchildsemi.com

(Source: National Semiconductor 1988, CMOS logic databook,
4001

..
National
Semiconductor .
Voltage Comparators
LM139/239/339,LM139A/239A/339A, LM2901,LM3302
Low Power Low Offset Voltage Quad Comparators
General Description
The LM139 !'-rit!1 eon1•1U of four independent
prcisoon voltaqe comp,.ltors wuh an offset voll
age specifiaotoon H low as 2 mV max lor all four
compautors. These were ignerl :wecof ically to
operate f rom 1 single POwer supply over a w•
flnge of volts. Or>trlloor; ftom spht pewer
supplies •s also pessible And tlw. low pOw.,supply
current drau> is o ndependent of the m"'Jmt ude uf
the pewer supply voltilge These comparators also
• ElirT-unates need lor dual supphes
• Allows sens•ng near gnd
• Compatible With all forms of logoc
• Power c1raon suitable for battery operatoon
Features
• Wide single supply vollage range or dual sup·

plies
hive a uniQuchlractr.fl tic o n lhal the on put
common-mode vOIIJ9e range onc;ludes ground.
ewn though operattd from 1 l•n<Jie pewer supply
LM139 series,
LM139A seroes. LM2901
LMJJ02
2 VOC to 36 Voc or
!I v0c to !18 v0c
2 voc to 28 voc
volt«.
Applicatooneas onclude lomot c:omiJitrators. somple
analog to dogual convertftrs. puis.sQuarewave and
time dtlay generatO<s; wode range VCO;MOS clock
or !1 VOC to !14 VoC
a Very low supply current drain 10.8 mA) -
o ndependent ot supply voltage 12 mW/compara·
tor at •5 Voc;l
timers; multivib<llors and ho9f"l voluge digiul logic
gates. The LM139 series was des19ned to directly
interface with TTL and CMOS. When operattd
• Low input bias;n<J current
• Low inpul offset current
and offset volt e
25nA
!5nA

!JmV
from both plus and monus pewsupplies. they
w1ll directly int face wuh "-10S log1c where t he
low pawer drain of the LMJ.J9 1S a distinct ldvan-
tage ovstandard comoar11ors.
• Input common -mode voltage rnge 1nclude1gnd
• Oifferenotinout •oltage r nge eQual to the
pewer supply voltage
Advantages
• Lowoutput
satu•atton voltage
250mV at 4 mA
• High p<ecisoon comp;orttors
• Reductd Vos drift over temperalur
Schematic and Connection Diagrams
. ...
• Outout voltage compat o ble with TTL. OTL.
ECL. MOS •nd CMOS log;e svnems

..,............ .......
0...H- l.M1.l.Ml:JIA.I,
l..l.M23tA.I,LM331J.
LM331SA.J., LM2101J "' LM3302J
NS , J14A
TypicalApplications 1v•- s.o v0el
..
0...H-LM:JftN,LM339AN,
l.-1N 0< LM3302N
S.. NS --Nl4A
....... .....
··-,
......
...,•.,. .
lettc COit'loetetOt Or..,,.CMOS
5-27

(Source: National Semiconductor 1982,Linear databook,vol. 1,
pp. 5· 27 -5-31. Reproduced with
pennission from National Semiconductor.)
UNIVERSITY
01' SOUTI ERN
QUEENSLAND
AUI IA IA
©University of Southern OJeensland
> -
X
•o
"'
: I
:::J

·
:;;
c;;i
Absolute Maxmi um Rat ngs
LM13t/lM23t/llol33t
lM13tAII.IIiU3tAILM33tA I.M330l
LMltOl
U'lj;.t::
... _Vl
Z"'- l O:Z-(
Su1>91Y Votoott.v' 36 VDc"' ua vDc ll voc or u• voc
Oifftr•ntttllnput Vohttt 38VDc li VDc
lnoot Voltott -o.3voc 10 t36voc -o.3voc to t21 voc
Power OluiDIII011 tNote 1)
Molded Dlr 570 rnW 570 rnW
C.•ily DIP IOOmW
F''' reel 100 tnW
OuOpul Shon.Circuil to GNO.II;ott 21 Continuous Continuous
ln,..l Curr tni iVIN <-11.3 VDcl. 'INott 31 SO rnA SOmA
O,...raliftt Tt MC Mitttur t R tf'ltlt

LM339A o•c to •7o•c -4o•c •n•c
LM,:I!IA -25 c to +85 c
lM7901 -.co•c to •as•c
LMIJ9A - 55 C to +125'C
StOUOt hrnPf"tur• Ranft -66•c to ·t1&o•c -66·c to + 1so•c
l•MI Tempe,.tult (Soldtrlng, 10 wcondtl :JOO'c 300 C
ElectricalCharacteristics IV'• 5 Voc • Note 41
lM13tA lMUtA, LMJ)tA lMI)I lMUt,LMJ)I lM210t lMlJOl
,AIIAMITlll CONDITIONS
MIN TYP MilX MIN TYP MAX MI N TYP
MAX MIN TYP MAX MI N TVP MA X MIN
TVP
UNITS
lnout Olht1 Voll>ft T"• 2s c.INol•91 ti.O 12.0 ti.O 17.0 t2.0
tS.O u.o 15.0 t2.0 !7.0 13 120 ..voc
Input litt Cuutnt I tNt•) ot I'N-It withOutpu·t in 25 100 25
250 25 tOO 25 250 25 250 25 500 •IIDC m
Linnr Rt"9'.T14. • 2s•c.(Note 51 rm
tff)ut0ft..,.1Cunt nt ltNC•I- IINI-1· 1II • 25'C u.o 12$ 15.0
u;o tJ.O 125 15.0 150 !5 t50 13 t100 nADC 1.)
@
:::>
-

iil
·
g,
(/)
fnput COII'ImOft Modt VOttttt TA • n•t.INolt 81 0 v*-t.s 0
v'-u 0 v*-1.5 0 v•-,.s 0 v*-•.s 0 v*-1s vDc
Aa.,..
$uii)OIV'CUI'rtftt RL •-on tn CC>fnPtrttort, TA • 25•c 0.8 20
O.t 20 01 20 0.8 2.0 01 20 0.1 2 ""'DC
Al •• .v'• "JtN.TA • 25"C 1 1!> lnAOC
Volt-.Gt n Al ;;: 15 •n.v'• t5 voc CT• 50 200 50 200 200 200
25 100 1 JO VltnV
Su-ll"f' Yosw-..1.TA • 2S"C
l•rtt Sitnll Rt't)OnM r;mc VeN • Til lOll"= 9orint.Vftef • 300
:JOO 300 300 300 300
1 4 Voc.VAL •6 VDC·Rt •5.1 k!l.
T,., u c
R•t.OOI'tt4' Tlmt VRt • 5 Voc.RL •5.1 k!l. 1.3 1.3 1.3 1.3 1.3
t.3
TA • 25"C.INolt 71
I
m
(D
a

;::;·
c.
(I)
I"E'"
::I
II)
c.
0c
ISI,..K S 4 mA.TA • 1s•c
- 000 150
- ""voc
II)
5'-
3
1?
(1)
:::J
OJ
0ltput Sin: Cvt, nt VINH1 VDt·YI NI•I'0. e.G 18 8.0 16 80

18 . 6.0 16 8.0 16 60 16 mADC
VO S 1.5 VDC·TA • 25'C
S.turellonVI NoC•lIIt•Voc.VINI•I" 0. 250 400 260 400 250
400 250
Outf)UIL• •ll..,.CuH•nt VNI I•.1 Voc.VtN-I 1"0, 0 I 0.1 0 I 0 I
01
0 I "'""ur.
Vo • I Voc.TA • 2'S"'C
::I
II)
iii"
D. ....,
I
I»
<r
Electrci alCharacteristics (Contonuedl
co
LM1HA lM2JeA, lMJaA LM1Je L.lMlH LM2t01 lMllOZ

m
.0!jC fARAMEUR OONOITIONS UNITS rm cm"o'z IMIN
TVI' MAX MI N TVf MAX MIN rn MAX MIN
TVP MAll MIN TVP MAX l!IIN TVP MAX N
!2c < Input Olf..t Vo1Utt INote it 4.0 4.0 to t.O • 15 •o mvoc
:e!:l
z>r.tS,!.:.!;! I"'PY'Offwt Ct" 4"'1 IINI•J - IINI I tiOO ·· &100
II flO flO 200 JOO •Aoe (.J1 0
I
OZ -<
@

c
::>
-
.izil
lnp,·ta..,Cvuent ••t. c•• 01 ltNc-• ...,,, " OutSM-·• .,.. 300 400
300 400 200 500 1000 ""DC
LIM... ,...,..
Jopul Common M-1/oll.,.l 0 v•-2 o 0 v•-2..0 0 v'-2.0 o v'-
2.0 0 v'-1.0 0 v'-201 voc
Aan91
S.tuUioon loll.., IIJNI- 1/oc.IIJNitl • 0. 700 100 700 100 400
700 700 I mVoc
ISINK S 4 mA
()vlpvLl u"_,. c,..,."' I"•Nto voc. viNt-J • o. 1.0 1.0 I 0 I 0 1.0
I 1.0 I Aoc
11o•JOVoc
Q,Htltnt•JII nput V01t..... IK,.p aiiiiJI'I0'' Voc lor v . I 38 I
:18 I 36 I 36 I 0 36 I 28 I voc
iluoodl INott8J
Nolo 1: For opora1t09 at high tompe<llurH, tho
LM3l!IILMJ39A, LM1901, LM3302 mutt bo de<llod based on
1 125 C moximum function lf,.,.,..tlllf O oncl• thtl'mll
rotitlonce ol 115'CIW wluch opploot 101
tht devic:t JOkiertd u o1 C)rinted clrcuh botrd.operatint in t
atill air ambi.nt. T.... LM239 and LM139•• bt derated bolted
Ofl t 15CfC n"Mximum Junction ttmplftU.Ift. The tow b'-
dlttii)IC1on and lht ''ON·
OFF" chtrK tllftt'c ot 1he outu k11p1tht chip diuipetJon 111rys

fl IPo 100 mW), provkted the output transl-llon art altowtd to
uturatt.
Nott 2: Shore c rcu•u ftom the output to v• etn CIUM tJCC.
IIit Matint tnct tYtntual dtstructk>n.Tht ma•imum output cuutnt
lllpPfOMimtlel';' 20 mA independent of the m-enitude of v•.
Note 3: This input cutrtnt will only exist when tht voh...at
any of tht Input ltadt ft driven neoative.It is dto the
cotltctor·blaelutnetion of tht Input PNP tr thtora becoming
fiOtwttd bial!td and thtrtby
ecunv u input dtOde cl:ampa.. lf'l edduion to thi,stdhkKtrMt
eisteihoonlltef'., NPN par.. itic transistor ec1ion on the IC
chip.ThiJ uanduor .::tion c:an cause thl output vollages ot U'tl
cof't"tCMratots to go to the
v• vohage lrv-el lor 10 gtound forllrf': overdrive) tor tN dmt
duurton lhat tn input is drivtn ntg; tiYe.This is not dfttruc·cive
end norml ouq,ut statfl will re..stablis.h when the il"ll)ut
"ohao•.W' Whic·h WIS n t·
liYo,...,n ttturns10 I WIUI !JIIIIIIhln -o.3 Voc (II 2S'Cl.
Nolo 4: ThoSI >ptCollcations opply tor V 4 • S Voc anci-6S'C
< T.t. S, t125' C. unlou othtrwillllllod.With tho LM23$/LM
391,,•lltompolllurospocific:&lions arolimittd to - 25 C $ TA S.
t86' C, lho
LM339/LM339A ot ruuro ipiCiiicotlons aro limited to o•c
TA:S. t70'C, ond tho LM2901, LM3302 llmJMroturo ronsro
loO' CTA S t8S'C.
Note 5; The dirtttton of the input curnnt is oua of tht IC due
to tht PNP Input stage.This current it tutntiatly
constant.indtJMndtnt of tht stett of the outpvt so no loading
change exius on the rtf eunc•0t
input hnH.
Note 1: Tht input common-mode vollatt or tither input
tign1lvoltaoe should not be atlowed to 10 negt ve by mort th•n
0.3V.Tht uppt:r lnd of tht common.fTOde voh•,.,. is v• -
1.5V.but eithtt ot
boch tnpuu can go to •30 Voc withou1dam• C25V for lM3302L
Note 7: The r•sponM ume specified is 1 100 mV input l'ep with

5 mV owrdrivt.for fargtt overdrivt sign ls 300 ns can be ob
eintd,...typteat performenc:t chMac:ttr•nic·s s.Kt•on.
Noll! 1: Potlt•vt ucurstons of tivoltage m1v exceed tht pewer
supply level. As lone ts cht othtr vohaoe rem•lns within tht
cornmon·modt r.tn8'f , tht c;omp.aretor will proYKit a pfoptr
output St411t.Thtl ow
onput vohogo """ mut' no1 bo !m thon -0.3 Voc ,.,0.3 Voc
IMiow tho moonlludo ot tho M0011Yo powor 1upply, if
usodllat 26' CI.
Noto 1: At outputswotch point, v0 ,. 1.4 voc. Rs•on with v• r.om
6 Voc: •ncl ov., tho lull I"""'common·mudo rango!O Voc to v+ -
1.6 V(icl.
m
iD
!l
0
:; :J;·
c.
CD
<"0'
::J
I»
:c:J.
I»
::J
-<
"ii'i'
(f)
0c
::T ro

3
0 c m m
::0
(fJ
Oi'
::>
Q_
1·-. ....V""-" .-.•.I
V".'. ._,.(
14 • I C
r..• •tt i C , l"..,••UC ·•i"'CI- I I
WVT OVIIJIH'tVt • ••V
l ll JL
11
c
-
-
••

u .
·
- .
•
"
::
..
TypicalPerformance Characteristics
LM139/LM2J9/LMJJ9.LM139AILM239AILMJ39A.LMJ302
.u. 1.
SuPOiyCutf'eftl
•
1..
ll'ltklt Cun.nt
.:
l
:y --·t--1--t--rt-;
c

u ..
1.1
! II t-+--t--1......-+--+--i i ! :"' ..•. u
..!
Surrt.'t VOl.TAClfVacf
•• "
)I .. ••
A--Timo lew V..io<.t,
Input 0werdri¥el - Neptive
-Timt fat V61Mkoi
lnpwl Ow.*f"'- 'otoitiw
I.I•V • U" UT
OV(ADifUVl
•
I =
u
,./ u

u
21 •• - J•··JL
_l_l l
::i
!,;:
.... u
Tlllllf.;;IIIM.I
L!w -
... Lt
"';''»' •
t.i ,...I.I.... U Z t
TypicalPerformance Characteristics LM2901
s..pp yc... _ Input CUlT._
1.1 ! l •
Output S.tw.ttoi'l Vott.at-
a=..

i...
;:
" ll
j
Y'.SUfft.Y YOL.TAGl Vocl
.. u
R.-.on•Tim•fof Vatious
..,...,O._.,drfw--N..atNe
.. u
A"POn• T•me tcw v.,iow
Input Ovwdr..,.....Potitin
:! u

-'-
i
5.8•V •1IW OT OV?UIOfiUVE: u - u-
. "' WUlGVlRDAIVI • IMeV
_L
i u H,.-'" .11
1_ hvf_ :: u
- u
0
••• .
I _l
. -
-
!_l
:.:u
i ••
-. _ ••
11•Vjl_ .. -
- 1I .
: :•.'u
u 1.1 1 lt
;.}

;
I
_I ! I
5-30
UNIVERSITY Of SOUTII ERN QUEENSLAND ....u••uu.
University of Southern
Queensland
.

Application Hints
The LM139 series are high gain , wide b1ndwidth
devices which, like most comparators, can easily
oscillote if the output lnd is inadvt!rtently allowed
to capac:itively couple to tt>e inputs via stray
CII)ICit n<» This shows up only during the output
volt.ge tr.,sitlon intervals as the comparator chan·
ges states. Power supply bypassing is not required
to solve this problem. Standard PC board layout
is helpful as it reduces stray input.output coupling.
Reducing the input resistors to < 10 kfl reduces
the feedback. signol levels and finally, adding even
a smoll omount ( 1 to 10 mV) of POSitive feedback
(hysteresis) auses such a rapid transition that
oscillations due to stray feedback J<e not POssible.
Simply socketing the IC and attaching resistors to
the pins will couse input'Output oscillations during
the small transition intervals unless hysteresis is
used. If the input signal is a pulse waveform, with
relatively fast rise and fall times, hysteresis is not
r ired.
All pins of any unused com!NfatOrs should be
!P'ounded.
The bies network of the LM139 serie-s establishes a
chin current which is independent of the magni·
tude of the POW9< supply voltage over the range
of frnm 2 Vee to 30 Voc·

It is usually unnecesSiry to use a bypass capacitor
ICrOSS the power supply line.
TypicalApplications tv• = 15 v0cl
,.. ,.
The differential input voltage may be larger t han
v• without damaging the devoce. Protection should
be provided to prevent the Input voltages f rom
going negative more than -0.3 V0c (It 25"C). An
input clamp dtode can be used n shown in the
applications section.
Theoutput of the LM139 tr
collector of a grounded-emitter NPN output tran·
sistor. Many collectors can be tied together to
p<ovide an output OR'ing function. An output
pull-up resistor can be connected to "'Y available
power supply voltage within the permitted supply
voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which
is applied to the v+ terminal of the LM139A
package. The output can also be used as a simple
SPST switch to ground (when a pull up resistor is
not used). The amount of current which the
output device can sink is limited by the drive
available (which is independent of v•) and the /l
of this device. When the ma11imurn urrtnt limit
i$ ruched (approx irmtely 16 mAl. the output

tr nsistor will come out of Slturation and the
output voltage will rise very rapidly. The output
saturation voltage i$ limited by the approximately
&Ofl r.., of the output transistor. The low offset
voltage of the output tronsistor (1 mV) allows
the output to clamp essentially to ground level
for .small load currents.
..
-
·;_r., '
OR Gflo

Pin outs
Instruments Ltd.)
Instruments Ltd.)
•
National
Semiconductor
MM54HCOO/MM74HCOO
Quad 2·1nput NAND Gate

GeneralDescription
These NAND gates utilize advanced silicon-gate CMOS
technology to achieve operating speeds similar to LS·TTL
gates with the low power consumption of stsndard CMOS
Integrated circuits.All gates have buffered outputs. All de·
vices have high noise Immunity and the ability to drive 10
LS.TTL loads.The 54HC/74HC logic family is functionally
as wellali pin-out compatible with the sj;andard 54LS/74LS
logic family. All Inputs are protected from damage due to
static discharge b)' internal diode clamps to Vee and
ground.
Connection and Logic Diagrams
Features
• Typicalpropagation delay: 8 ns
• Wide power supply range:2-6V
• Low quiescent current 20 J>A maximum (74HC Series)
• Low input current:1 )'A maximum
• Fanout of 10 LS-TTL loads
Dual·ln·Una Package
2

A1 81
Y1 A2
Top VIew
12 BND
TUF/5282-t
Otder Number MM54HCOO'or MM74HCOO'
'Pieaselool< IntoS.Ct!On8,Appendix DlOt evailabit;ty ovl
ariouopact<age typn.
TI./F/&202-2
3-3
p. 3·3. Reproduced with pennission from
UNIVERSITY
Ill:SOUTHERN

QUEE
-
Q
-
o..... r---------------------------------------------------------------
iN tional
B
:..I.E..
Semiconductor
§ CD4001M/CD4001C Quadruple 2-lnput NOR Gate
0 CD4011M/CD4011C Quadruple 2-lnput NAND Gate
0......
C)
(.)

:E
GeneralDescription
The CD4001M/CD4001C,CD4011M/CD4011C are mono-
lithic complementary MOS (CMOS) quadruple two-input
NOR and NAND gate integrated circuits.N· and
P.roannol enhancement mode ttansistors provide a
symmetrical eir-
Features
• Wide supply voltage range
• Low power
• High noiseImmunity
3.0V to 16V
10 nw (typ.)
0.45 v00 (typ.)
e; cuit with output swings essentially equalto the supply volt-
C) age.This results In high noise Immunity over a wide supply
voltage range. No DC power other than that causedby leak-
0 age current Is consumed during static conditions. All inputs
are protected against static discharge end latching condi-
tions.
Connection Diagrams
v.,.
Dual-In-Una Package

1J 12 11 10 I •
n h
1 z J • 5 I I'
TopVIew
CD4011M/CD4011C
DuaJ.In-UnePackage
TUF/6038-1
Top View
CD4001M/CD4001C
Order Number CD4001'or CD4011'
•PI<IuelookIntoSec1Jon8,-'l>l>endix DtO< avalllllililyof
variouspackage types.
5-6

TUF/5938-2
p. 5-6. Reproduced with pennission from
UNIVERSITY
Ill:SOUTHERN
QUEE

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