Lorenzo Electronics Binary Scan Tester (LE1210) Application Notes

1. Lorenzo Electronics
LE1210
Digital ICT & BST Tester
with ATPG
Application Notes - AN101

2. Scope (1)
● Demonstrates LE1210 Digital Tester (DGT) &
BST tester running tests over portions of DGT
System board.
● Automatic Test Program Generation (ATPG) for
both DGT and BST test vectors.
● Capable of detecting Device Under Test (DUT)
Boundary Scan (BSC) IC pins pin-short and
pin-open faults.

3. Scope (2)
● Test Setup file allowing ATPG customization.
● ATPG test vectors cover all properly equipped
BSC nodes in the test generation setup file.
● Excluding tester power sequences, running
complete test vectors took less than 1 sec.
● Logging files contain detailed logic states of
DGT pins and BSC cells, as well as the fault
indication, if any.

4. Test Setup (1)
● As shown in page 6, the System board has 4
BSC capable FPGA chips which are partitioned
into 2 disjointed sections where each section
has its own JTAG network.
● Chips U2/U3 will have their JTAG port
connected to BST JTAG Controller (page 7).
With that, U2/U3 and the associated circuits will
be converted into a DUT.
● DGT pins 129 - 256 are still capable of
performing digital ICT tester functions.

5. Test Setup (2)
● In Test Interface Board (P.7), 8 jumper wires are
connecting the “converted” DUT to the DGT
pins 129 – 136.
● DUT equivalent circuit, labeled with original
DGT pin number in tester interface board,
FPGA pin's port names defined in its BSDL file,
is depicted on Page 8.
● With Buffer chip's directional control properly
taken care of, the selected U3 pins and the
DGT pins logic states can mirror each other.

6. DUT DGT Tester
U2/U3 JTAG port
U2 U3 U4 U5
System Board

7. Jumper wires interconnecting
DGT tester pins 121-128 and 129-136
JTAG Controller
connected to U2/U3 JTAG port
Test Interface Board: Connections

8. BSC ports DGTDUT
DUT Equivalent Circuit
u3
U3.84
U3.83
U3.82
U3.79
U3.78
U3.77
U3.76
U3.75

9. Pindef (1)

10. Pindef (2)
● Pindef setup file name: pindef.csv, a comma
separated variables file.
● First column entries are the DGT pin numbers.
Valid pin number: 1 – 256.
● Second column is for Netlist file's BSC dev/pin
names whose nodes are “connected” to digital
tester pins.
● Third column defines DUT data direction.
● Fourth column is used for defining a fixed logic
level applying to / detected by the DGT.

11. Test Setup File (1)
#bsc
device u2 extest xc3s50an_tq144.bsd;
device u3 extest xc3s50an_tq144.bsd;
devicechain u2 u3;
freq 10000000;
#endbsc
#netlist
file system_board.asc;
power_rail power vcc vccb1 vccb2;
power_rail ground gnd;
pin_name p;
put0 u3.72;
bypass u3.43 u3.44 u3.45 u3.46 u3.47 u3.48 u3.49 u3.50 u3.51 u3.53;
bypass u3.55 u3.57 u3.58 u3.59 u3.60 u3.62 u3.63 u3.64;
bypass u3.67 u3.68 u3.69;
bypass u2.70 u3.70;
get1 u3.42;
#endnetlist

12. Test Setup File (2)
● Test setup file name: 1.src.
● 2 separate sections: BSC and Netlist. Each
section starts with #bsc / #netlist, and ended
with #endbsc / #endnetlist.
● A setup statement starts with a keyword (p.11,
e.g. device) followed by one or more entries as
needed. End of the statement line must be
delimited by a semicolon.

13. Test Setup File (3)
● #bsc device line defines a BSC device name
listed in the netlist file, and the associated
BSDL file.
● #bsc devicechain line defines the order of BSC
devices connected to the JTAG port. It starts
with the device that has its tdi pin connected to
that of JTAG port, … , the last device that has
its tdo pin connected to the JTAG tdo pin.
● #bsc freq line allows user to adjust the tck clock
rate if needed. If not specified, ATPG will set to
the lowest clock rate of the BSC device in the
devicechain.

14. Test Setup File (4)
● #netlist power_rail power line defines one or
more power rail alias used in the netlist file.
● #netlist power_rail ground line defines one or
more ground plan alias used in the netlist file.
● #netlist bypass line defines a set of BSC
device/pin names, listed in netlist file, but will
not be used by LE1210 test generation process.
For that, their BSC output cells will be set to hi-
z state while their BSC input cells captured data
will be ignored. In this test, a few BSC pins are
bypassed due to their connections to the active
DGT MPU bus.

15. Test Setup File (5)
● #netlist get1 (or get0) line defines one or more
BSC dev/pin names, listed in netlist file, will use
their input cells to check for fixed logic level 1 or
0. Their output cells will be set to hi-z. In 1.src,
the use of #netlist get1 is for a BSC pin with
external pull up resistor.
● #netlist put1 (or put0) line defines one or more
BSC dev/pin names, listed in netlist file, will
drive their output cells fixed logic level 1 or 0.
In the meantime, the input cells will validate
their output cell logic levels.

16. Test Generation (1)
● Test setup file 1.src will be processed by ATPG
parser, which in turn will invoke bsdl parser and
netlist parser to scan over the bsdl and netlist
files specified.
● 3 text files will be created: 1.lst, 1_bsdl.lst, and
1_netlist.lst. If the ATPG process is
successfully done, it will produce 2 binary
output files: 1.bin and 1_bsdl.bin for later test
execution.

17. Test Generation (2)
● 1_netlist.lst lists BSC pins within netlist file
which will be incorporated in the test
generation. They will be further classified into
(1) tied to DGT pins as defined in pindef (2)
hardwired to power rail or ground plane (3)
setup to get0, get1, put0, put1 (4) normal BST
pins.
● Groups (1) and (4) are divided into test groups
in which single BSC IC or DGT serves as test
driver with one or more BSC IC / DGT serves
as test receivers.

18. Test Generation (3)
● Following page shows partial screen of test
groups at the end of 1_netlist.lst.
● Test groups for BSC only (normal) pins (no
DGT connection) will have 1 test driver and 1
test receiver.
● The last test group has U3 BSC output cells as
test driver with its BSC input cells and DGT pins
as test receiver.

19. Test Generation (4)

20. Running Tests (1)
● LE1210 will run test vectors using binary files
created by pindef and Test Generator. These
include pindef.bin, 1.bin, and 1_bsdl.bin.
● Test output files include sysout text file, sysout
csv file, and the csv files for each of the BSC
devices in the DUT. Those file names are time-
stamped to prevent files from been overwritten.
● Tests will be executed with and without the fault
inserted. Excerpts of test trace files for those
tests will be depicted.

21. Running Tests (2)
● First test vector will be DGT driving fixed logic
toward DUT for those use pindef in fixed logic.
● Second DGT vector will validate the DUT fixed
logic states defined in pindef out fixed logic.
● Starting test vector #3 will be alternating DGT
and BST test vectors in which BST and DGT
are cross checking each other's driving data.
● Iterations of DGT and BST will use walking-1
test patterns to ensure open/short fault
detections.

22. Running Tests (3)
● Test vector #4 also starts fixed BSC pin drive
and validation logic states defined in Test
Generation setup file get0/get1/put0/put1 lines.
● LE1210 test output csv files conventions are
that signals driving into DUT are listed as 0/1/Z,
and the signals detected from DUT are L/H/X.
● The BSC pins not participating in test activities
are (1) not listed in Netlist file (2) device not
included in #bsc device chain (3) bypassed in
test generation (4) not properly equipped with
BSC input or output cells.

23. sysout-csv (1)

24. sysout-csv (2)
● Vector 1-2: for DGT pins 129-136, DUT out pins
are in X states (don't care) due to unknown
driving BSC output cells states.
● Vector 3, no DGT pin is driving toward DUT.
DGT pins 129-136 are still in X states.
● Vector 5, DGT pins 129-136 are detecting BSC
pins u3.84-u3.75 output cells signals in vector
4. Similarly, vector 7 DGT pins are receiving
BST driving signals in vector 6, … .
● Test passed without showing “failed” state.

25. u3-csv (1)

26. u3-csv (2)
● Test group, U3-p75 to U3-p84, with U3-p79 as
LSB will drive walking-1 test pattern starting
vector #4. Test validation are done by DGT in
vector #5 (pin 129-136) and BST in vector #6
(their input cells).
● Simultaneously in vector #6, output cells of the
same test group will drive 'shift-left' data. They
will be validated by DGT in vector #7 and BST
in vector #8.

27. u2-csv (1)

28. u2-csv (2)
● U2 pins p75 to p84 do not have connections to
the DGT pins.
● Each of those U2 pins output cells driving data
will be validated only by its own input cell in the
follow on BST test vector.
● Vector #4, u2-p78 output cell driving data
(spreadsheet column FQ) will be validated by
its input cell(spreadsheet column FP) in vector
#6. Vector #6, u2-p78 output cell driving data is
validated by its input cell in vector #8.

29. u2-csv (3)

30. u2-csv (4)
● Previous page shows BSC cells of u2-p43 to
u2-p47 are having their output cells put to hi-z
state while their input cells put to X state – don't
care.
● In netlist file, u2.43 and u3.43 share the same
node. With u3.43 defined to be bypass in the
test generation setup file, it results in bypassing
u2.43.

31. Fault Insertion Test (1)
● Ground wire will be connected to DGT pin #129
and repeat the previous test. The excerpts of
trace files are pictured in P32 and P33.
● Sysout csv file shows DGT failed when
detecting logic state L in DGT pin #129, vector
11, 27 and 43(not shown).
● BSC device U3 didn't fail the test on its pin #84.
This pin is isolated from DGT pin #129 with a
buffer circuit. Its input cell (highlighted) detects
valid logic state H in vector 12, 28, and 44.

32. Fault Insertion Test (2)

33. Fault Insertion Test (3)