Deviprasad Shetty has over 1.6 years of experience in PCIe IP level verification. He has worked as a contractor for LSI and as a project intern at LSI R&D India. He is proficient in Verilog HDL, Specman E, and has knowledge of PCIe protocols. His education includes an MSc.Tech in VLSI Design from MCIS Manipal and a BE in Electronics and Communication. His projects include PCIe controller verification using Specman and asynchronous FIFO design and verification.

1. DEVIPRASAD SHETTY S. Mobile No: 8762119561
Email: devipdshetty@gmail.com
Career Summary & Experience:
 1.6 years of Experience on PCIe IP level verification.
 Working for Techvulcan as associate engineer from last 8 month(july 2014 –present).
 Worked as contractor for LSI, An Avago Technologies company for 6 months(july 2014 –
jan 2015) on PCIe GEN3 controller verification
 Worked as a PROJECT INTERN at LSI R&D India Pvt Ltd. Bangalore from July 2013 to
July 2014
 Proficient in Hardware Verification Languages such as Verilog HDL and Specman E ,
system Verilog(learning)
 Good PCI-Express Transaction and Link layers protocol knowledge
 Hands on experience on PCIe protocol verification with excellent debug skills
Education Details:
• MSc.Tech in VLSI-DESIGN from MCIS Manipal. Affiliated to Manipal University
Manipal Karnataka with aggregate marks 9.01/10(CGPA) in JULY 2014.
• BE in Electronics & Communication (ECE) from EAST POINT COLLEGE
ENGINEERING TECHNOLOGY, Karnataka. Affiliated to Visveswaraiah Technological
University (VTU), Belgaum with aggregate marks 76.20% in June 2011.

2. Project Details:
Project 1: PCIe Controller(Transaction Layer) verification using specman environment
Team Size: 3 Engineers
Company: LSI R&D India Pvt Ltd . Bangalore
Duration: JULY 2013 to JULY 2014.
Operating System: Unix.
Tools & Language: VCS, Specman E.
Project Description: Aim of this project is to verify PCIe controller, Pcie controller consists of
Transaction Layer and Data Link layer. Subsystem level consists of PIPE and SerDes, this is Black box
for Verification. Denali VIP is used for this project.
Responsibilities:
• Completion handling feature verification.
• Credit based feature verification.
• L0s and L1 feature verification
• AHB read and write verification attribute checking of register field
• Ordering rules of PCIe verification.
Project 2: PCIe Controller verification (Link Verification) using Specman environment
Team Size: 3 Engineers
Company: LSI R&D India Pvt Ltd . Bangalore
Duration: AUG 2014 to jan 2015.
Operating System: Unix.
Tools & Language: VCS, Specman E.
Project Description: This project is focused on Link layer verification in Specman environment as part
of PCIe controller IP development.
Responsibilities:
• LTSSM Transition like Polling compliance Loop back feature verification.
• Disable hot reset state transition verification
• PPM variation verification
Project 3: Asynchronous FIFO Design and Verification.
Team Size: 2
Company: Academic project at MCIS Manipal
Duration: August 2012 to December 2012.
Operating System: Unix.
Tools & Language: VCS and Verilog
Project Description: Aim of this project is to design synchronous FIFO with Asynchronous Comparison
this project goals to achieve synthesizable FIFO design and verifying design using normal Verilog test
bench.
Responsibilities:
• Synthesized design using Design Compiler.
• Verilog test bench written to verify design.

3. Project 4: TIME BASED ADC FOR LOW VOLTAGE
Team Size: 2 Engineers
Company: Academic project at MCIS Manipal
Duration: January 2013 to June 2013.
Operating System: Unix
Tools & Language: VIRTUOSO, VCS
Project Description: ADC is very important component of the any communication system, Designing of
the ADC should consider area and power consideration. In this project converting the voltage signal to
time signal (pulse) using pulse coding modulation. This time signal is converted into the digital signal using
(TDC) time to digital converter
Responsibilities:
• Developing schematic using VIRTUOSO tool and verifying design.
• Writing small Verilog code for TDC.
• Integrating digital module and analog module checking simulation for expected result.
Project 5: VIRTUAL KEYBOARD
Team Size: 4 Engineers
Company: Academic project for East Point College of engineering and technology
Duration: JAN 2011 to May 2011.
Operating System: Windows.
Tools & Language: ALP
Project Description: Virtual keyboard is just another example of today’s computer trend of smaller and
faster. And for this we have come forward this solution, in this project we are demonstrating an emerging
technology in which bulky keyboard replaces by virtual keyboard. The virtual keyboard has two main
component camera, printed paper. CMOS camera capture finger passes through printed paper and
transmits to AVR similar processor and then after processing we get output which key pressed
Technical Skills:
Hardware Description Language : Verilog HDL
Hardware Verification Language : Specman-E, System Verilog
Protocols : PCI-Express
Operating System : Windows Family, Unix
EDA Tools : Synopsys-VCS, specman.
Contact Details:
Mobile No : +91 8762119561
Email : devipdshetty@gmail.com
Place : Bangalore