radix_4 fft processor can be determine to creating for four channel and if it is from how moving the data from one stage to another stage and how get correct output equal to input. the main advantage:creating for multiple channel from group of channel and analysis how moving of data from stage by stage, increasing for data processing speed,

1. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fft is
Port ( S : inout STD_LOGIC_VECTOR(15 downto 0);
Y : out STD_LOGIC_VECTOR(15 downto 0);
g : inout STD_LOGIC_VECTOR (15 downto 0);
w : inout STD_LOGIC_VECTOR (15 downto 0));
end fft;
package fft_pkg is
type std_logic is
record
r:real;
i:real;
end record;
type std_logic_vectoris array (15 downto 0) of std_logic;
type real is array (15 downto 0) of std_logic;
function add01 (n4,n8:in std_logic)return std_logic;
function add02 (n1,n13:in std_logic)return std_logic;
function add03 (n5,n9:in std_logic)return std_logic;
function add04 (n2,n14:in std_logic)return std_logic;
function add05 (n6,n10:in std_logic)return std_logic;
function add06 (n3,n15:in std_logic)return std_logic;

2. function add07 (n7,n11:in std_logic)return std_logic;
function sub10 (n0,n12:in std_logic)return std_logic;
function sub11 (n4,n8:in std_logic)return std_logic;
function sub12 (n1,n13:in std_logic)return std_logic;
function sub13 (n5,n9:in std_logic)return std_logic;
function sub14 (n2,n14:in std_logic)return std_logic;
function sub15 (n6,n10:in std_logic)return std_logic;
function sub16 (n3,n15:in std_logic)return std_logic;
function sub17 (n7,n11:in std_logic)return std_logic;
function mult20 (n0,n3:in std_logic)return std_logic;
function mult21 (n1,n2:in std_logic)return std_logic;
function mult22 (n4,n7:in std_logic)return std_logic;
function mult23 (n5,n6:in std_logic)return std_logic;
function mult24 (n8,n11:in std_logic)return std_logic;
function mult25 (n9,n10:in std_logic)return std_logic;
function mult26 (n12,n15:in std_logic)return std_logic;
function mult27 (n13,n14:in std_logic)return std_logic;
function add30 (n0,n12,n4,n8:in std_logic)return std_logic;
function add31 (n1,n13,n5,n9:in std_logic)return std_logic;
function add32 (n2,n14,n6,n10:in std_logic)return std_logic;
function add33 (n3,n15,n7,n11:in std_logic)return std_logic;
function sub40 (n0,n12,n4,n8:in std_logic)return std_logic;
function sub41 (n1,n13,n5,n9:in std_logic)return std_logic;
function sub42 (n2,n14,n6,n10:in std_logic)return std_logic;

3. function sub43 (n3,n15,n7,n11:in std_logic)return std_logic;
function mult50 (n0,n12,n4,n8:in std_logic)return std_logic;
function mult51 (n1,n13,n5,n9:in std_logic)return std_logic;
function mult52 (n2,n14,n6,n10:in std_logic)return std_logic;
function mult53 (n3,n15,n7,n11:in std_logic)return std_logic;
end fft_pkg;
package bodyfft_pkg is
function add00(n0,n12:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n0.r+n12.r;
sum.i:=n0.i+n12.i;
return sum;
end add00;
function add01 (n4,n8:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n4.r+n8.r;
sum.i:=n4.i+n8.i;
return sum;
end add01;
function add02 (n1,n13:in std_logic)return std_logic is
variable sum:std_logic;
begin

4. sum.r:=n1.r+n13.r;
sum.i:=n1.i+n13.i;
return sum;
end add02;
function add03 (n5,n9:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n5.r+n9.r;
sum.i:=n5.i+n9.i;
return sum;
end add03;
function add04 (n2,n14:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n2.r+n14.r;
sum.i:=n2.i+n14.i;
return sum;
end add04;
function add05 (n6,n10:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n6.r+n10.r;
sum.i:=n6.i+n10.i;
return sum;

5. end add05;
function add06 (n3,n15:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n3.r+n15.r;
sum.i:=n3.i+n15.i;
return sum;
end add06;
function add07 (n7,n11:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n7.r+n11.r;
sum.i:=n7.i+n11.i;
return sum;
end add07;
function sub10 (n0,n12:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n0.r-n12.r;
diff.i:=n0.i-n12.i;
return diff;
end sub10;
function sub11 (n4,n8:in std_logic)return std_logic is
variable diff:std_logic;

6. begin
diff.r:=n4.r-n8.r;
diff.i:=n4.i-n8.i;
return diff;
end sub11;
function sub12 (n1,n13:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n1.r-n13.r;
diff.i:=n1.i-n13.i;
return diff;
end sub12;
function sub13 (n5,n9:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n5.r-n9.r;
diff.i:=n5.i-n9.i;
return diff;
end sub13;
function sub14 (n2,n14:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n2.r-n14.r;
diff.i:=n2.i-n14.i;

7. return diff;
end sub14;
function sub15 (n6,n10:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n6.r-n10.r;
diff.i:=n6.i-n10.i;
return diff;
end sub15;
function sub16 (n3,n15:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n3.r-n15.r;
diff.i:=n3.i-n15.i;
return diff;
end sub16;
function sub17 (n7,n11:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n7.r-n11.r;
Diff.i:=n7.i-n11.i;
return diff;
end sub17;
function mult20 (n0,n3:in std_logic)return std_logic is

8. variable prod:std_logic;
begin
prod.r:=(n0.r*n3.r)-(n0.i*n3.i);
prod.i:=(n0.i*n3.i)+(n0.i*n3.i);
return prod;
end mult20;
function mult21 (n1,n2:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n1.r*n2.r)-(n1.i*n2.i);
prod.i:=(n1.i*n2.i)+(n1.r*n2.r);
return prod;
end mult21;
function mult22 (n4,n7:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n4.r*n7.r)-(n4.i*n7.i);
prod.i:=(n4.i*n7.i)+(n4.r*n7.r);
return prod;
end mult22;
function mult23 (n5,n6:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n5.r*n6.r)-(n5.i*n6.i);

9. prod.i:=(n5.i*n6.i)+(n5.i*n6.i);
return prod;
end mult23;
function mult24 (n8,n11:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n8.r*n11.r)-(n8.i*n11.i);
prod.i:=(n8.i*n11.i)+(n8.r*n11.r);
return prod;
end mult24;
function mult25 (n9,n10:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n9.r*n10.r)-(n9.i*n10.i);
prod.i:=(n9.i*n10.i)+(n9.r*n10.r);
return prod;
end mult25;
function mult26 (n12,n15:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n12.r*n15.r)-(n12.i*n15.i);
prod.i:=(n12.i*n15.i)+(n12.r*n15.r);
return prod;
end mult26;

10. function mult27 (n13,n14:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n13.r*n14.r)-(n13.i*n14.i);
prod.i:=(n13.i*n14.i)+(n13.r*n14.r);
return prod;
end mult27;
function add30 (n0,n12,n4,n8:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.i:=n0.i+n12.i+n4.i+n8.i;
sum.r:=n0.r+n12.r+n4.r+n8.r;
return sum;
end add30;
function add31 (n1,n13,n5,n9:in std_logic)return std_logic is
variable sum:std_logic;
begin
sum.r:=n1.r+n13.r+n5.r+n9.r;
sum.i:=n1.i+n13.i+n5.i+n9.i;
return sum;
end add31;
function add32 (n2,n14,n6,n10:in std_logic)return std_logic is
variable sum:std_logic;
begin

11. sum.r:=n2.r+n14.r+n6.r+n10.r;
sum.i:=n2.i+n14.i+n6.i+n10.i;
return sum;
end add32;
function add33 (n3,n15,n7,n11:in std_logic)return std_logic is
variable sum: std_logic;
begin
sum.r:=n3.r+n15.r+n7.r+n11.r;
sum.i:=n3.i+n15.i+n7.i+n11.i;
return sum;
end add33;
function sub40 (n0,n12,n4,n8:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n0.r-n12.r-n4.r-n8.r;
diff.i:=n0.i-n12.i-n4.i-n8.i;
return diff;
end sub40;
function sub41 (n1,n13,n5,n9:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n1.r-n13.r-n5.r-n9.r;
diff.i:=n1.i-n13.i-n5.i-n9.i;
return diff;

12. end sub41;
function sub42 (n2,n14,n6,n10:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n2.r-n14.r-n6.r-n10.r;
diff.i:=n2.i-n14.i-n6.i-n10.i;
return diff;
end sub42;
function sub43 (n3,n15,n7,n11:in std_logic)return std_logic is
variable diff:std_logic;
begin
diff.r:=n3.r-n15.r-n7.r-n11.r;
diff.i:=n3.i-n15.i-n7.i-n11.i;
return diff;
end sub43;
function mult50 (n0,n12,n4,n8:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n0.r*n12.r*n4.r*n8.r)-(n0.i*n12.i*n4.i*n8.i);
prod.i:=(n0.i*n12.i*n4.i*n8.i)+(n0.r*n12.r*n4.r*n8.r);
return prod;
end mult50;
function mult51(n1,n13,n5,n9:in std_logic)return std_logic is
variable prod:std_logic;

13. begin
prod.r:=(n1.r*n13.r*n5.r*n9.r)-(n1.i*n13.i*n5.i*n9.i);
prod.i:=(n1.i*n13.i*n5.i*n9.i)+(n1.r*n13.r*n5.r*n9.r);
return prod;
end mult51;
function mult52 (n2,n14,n6,n10:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.i:=(n2.i*n14.i*n6.i*n10.i)+(n2.r*n14.r*n6.r*n10.r);
prod.r:=(n2.r*n14.r*n6.r*n10.r)-(n2.i*n14.i*n6.i*n10.i);
return prod;
end mult52;
function mult53 (n3,n15,n7,n11:in std_logic)return std_logic is
variable prod:std_logic;
begin
prod.r:=(n3.r*n15.r*n7.r*n11.r)-(n3.i*n15.i*n7.i*n11.i);
prod.i:=(n3.i*n15.i*n7.i*n11.i)+(n3.r*n15.r*n7.r*n11.r);
return prod;
end mult53;
end package bodyfft_pkg;
architecture Behavioral of fft is
component std_logic_1is
port(
S0,S12:in std_logic;

14. w0,w1: in std_logic;
g0,g1: in std_logic
);
end component std_logic_1;
component std_logic_2 is
port(
S4,S8:in std_logic;
w2,w3:in std_logic;
g2,g3:in std_logic
);
end component std_logic_2;
component std_logic_3 is
port(
S1,S13:in std_logic;
w4,w5:in std_logic;
g4,g5:in std_logic
);
end component std_logic_3;
component std_logic_4 is
port(
S5,S9:in std_logic;
w6,w7: in std_logic;
g6,g7:in std_logic
);

15. end component std_logic_4;
component std_logic_5 is
port(
S2,S14:in std_logic;
w8,w9: in std_logic;
g8,g9:in std_logic
);
end component std_logic_5;
component std_logic_6 is
port(
S6,S10:in std_logic;
w10,w11:in std_logic;
g10,g11:in std_logic
);
end component std_logic_6;
component std_logic_7 is
port(
S3,S15:in std_logic;
w12,w13:in std_logic;
g12,g13:in std_logic
);
end component std_logic_7;
component std_logic_8 is
port(

16. S7,S11:in std_logic;
w14,w15:in std_logic;
g14,g15:in std_logic
);
end component std_logic_8;
component std_logic_11 is
port(
g0,g3:in std_logic;
w0,w3:in std_logic;
Y0,Y1:out std_logic
);
end component std_logic_11;
component std_logic_12 is
port(
g1,g2:in std_logic;
w1,w2:in std_logic;
Y2,Y3:out std_logic
);
end component std_logic_12;
component std_logic_13 is
port(
g4,g7:in std_logic;
w4,w7:in std_logic;
Y4,Y5:out std_logic

17. );
end component std_logic_13;
component std_logic_14 is
port(
g5,g6:in std_logic;
w5,w6:in std_logic;
Y6,Y7:out std_logic
);
end component std_logic_14;
component std_logic_15 is
port(
g8,g11:in std_logic;
w8,w11:in std_logic;
Y8,Y9:out std_logic
);
end component std_logic_15;
component std_logic_16 is
port(
g9,g10:in std_logic;
w9,w10:in std_logic;
Y10,Y11:out std_logic
);
end component std_logic_16;
component std_logic_17 is

18. port(
g12,g15:in std_logic;
w12,w15:in std_logic;
Y12,Y13:out std_logic
);
end component std_logic_17;
component std_logic_18 is
port(
g13,g14:in std_logic;
w13,w14:out std_logic;
Y14,Y15:out std_logic
);
end component std_logic_18;
-------------------------------------starting for bit reversal---------------
component bitreversal_20 is
port(
S0,S12,S4,S8:inout std_logic;
g0,g1,g2,g3:inout std_logic;
w0,w1,w2,w3:inout std_logic
);
end component bitreversal_20;
component bitreversal_21 is
port(
S1,S13,S5,S9:inout std_logic;

19. g4,g5,g6,g7:inout std_logic;
w4,w5,w6,w7:inout std_logic
);
end component bitreversal_21;
component bitreversal_22 is
port(
S2,S14,S6,S10:inout std_logic;
g8,g9,g10,g11:inout std_logic;
w8,w9,w10,w11:inout std_logic
);
end component bitreversal_22;
component bitreversal_23 is
port(
S3,S15,S7,S11:inout std_logic;
g12,g13,g14,g15:inout std_logic;
w12,w13,w14,w15:inout std_logic
);
end componentbitreversal_23;
component bitreversal_24 is
port(
g0,g3,g1,g2:inout std_logic;
w0,w3,w1,w2:inout std_logic;
Y0,Y1,Y2,Y3:out std_logic
);

20. end componentbitreversal_24;
component bitreversal_25 is
port(
g4,g7,g5,g6:inout std_logic;
w4,w7,w5,w6:inout std_logic;
Y4,Y5,Y6,Y7:out std_logic
);
end componentbitreversal_25;
component bitreversal_26 is
port(
g8,g11,g9,g10:inout std_logic;
w8,w11,w9,w10:inout std_logic;
Y8,Y9,Y10,Y11:out std_logic
);
end componentbitreversal_26;
component bitreversal_27 is
port(
g12,g15,g13,g14:inout std_logic;
w12,w15,w13,w14:inout std_logic;
Y12,Y13,Y14,Y15:out std_logic
);
end componentbitreversal_27;
signal g0,g1:std_logic_vector(1 downto 0);
signal g2,g3:std_logic_vector(3 downto 2);

21. signal g4,g5:std_logic_vector( 5 downto 4);
signal g6,g7:std_logic_vector( 7 downto 6 );
signal g8,g9:std_logic_vector(09 downto 8);
signal g10,g11:std_logic_vector(11 downto 10);
signal g12,g13:std_logic_vector(13 downto 12);
signal g14,g15:std_logic_vector(15 downto 14);
constant w0:real:=0.0000002;
constant w1:real:=0.0000002;
constant w2,w3:real:=0.7376;
constant w4:real:=1.3452666;
constant w5:real:=1.3452666;
constant w6:real:=1.70677737;
constant w7:real:=1.70677737;
constant w8:real:=0.7008;
constant w9:real:=0.7008;
constant w10:real:=0.13425;
constant w11:real:=0.13425;
constant w12:real:=0.4354636;
constant w13:real:=0.4354636;
constant w14:real:=5.6768888;
constant w15:real:=5.6768888;
begin
---------------first stage butterfly 's---------------------
sl_1:std_logic_1 port map (S(0),S(12),w(0),w(1),g(0),g(1));

22. sl_2:std_logic_2 port map (S(4),S(8),w(2),w(3),g(2),g(3));
sl_3:std_logic_3 port map (S(1),S(13),w(4),w(5),g(4),g(5));
sl_4:std_logic_4 port map (S(5),S(9),w(6),w(7),g(6),g(7));
sl_5:std_logic_5 port map (S(2),S(14),w(8),w(9),g(8),g(9));
sl_6:std_logic_6 port map (S(6),S(10),w(10),w(11),g(10),g(11));
sl_7:std_logic_7 port map (S(3),S(15),w(12),w(13),g(12),g(13));
sl_8:std_logic_8 port map (S(7),S(11),w(14),W(15),g(14),g(15));
----second stage butterfly's----
sl_11:std_logic_11 port map (g(0),g(3),w(0),w(3),Y(0),Y(1));
sl_12:std_logic_12 port map (g(1),g(2),w(1),w(2),Y(2),Y(3));
sl_13:std_logic_13 port map (g(4),g(7),w(4),w(7),Y(4),Y(5));
sl_14:std_logic_14 port map (g(5),g(6),w(5),w(6),Y(6),Y(7));
sl_15:std_logic_15 port map (g(8),g(11),w(8),w(11),Y(8),Y(9));
sl_16:std_logic_16 port map (g(9),g(10),w(9),w(10),Y(10),Y(11));
sl_17:std_logic_17 port map (g(12),g(15),w(12),w(15),Y(12),Y(13));
sl_18:std_logic_18 port map (g(13),g(14),w(13),w(14),Y(14),Y(15));
--------- first stage bit reversal part of the butterfly'S --------------------
complex_000:bitreversal_20 port map
(S(0),S(12),S(4),S(8),w(0),w(1),w(2),w(3),g(0),g(1),g(2),g(3));
complex_001:bitreversal_21 port map
(S(1),S(13),S(5),S(9),w(4),w(5),w(6),w(7),g(4),g(5),g(6),g(7));
complex_002:bitreversal_22 port map
(S(2),S(14),S(6),S(10),w(8),w(9),w(10),w(11),g(8),g(9),g(10),g(11));
complex_003:bitreversal_23 port map
(S(3),S(15),S(7),S(11),w(12),w(13),w(14),w(15),g(12),g(13),g(14),g(15));

23. ----------------first stage bit reversal part of the butterfly''S-----------------------
complex_004:bitreversal_24 port map
(g(0),g(3),g(1),g(2),w(0),w(3),w(1),w(2),Y(0),Y(1),Y(2),Y(3));
complex_005:bitreversal_25 port map
(g(4),g(7),g(5),g(6),w(4),w(7),w(5),w(6),Y(4),Y(5),Y(6),Y(7));
complex_006:bitreversal_26 port map
(g(8),g(11),g(9),g(10),w(8),w(11),w(9),w(10),Y(8),Y(9),Y(10),Y(11));
complex_007:bitreversal_27 port map
(g(12),g(15),g(13),g(14),w(12),w(15),w(13),w(14),Y(12),Y(13),Y(14),Y(15));
end Behavioral;