Electrónica Digital con VHDL

1. Practica #7 – Memorias 115 de Noviembre de 2017
TECNOLÓGICO NACIONAL DE
MÉXICO
Instituto Tecnológico de matamoros
Diseño digital con VHDL
Memorias
Ing. Electrónica
Practica #7
Nombre(s) de alumno(s): Núm. de control:
Joel ivan teran ramirez ……………………………………………………15260142
Santiago pablo Alberto...…………………………………………………..15260092
Jesus Alberto medrano Ortiz …………...…………………………………15260147
Edgar Oziel Olvera rivera……….…………….…………………………...15260128
Profesor: Arturo Rdz. Casas
H. MATAMOROS,TAM. 15 de Noviembre 2017

2. Practica #7 – Memorias 215 de Noviembre de 2017
Objetivos:
·. El objetivo de la realización de esta práctica es implementar un código vhdl con el cual
se pueda controlar la salida de la suma de dos memorias diseñadas.
Material:
- ISE WebPack
- Board BASYS2.
Desarrollo
1.- Escriba un codigo en VHDL que desarrolle la siguiente funcion, los datos de ROM1 y
ROM2 son sumados y el resultado es almacenado en la memoria RAM. Primero se deben
de disenar cada modulo y despues todos los modulos usando las tecnicas de diseno de
“port map”.
2. En base a lo anterior. Implementar el siguiente código:
Top
libraryIEEE;
use IEEE.STD_LOGIC_1164.ALL;
entityTopis
Port ( Clock: in STD_LOGIC;
Addres: in STD_LOGIC_VECTOR(1 downto0);
Upload: in STD_LOGIC;
Add : in STD_LOGIC;

3. Practica #7 – Memorias 315 de Noviembre de 2017
Show: in STD_LOGIC;
Data_Out : out STD_LOGIC_VECTOR(7 downto0));
endTop;
architecture Behavioral of Topis
componentROMis
port(
Clk : instd_logic;
Rd : instd_logic;
Addr : in std_logic_vector(1downto0);
S : outstd_logic_vector(7downto0));
endcomponent;
componentRAMis
port( Clk,Wt,Rd :instd_logic;
Addr: in std_logic_vector(1downto0);
S: out std_logic_vector(7downto0);
E: in std_logic_vector(7downto0));
endcomponent;
componentSUMis
Port ( A : in STD_LOGIC_VECTOR (7 downto0);
B : in STD_LOGIC_VECTOR (7 downto0);
Upload : in STD_LOGIC;
Add : in STD_LOGIC;
X : out STD_LOGIC_VECTOR (7 downto0));
endcomponent;
Signal a,b, x : STD_LOGIC_VECTOR(7 downto0);
begin
U1 : ROM
port map(
Clk=> Clock,

4. Practica #7 – Memorias 415 de Noviembre de 2017
Rd => Upload,
Addr=> Addres,
S => a);
U2 : ROM
port map(
Clk=> Clock,
Rd => Upload,
Addr=> Addres,
S => b);
U3 : SUM
port map(
A => a,
B => b,
Upload=> Upload,
Add=> Add,
X => x );
U4 : RAM
port map(
Clk=> Clock,
Wt => Add,
Rd => Show,
Addr=> Addres,
S => Data_Out ,
E => x );
endBehavioral;
U1 ROM
libraryIEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;
entityROMis
port(
Clk : instd_logic;
Rd : instd_logic;
Addr : in std_logic_vector(1downto0);
S : outstd_logic_vector(7downto0));
endROM;
architecture Behavioral of ROMis
type ROM_Array is array (0 to 3)of std_logic_vector(7downto0);
constantContent:ROM_Array := (
0 => "00000001", -- value inROMat location0H
1 => "00000010", -- value inROMat location1H
2 => "00000011", -- value inROMat location2H
3 => "00000100", -- value inROM at location3H
OTHERS => "11111111");
begin
process(Clk)--,Read,Address)
begin
if( Clk'eventandClk= '0' ) then
if( Rd= '1' ) then
S <= Content(conv_integer(Addr));
else
S <= "ZZZZZZZZ";
endif;
endif;
endprocess;
endBehavioral;

6. Practica #7 – Memorias 615 de Noviembre de 2017
U2 ROM
libraryIEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entityROMis
port(
Clk : instd_logic;
Rd : instd_logic;
Addr : in std_logic_vector(1downto0);
S : outstd_logic_vector(7downto0));
endROM;
architecture Behavioral of ROMis
type ROM_Array is array (0 to 3)of std_logic_vector(7downto0);
constantContent:ROM_Array := (
0 => "00000001", -- value inROMat location0H
1 => "00000010", -- value inROMat location1H
2 => "00000011", -- value inROMat location2H
3 => "00000100", -- value inROM at location3H
OTHERS => "11111111");
begin
process(Clk)--,Read,Address)
begin
if( Clk'eventandClk= '0' ) then
if( Rd= '1' ) then
S <= Content(conv_integer(Addr));
else
S <= "ZZZZZZZZ";
endif;

7. Practica #7 – Memorias 715 de Noviembre de 2017
endif;
endprocess;
endBehavioral;
SUM
libraryIEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entitySUMis
Port ( A : in STD_LOGIC_VECTOR (7 downto0);
B : in STD_LOGIC_VECTOR(7 downto0);
Upload: in STD_LOGIC;
Add: in STD_LOGIC;
X : out STD_LOGIC_VECTOR(7 downto0));
endSUM;
architecture Behavioral of SUMis
signal Num1,Num2: std_logic_vector(7downto0);
begin
process(Upload,Add)
begin
if Upload= '1' then
Num1 <= A;
Num2 <= B;
elsif Add='1' then
X <= ( Num1+ Num2);
endif;
endprocess;
endBehavioral;

8. Practica #7 – Memorias 815 de Noviembre de 2017
RAM
libraryIEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entityRAMis
port( Clk,Wt,Rd :instd_logic;
Addr: in std_logic_vector(1downto0);
S: out std_logic_vector(7downto0);
E: in std_logic_vector(7downto0));
endRAM;
architecture Behavioral of RAMis
type ram_type isarray (0 to 3) of std_logic_vector(7downto0);
signal tmp_ram:ram_type;
begin
process(Clk)
begin
if (Clk'eventandClk='1') then
if Wt='1' then
tmp_ram(conv_integer(Addr)) <=E; --write
s <= "ZZZZZZZZ";
elsif Rd= '1' then
s <= tmp_ram(conv_integer(Addr));
else
s<= "ZZZZZZZZ";
endif;
endif;
endprocess;
endBehavioral;

9. Practica #7 – Memorias 915 de Noviembre de 2017
UCF
NET "Clock"LOC = "B8";
NET "Addres<0>"LOC = "P11";
NET "Addres<1>"LOC = "L3";
NET "Upload"LOC = "N3";
NET "Add"LOC = "E2";
NET "Show"LOC = "F3";
NET "Data_Out<0>" LOC = "M5";
NET "Data_Out<1>" LOC = "M11";
NET "Data_Out<2>" LOC = "P7";
NET "Data_Out<3>" LOC = "P6";
NET "Data_Out<4>" LOC = "N5";
NET "Data_Out<5>" LOC = "N4";
NET "Data_Out<6>" LOC = "P4";
NET "Data_Out<7>" LOC = "G1";
NET "Upload"CLOCK_DEDICATED_ROUTE = FALSE;
3. Implemente el código VHDL en el board Basys 2.
Análisis de resultados y conclusiones
Se concluyó de forma correcta la práctica desarrollando nuevas formas de poner en
práctica los conocimientos adquiridos al igual de los diferentes usos que se le pueden dar
al programador BASYS 2 por medio de memorias.