This document describes a single cycle processor implemented in Verilog that executes instructions in one clock cycle. It includes a register file to store data, an program counter (PC) to track the next instruction address, a controller to decode instructions and control operations, an arithmetic logic unit (ALU) to perform arithmetic and logical operations on data, and a memory to store and retrieve data. The processor supports load, store, add, and, or, subtract, set on less than, and branch equal instructions operating on 32-bit data words through its register ports, ALU, and memory components controlled by the single cycle controller.

1. SINGLE CYCLE
PROCESSORVerilog implementation

2. • This processor executes each instruction in one clock cycle only.
• Compatible operations:
IType:
Load word
Store word
RType:
Add
And
Or
Subtract
SLT
JType
Beq

3. Register
• It takes the data addresses from instruction memory in order to
fetch the data which is already saved in it and/or write the data from
the data memory in a certain address. then save it in memory .
• Data is read through 2 32bit output ports for further operation.
• The Data required to be loaded onto the register is fed through 32
bit input port.

4. Register code

5. PC
• A program counter that compute the address of the next
instruction and pass it to the instruction memory which read that
address and pass the corresponding data to the register.
• The address of the next instruction is calculated by incrementing
the current by 4 since we deal with words (32 bit )instruction, while
the memory is byte addressable.

6. PC code

7. Controller
• It force some values for every instruction to control ALU and make
operations on data.
• It is divided into two modules:
 controller which detects R , I and J types and sends signals accordingly
ALU control which determines which R type instruction received

8. Controller code
Determines I type instructions Load word, Store word, Branch equal
and Jump instructions and gives outputs
The R type is determined and gives ALUop as an output which is not
00 or 01
Outputs from Controller: RegDst, Jump, Branch, MemRead,
MemToReg, MemWrite, ALUsrc, RegWrite and ALUop

9. Controller Truth Table

10. ALU Control
• Determines the R type instructions which areAdd, Subtract, And,
Or

11. ALU
• ALU takes 2 input data from register and check the operation from ALU
control and then generate a result and send it to memory (LW/SW) or the
register (R).
ALU control Function
000 AND
001 OR
010 ADD
110 SUBTRACT
111 Set on Less Than

12. ALU code

13. Memory
• Memory receives data address from ALU to save data in it then it
waits for an input to write data or read data.
• If read it will write data on register.

14. Memory code

15. Generic modules
Mux 32bit
Mux 5 bit
Adder
Shift left by 2
Sign extension
And gate

16. Data top module

17. Main top module

18. Simulation screenshots
• add

19. • Subtract
Zero flag
Simulation screenshots (cont’d)

20. Simulation screenshots (cont’d)
• and

21. • Or
Simulation screenshots (cont’d)

22. • Slt true
Simulation screenshots (cont’d)

23. • Slt false
Simulation screenshots (cont’d)

24. RTL Schematic