This document discusses signals and variables in VHDL. It defines signals as being used to pass values between circuits and components, while variables represent local information that can only be used within processes. Signals are updated at the end of processes while variables are updated immediately. Examples are given to demonstrate using signals for counters and how signals and variables differ in terms of assignment, scope, and timing of updates. The document concludes by explaining how the number of flip-flops required can differ depending on whether outputs are assigned to signals or variables.

1. Andrés Rincón
Ángela Pedraza
Sistemas Digitales I
Integration of entities in
VHDL

2. Introduction
• One of the strengths of VHDL is the ease of
integrating " digital systems " containing a large
number of electronic subsystems in order to minimize
the size of the application.
• The integration of entities can be done by the
individual design of each logical block through various
internal processes that can later be joined by a
common program

3. SIGNAL y VARIABLES
• VHDL provides two objects to work with non- static data values ​​: signals and variables.
• A variable is local, used only in sequential codes : processes
• SIGNAL
• A signal is used to pass values ​​input or output of a circuit, and between their internal
drives.
• Sintaxis:
• SIGNAL name : type [range] [:= initial_value];
• Ejemplos:
• SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);

4. SIGNAL
 Contador de unos (1)
 The code has multiple
assignments to the same
signal; signal-temp- (temp <=
0; y temp <= temp + 1;).

5. VARIABLES
• Contrary to a signal or constant, a variable represents only local information.
• It can only be used within a process (sequential code) and its value can not be
transferred directly.
• Updating is immediate, and the new value can be used immediately in the next
line of code
• Sintaxis:
• VARIABLE name : type [range] [:= init_value];
• Examples:
• VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";

6. VARIABLES
 Contador de unos (1)

7. SIGNAL versus VARIABLE
SIGNAL VARIABLE
Asignació
n
<= :=
Utilidad Representa interconexión de
circuitos (cableado)
Representa información local
Visión Global Local (visible solo dentro del proceso)
Entorno En código secuencial, la
actualización no es inmediata (el
nuevo valor por lo general solo
es disponible a la finalización del
proceso).
Actualización inmediata (el nuevo valor
puede ser usado en la siguiente línea del
código)
Uso En Paquetes, entidades,
arquitecturas. En una entidad,
todos los puertos son señales por
defecto.
Solo en código secuencial (dentro de un
proceso, en su parte declarativa)

8. • Examples:
 In the process , both as output2 output1 are
stored ( inferred FF ) , because both values ​​are
assigned to the transition of another signal ( clk ) .
NUMBER OF RECORDS

9. NUMBER OF RECORDS
• Ejemplo 2:
 In the example , only output1 is stored ( output2 will use logic gates ) .

10. Número de registros: DFF con q and qbar
• Both solutions work properly. The Difference between
them lies in the number of FF required in each case .