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- 1. ANALOG AND MIXED MODE VLSI VI SEM ENC DATA CONVERTER FUNDAMENTALSIntroductionWhy data Conversion? • Most real-world signals are analog in nature. • Real-world signals-Continuous time, Continuous amplitude • However Digital signal processing allows us to efficiently manipulate information. • Digital abstraction-discrete time, discrete amplitude • To take advantage of DSP we must be able to move from analog to digital and back as neededWhat is data Converter? • A device that converts a signal from analog to digital domain and vice versa.What type of systems require data converters? • Any system that requires real inputs from outside world that need to be processed digitally or any system that wants to convert digital data to analog signal that can be interpreted in the outside world need a converter.How does a data converter fit in to signal chain? • Data converters typically accept analog signals from sensors once these signals have been conditioned, and pass off digital data to a processor. • They can also accept digital data from these devices and pass them off for signal conditioning and analog system output. 1
- 2. Applications- wide range. • Performance requirements such as resolution and bandwidth are set by intended applications. • Portable devices-push the limits of technology by requiring faster speed and lower power. • Communications: Wireless transceivers, Modems • Computing and control: Imagers,displays, Multimedia • Measurement & Instrumentation: Test equipment, Industrial and scientific Instrumentation, Sensors & actuators. • Consumer Electronics: Video/Audio, Control (Automotive, Appliances, etc). • Embedded data Conversion 2
- 3. Types of Data ConvertersTwo types: 1. Analog to digital Converter(ADC) 2. Digital to analog Converter(DAC)Analog to digital converter consists of two basic functions. • Sampling: convert a continuous time input signal to a discrete time representation. • Quantization: convert a continuous amplitude input signal to a discrete amplitude representation. • Input signal must be bandlimited to no more than ½ FS to prevent aliasing. 3
- 4. Uniform Sampling and QuantizationUniform Sampling and Quantization-Sample signal Uniformly in time-Quantize signal Uniformly in amplitudeIssues:How fast to sample?How much noise added to quantization?How can we reconstruct signal back to analog form?Discrete time signals-Discrete time signals are simply a sequence of numbers with a set ofcorresponding discrete time indexes.-Intermediate signal values are not defined.-Mathematically convenient but non-physical:use the term sampleddata signals. 4
- 5. -Representing signals in discrete–time domain determines anincrease in ambiguity in frequency domain; undesired frequencytranslation /interaction(aliasing)Sampling theoryFig. shown below illustrates the sampled signal in time and frequencydomain. 5
- 6. 6
- 7. Types of SamplingNyquist rate Sampling: Sampling at twice the signal frequencyDown samplingUp sampling 7
- 8. Over Sampling 8
- 9. Down Sampling fs<2fbData Converter Building blocks • Sample and Hold Circuits • Operational Amplifiers,OTA’s • Comparators • Filters • Current sources • Reference Circuits • Logic CircuitsData Converters key parameters • Performance parameters are Sampling freq Resolution. • Precision Parameters are 9
- 10. 10
- 11. 11
- 12. • Sampling frequency is the speed at which samples are measured and converted’ -inversely related to sample time. -measured in samples per second. • Resolution is the number of digital bits that the converter will use. -determines to what granularity a data converter can identify ananalog signal. -12 bit converter will have 212 different voltage levels it canidentify. • Throughput is the amount of digital data a converter uses in a given amount of time. -12 bit Conveter running at 100KSPS has 1.2Mbps throughput.INL and DNLINL(Integral Nonlinearity error)-deviation of the values on the actual transfer function from the idealtransfer function once the gain and offset errors are nullified.-The summation of differential nonlinearities from the bottom up to aparticular step , determines the value of the INL at that step. 12
- 13. INL(Integral Nonlinearity error)-INL is defined as the integral of DNL.-good INL gaurantees good DNL.-INL error-how far away from the ideal transfer function value themeasured converter is. -Can not be corrected are calibrated. -inherent in the design and manufacuring of the converter.-Point used as zero occurs ½ of LSB before the first code transition.-The full scale point is defined as level ½ LSB beyond last codetransition.-deviation is measured from centre of each particular code to the truestraight line between these two points.DNL (Differential Nonlinearity error)-difference between the actual step width (for an ADC) or stepheight(for DAC) and the ideal value of 1 LSB.-In ADC there is also a possibility that there can be missing codes.(ifDNL> -1LSB)i.e. one or more of the possible 2 n binary codes arenever output.DNL specifies the deviation of any adjacent code in the transferfunction of DAC or ADC from an ideal code width of 1 LSB. 13
- 14. -DNL is determined by subtracting the locations of successive codetransition points after compensating for gain and offset errors.-positive DNL implies that the code is longer than the ideal codewidth. - negative DNL implies that the code is Shorter than the ideal code width - DNL is measured in the increasing code direction of the transfer curve. - The transition of code N is compared to that of code N+1. - For DAC, DNL error of -1LSB implies that the output did not increase for increasing input code. - 14
- 15. - For DAC, DNL error of greater than -1LSB implies that the device is non-monotonic. - For an ADC,DNL error of greater than -1LSB implies that at least one code is missing, meaning that there is no analog voltage which will generate a particular code. - Manufactures include”No missing Codes”spec. Gain and Offset error - Gain error has a non ideal slope. - Ideally, in the graphs above, as the analog input increases at a certain rate, the output codes would also increase at the same rate. - If the output codes increase at a different rate than the analog input does, then it results in gain error.Gain error can be defined as the difference between the level thatproduces the greatest code and the smallest code, versus the ideallevels that produce these codesIn an ideal situation, data converter would begin to notice deviationsfrom true zero voltage.However, because of offset error, a small constant analog voltage isalways present before the conversion begins to function linearly. 15
- 16. 16
- 17. Dynamic Characteristics 1. SNR (Signal-to-Noise Ratio) - RMS value representing the ratio of the amplitude of the desired signal to noise power below one half of the frequency. - Measure of strength of a signal to background noise. - Contributes to the overall dynamic performance of the device at higher frequencies and affects the linearity at those frequencies. - In audio world, a low SNR means the device has lots of hiss and static high rating. - Key measure of Data converter. 2. Total Hormonic Distortion - The ratio of sum of the powers of all hormonic frequencies above the fundamental frequency to the power of the funadamental frequency.(dB) -expression of distortion effect of signal harmonics on the original signal. 3.ENOB(Effective Number of bits) -The number of bits achieved in a real system, discounting bits that are affected by noise. -Another way of specifying SNR. 4. SFDR(Spurious dynamic range) -Distance in dB between the fundamental input and the worst spur. -headroom available in FFT plot. -difference between the signal amplitude and the first and largest harmonic spur. -measure of signal quality. -higher values are desirable. 17
- 18. Data Converters Building blocks• Sample and Hold Circuits• Operational Amplifiers,OTA’s• Comparators• Filters• Current sources• Reference Circuits• Logic Circuits 18
- 19. Data Converters blocks-DACDigital n-bit word 19
- 20. • For an n-bit word, the MSB has a weight of2 (n-1) = 2 n / 2 where ‘n’ is the total number of bits in the word, • LSB has a weight of 1. • The Least and Most Significant Bits(LSB & MSB) are just what their name implies.Digital coding techniques 20
- 21. Thermometer code • Thermometer-code differs from a binary code in that a thermometer-code has 2N - 1 digital inputs to represent 2N different digital values, • Typically, in a thermometer-code the number of 1’s represent the decimal value.Features • Low DNL errors • Guarnteed monotonocity • Reduced glitch area • Increased complexity(binary code needs only N digital inputs to represent 2N different digital values.) 21
- 22. • The transfer function of DAC is a series of discrete points as shown in fig. • 1 LSB corresponds to the height of a step between successive analog outputs, • A DAC can be thought of as a digitally controlled potentiometer whose output is a fraction of the full scale analog voltage determined by the digital input data. • Resolution: The number of bits in the digital input word. • Each of the possible digital input word has its own unique analog output voltage.An N-bit digital word is mapped in to an equivalent analog voltage byscaling a reference. 22
- 23. Analog output of unipolar DAC is • Vref need special care for design. VLSB is the voltage change when one LSB changes. Data Converters DAC spec-Nonlinearity The maximum analog voltage that can be generated is known as full-scale voltage, VFS(does not equal to Vref, because the resolution is finite) and is defined as the difference between Vref and VLSB or the analog output for the largest digital word (111…1) and the analog output for the smallest digital word(000..0). 23
- 24. Consider 3 bit DAC. Vref: 5V Vout = F Vref F-fraction determined by n-bit word F=D/2N Vout(max) = 7/8 Vref. Max. analog voltage generated-full scale voltage VFSI LSB = Vref/2NFor 3-bit DAC 1 LSB= 5/8 V = 0.625VMSB causes the output to change by ½ Vref.Ex- Find the resolution of DAC if the output voltage is desired tochange in 1mV, Vref is 5V.Solution : DAC must resolve1mV/5V = 0.0002 =.02%Accuracy required = 1/2N =0.0002N=Log (5V/1mV)= 12.29 = 13 bitsComparison of 3,8 16 bit DAC with Vref=5vResolution Comb 1LSB % accuracy Vfs 3 8 0.625V 12.5 4.375V 8 256 19.5mV 0.391 4.985V16 65,536 76.29uV 0.00153 4.9999V • Increasing the resolution by 1 bit increases the accuracy by a factor of 2. • Precision required to map the analog voltage at high resolution is very difficult to achieve, • Vout approaches that of Vref as N increases. 24
- 25. DAC-NonlinearityDifferential Nonlinearity: • Ideal increments as per the ideal curve= 0.625V=1LSB • Nonideal components cause the analog increments to differ from ideal values.The difference between actual and ideal- differential nonlinearity is • DNLn = Actual increment height of transition n – Ideal increment height • N-number corresponding to digital input transition.Differential Nonlinearity:Examplen=3, Vref=5V1LSB=1/8 of Vout/VrefDNL 1=DNL 2=DNL 7=0DNL 3=1.5 LSB-1 LSB =0.5 LSB=0.3125VDNL 4=0.5 LSB-1 LSB =-0.5 LSBDNL 5=0.25 LSB-1 LSB =-0.75 LSBDNL 6=1.75 LSB-1 LSB =0.75 LSB 25
- 26. Differential Nonlinearity:ExamplePlot DNL in LSB versus input digital code.DNL for the converter is ±0.75LSB since the overall error of DAC isdefined by its worst-case DNL.Generally, DAC will have ±1/2 LSB of DNL ,if it is to be n-bitaccurate.Differential Nonlinearity:Example5-bit DAC with .75LSBs of DNL has resolution of 4-bit DAC.If the DNL for DAC is less than -1LSBs, then DAC is said to benonmonotonic.DAC-should exhibit monotonicity if it is to function witout error.The DNL specification measures how well a DAC can generateuniform analog LSB multiples at its output. 26
- 27. Integral Nonlinearity: • Another important Static characteristic of DAC. • Difference between the data converter output values and a reference straight line drawn through the first and last output values. • INL defines the linearity of overall transfer curve as INL n = Output value for input code n – output value of the reference line at that point.INL-other errors(gain and offset are zero) 27
- 28. Integral Nonlinearity:Converter with N-bit resolution will have less than ±1/2 LSB of DNL orINL.For ex- 13 bit DAC having greater than ±1/2 LSB of DNL or INLactually has the resolution of 12bit DAC.0.5LSB = Vref/2 N+1Integral Nonlinearity:Ex3-bit DAC, Vref=5VIntegral Nonlinearity:INL2 = INL4 = INL6= INL7=0INL1 = INL3 = 0.5LSBINL5 = -0.75LSBINL for the DAC is considered to be its wirst case INL of +0.5 LSBand -0.75 LSB.Another method: Best-fit-minimize INL 28
- 29. Offset ERROR:Analog output should be 0V for D=0However, an offset exists.-seen as shift in the transfer curve. 29
- 30. Gain ERROR:Gain error exists if the slope of the best-fit line through the transfercurve is different from the slope of the best-fit line for the ideal case.Gain error=Ideal slope-Actual slope.Latency:Total time from the moment that the input digital word changes to theanalog output value has settled to within a specified tolerance. 30
- 31. Signal to Noise Ratio-SNR:-ratio of Signal power to the noise at the analog output.Dynamic Range:Largest output signal over the smallest output signal.Related to resolutionN-bit DAC can produce a maximum of 2N -1 multiples of LSBs anda minimum value of 1LSB.Dynamic Range:Largest output signal over the smallest output signal.Related to resolutionDR = 20log(2N - 1)/1 DB16 bit DR is 96.33db. Analog to Digital Converter 31
- 32. 32
- 33. • Resolution of an A/D Converter is the number of output bits it has(3-bits, in this example)• Resolution may also be defined as the size of the LSB or one count.Sample-and-hold(S/H) are critical in ADC.• Characterize S/H circuit-performing data conversion.• Analog signal is instantly captured and held until the next sampling period.• However, a finite amount of time is required for sampling.• During sampling period, analog signal may continue to vary- track-and-hold or T/H. 33
- 34. • S/H circuits operate in both static(hold mode) and dynamic(sample mode)Sample Mode • .Acquisition time: Time required for the S/H to track the analog signal to within a specified tolerance, once the sampling command has been issued. • Worst case acquisition time would correspond to the time required for the output to transition from 0 to Vin(max). • S/H circuits use amplifiers as buffers. 34
- 35. Sample Mode • .Acquisition time: • Output of T/H is limited by the amplifier’s slew rate. • If the amplifier is not compensated correctly, and the phase margin is too small, then a large overshoot occur which requires a longer settling time. • Error tolerance at the output of S/H –dependent on amplifiers’s offset, gain error and linearity. 35
- 36. Hold Mode1.Pedestal error: occurs as result of charge injection and clockfeedthrough. • Part of the charge built up in the channel of the switch is distributed onto the capacitor,slightly changing its voltage. • Clock couples onto the capacitor via overlap capacitance between the gate and the source or drain.Droop error:related to leakage of current from the capacitor due to parasiticimpedances and to the leakage through reverse biased diode formedby drain of the switch.Leakage current: compensated by making drain area small.Minimize droop: increase the value of the capacitor.Tradeoff,however –increase time required to charge the capacitor tothe value of the input signal.Aperture ErrorTransient effect that introduces error occurs between the sample andhold modes. 36
- 37. Finite amount of time,referred to as aperture time, is required todisconnect the capacitor from the analog input source.Aperture Uncertainty or aperture jitter:creating sampling error.Aperture ErrorRelated to the frequency of the signal and the worst case apertureerror occurs at the zero crossing, where dV/dt is the greatest.This assumes that the S/H circuit is capable of sampling both positiveand negative voltages.The amount of error that can be tolerated is directly related to theresolution of the conversion. • Example:Given Vin= A sin 2*pi*f*t A=2V f=100KHzAperture uncertainity is 0.5ns.Find the sampling error 37
- 38. Solution: dV/dt = 2*pi*f* A cos 2*pi*f*t • Maximum slew rate occurs when cosine term is = 1, • dV/dt (max) = 2*pi*f*A. • Sampling error = dV(max)= 0.628mVFor ADC, the input is an analog signal with an infinite number ofvalues, which has to be quantized into an N-bit digital word.ADC, however has to “quantize” the infinite-valued analog signal intomany segments so thatNumber of quantization levels=2NTransfer curve: stair caseMaximum output of ADC will be 111(2N -1) corresponds toVin/Vref≥7/8.Error caused by quantization. 38
- 39. 1 LSB = Vref/2N = 0.625V for Vref=5VQuantization Error:Difference between the actual analog input and the value of theoutput(staircase) given in voltage.Quantization Error:Qe =Vin – V staircaseV staicase =D. Vref/2N = D. VLSBVLSB is value of 1 LSB in volts.Qe-expressed in terms of LSBs.Qe-generated by subtracting the value of the staircase from thedashed line.Quantization Error: • Sawtooth waveform is centered about ½ LSB. • Ideally magnitude of Qe will be between 0 and 1 LSB. • If Qe is centered about zero so that error would be ±1/2 LSB. • Here entire curve is shifted to left by ½ LSB. 39
- 40. Quantization Error:First code transition occurs when Vin/Vref ≥1/16. .(between 0 and1/8)Therefore the range of Vin/Vref for the digital output corresponding to000 is half as wide as the ideal step.Last transition occurs when Vin/Vref ≥13/16.(between 6/8 and 7/8)DNL:Similar to that of DAC.DNL is the difference the actual code width of a nonideal converterand the ideal case.DNL=Actual step width-Ideal step width. 40
- 41. Since the step widths can be converted to either volts for LSBs, DNLcan be defined in either units.DNL:Ideal step width=1/8Videalstepwidth=1/8 Vref= 0.625V=1LSBExample: 3-bit ADC, Vref=5V, find Qe in units of LSBs.DNL0=DNL4 =DNL5=0DNL2 = 1.5 LSB-1LSB = 0.5LSBDNL3= 0.5 LSB-1LSB = -0.5LSBDNL5 = -0.5LSBDNL6 = -0.5LSBOverall DNL for the curve is ±0.5LSBAs DNL increases in either direction, Qe worsens. 41
- 42. DNL:ADC with -1LSB DNL is guarnteed to have a missing code.DNL5 = -1LSB- missing code.ADC with -1LSB DNL is not guarnteed to have a missing code 42
- 43. INL0=INL1 =INL4 =INL5 =INL7 =0INL3 = 3/8 -5/16 = 1/16=0.5LSBINL6 =-0.5LSBOverall INL for the curve is ±0.5LSBINL determined by inspecting value of Qe.INL=magnitude of Qe outside ±LSB band of Qe. 43
- 44. Offset and Gain Errors:Identical to DAC.Offset errors occur when there is a difference begtween the value offirst code transition and the ideal value of ½ LSB.Offset error is a constant value.Qe becomes ideal after initial offset is overcome.Gain or Scale factor error-differenceGain or Scale factor error-difference in the slope of a straight line drawn through the transfercharacteristic and the slope of an ideal ADC.Aliasing.Dynamic aspects of converter.Falias = Factual - Fsample 44
- 45. 45
- 46. 46
- 47. Signal to Noise Ratio(SNR)-ratio of largest RMS input signal into the converter over the RMSvalue of the noise.SNR=20 log (Vin(max)/VnoiseVin(max) = Vref/2*21/2 = 2N VLSB/2*21/2Qe,RMS = VLSB/121/2SNR=20N log (2) + 20 log (121/2) - 20 log (2*21/2) = 6.02N+1.76Signal to Noise Ratio(SNR)Example:16-bit ADC, SNRD=88db Resolution=?SNR= 6.02N+1.76N= 88-1.76/6.02 = 14.32 bitsMixed Signal layout Issues • Analog IC’s are more sensitive to noise than digital iC’s. • Sensitive analog nodes must be protected and shielded from any potential noise sources. • Grounding and power supply routing must also be considered. • Most of the ADC’s use switches controlled by digital signals. • Techniques for mixed-signal designs vary in complexity and priority. • Successful design will always minimize the effect of the digital switching on the analog circuits.Mixed Signal layout StrategySystem level- Device level-Interconnect level • Interconnect considerations • Shielding 47
- 48. • Guard rings • Fully differential/Matching design • Power supply and Grounding Issues • FloorplanningTypes of DAC • Resistor String • R-2R ladder Network • Current Steering • Charge scaling DAC • Cyclic DAC • Pipeline DAC Resistor String DAC • Most basic DAC. • Simple resistor string of 2N identical resistors and switches, • Analog output voltage is voltage division of resistors at the selected output tap. 48
- 49. Resistor String DAC • Arch: typically results in good accuracy, provided that no output current is required and the values of resistors are within the specified error tolerance . • Ouput is monotonicDrawbacks • Converter output is always connected to 2N -1 switches that are off and one switch is ON. • For larger resolution, a large parasitic capacitance appears at the output node, resulting in slower conversion speeds.Alternative to Resistor String DAC • Input to the switch array is binary word since the decoding is inherent in binary tree arrangement of the switch. • Another drawback in resistor string is • Balance between area and power dissipation. 49
- 50. • IC version of DAC –larger area because of large prime components for higher resolution • For low resolution use active resistors such as nwell resistors. • As resolution increases , relative accuracy of resistors becomes important factor. • R can be made small to rteduce area, power dissipation would then be critical issue as current flows through the resistor string at all times.Resistor String Problem • 3bit resistor string DAC using binary switches, VrefV, PD= 5mW, Compute the analog output for each input digital data. Imax= 5mW/5V =1mA R= 1/8 * 5V/1mA = 625 ohms. 50
- 51. Data Converters DAC-NonlinearityMismatch errors relate to Resistor String DAC • Accuracy of resistor string is related to matching between the resistors, which determine DNL and INL. • Let resistor Ri has mismatch error, so that Ri= R + ∆Ri ideal + mismatch • Suppose mismatches were symmetrical about the string, so that sum of all the mismatch terms were zero or N 2 ∑ i=1 ∆ Ri = 0 Value of voltage at the top ri is Vi, ideal= (i) Vref/ 2N for i=1,2 ….2N -1 51
- 52. • Actual value of ith voltage will be the sum of all resistors up to and including resistor i, divided by the sum of all resistors in the string i i ∑ k =1 Rk ∑ k =1 R + ∆ Rk Vi = N ⋅ Vref = N ⋅ Vref 2 2 ⋅R ∑ k =1 Rk i Vref ⋅ i Vref Vi = N + N ∑ ∆ Rk 2 2 ⋅R k =1 i Vref ∆Rk Vi = Vi, ideal + N ∑ R 2 k =1INL of Resistor String DACINL= Vi-Vi,idealWorst case INL when i=2N and ∆Rk mismatch. i Vref INL = N ∑ ∆ Rk / R 2 k =1INL of Resistor String DACIf resistors mismatch by 2%, then-.02R≤∆Rk≤+.02R i Vref INL = N ∑ ∆ Rk /R 52 2 k =1
- 53. INL max = Vref/2N * 2N-1 *.02R/R =.01VrefEx:Find n if limited by INLIf resistors mismatch by 1%, then-.01R≤∆Rk≤+.01R N −1 Vref 2 INL = N ∑ ∆ Rk /R 2 k =1INL max = Vref/2N * 2N-1 *.01R/R =.005Vref =.025V INL max = ½ LSB1/2LSB = .025V = 5/2N+1DNL of worst case Resistor string DACDNL= actual step height-ideal step height i (i )Vref Vref ∆Rk Vi − Vi − 1 = N + N ∑ R 2 2 k =1 Vref ∆ Ri Vactual = N 〈1 + 〉 2 RDNL=Vactual –Videal = Vref/2N* ∆Ri/R 53
- 54. Ex: let ∆R = 2%DNL max= .02R/R * Vref/2N = .02LSBDNL max ≤1/2 LSBR-2R Ladder Network • Fewer resistors • Starting at the right end of network, resistance looking to right of any node to groun is 2R. • Vout= -itot*Rf • N −1 Vref 1 itot = ∑ Dk N ⋅ 2R k =0 2Dk kth bit of input wordSwitch resistance is negligible.voltage drop leading to errorTotal resistance of any horizontal branch R’R’ = R + ∆R/2Resistance of any vertical; branch is 2R + ∆R 54
- 55. R-2R Ladder NetworkR’-2R’ relationship to be maintained,Dummy switch size of a 2R switch will have to be placed in serieswith the terminating resistor as well.Problem3-bit DAC R=1k, Rf = 2k, Vref=5VSwitch resistances negligible. 55
- 56. Integral Nonlinearity 56
- 57. Current SteeringUses current throughout conversion.Requires precision current source.Set of current sources 57
- 58. 58
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