This document discusses power electronic devices and their characteristics. It describes several types of power devices including bipolar junction transistors (BJT), field effect transistors (FET), thyristors, Darlington transistors, and insulated gate bipolar transistors (IGBT). It covers the key characteristics, operating principles, and ratings of these devices. It also discusses how snubber circuits using inductors, resistors, and capacitors can be designed to protect power devices from high rates of change of current (di/dt) and voltage (dv/dt) during switching.

1. Power Electronic
Devices and their
Characteristics

2. Control of Energy
Consumption
Period (t)
On-time
(ton)
Off-time
(toff)
Time
Power
P
t
P
E 
Duty Ratio (K)
t
P
t
E on
t


3. Load Switching
Period (t)
On-time
(ton)
Off-time
(toff) Time (t)
Power
P
toff
ton

4. Ideal Switch
Vsw
i
R
vs
vsw
i
vt
+
-
vs
R
vs

5. N
N
P
(C)
(B)
(E)
Collector
Emitter
Base
(C)
(B)
(E)
(C)
(E)
(B)
IB
IC
IE
VCE
VCB
VBE
B
C I
I 

C
B
E I
I
I 

BE
CB
CE V
V
V 

Bi-polar Transistor (BJT)

6. IB
V
BE
0.6
IB1
IB2
< IB1
I = 0
B
Base Characteristics Collector Characteristics
Linear Region
Saturation Region
Cut Off Region
IC
VCE
Characteristics of Bi-polar
Transistor
(C)
(E)
(B)
IB
IC
IE
VCE
VCB
VBE

7. VCE
IC
VCC
RL
IB max
IB = 0
(1)
(2)
IC
RL
VCC
VCE
IB
C
L
CE
CC I
R
V
V 

VCC
At point (1)
VCE is very small
L
CC
C
R
V
I 
At point (2)
IC is very small
CC
CE V
V 
Closed
switch
Open
switch

9. Example
• A transistor has a current gain of 200
in the linear region and 10 in the
saturation region. Calculate the base
current when the collector current is
equal to 10 A assuming that the
transistor operates in the linear
region. Repeat the calculation for
the saturation region

10. Solution
mA
50
200
10
I
I
1
C
B 



In the linear region
In the saturation region
A
1
10
10
I
I
2
C
B 




11. Main Features of BJT
• Current controlled device
– Base current must be present during the
closing period
– High base losses
• Low current gain in the saturation
region
• Can operate at high frequencies

12. Field Effect Transistor (FET)
ID
VDS
V GS1
VGS3 < VGS2
VGS2 < VGS1
V
GS4 < V GS3
0 <
(G)
(D)
(S)
ID
VDS
VGS

13. Main Features of FET
• Voltage controlled device
• Low gate losses

14. Thyristors (Four Layer Diode)
N
N
P
P
Anode (A)
Cathode (K)
VBO
IA
VRB
Ih
VAK

15. Thyristors [Silicon Controlled Rectifier
(SCR)]
AK
VBO
I
A
V
VRB
Anode (A)
Cathode (K)
Gate (G)
V
TO
Ig > 0
Ig = 0
Ig = max
Ih

17. Closing Conditions of SCR
1. Positive anode to
cathode voltage
(VAK)
2. Maximum
triggering pulse is
applied (Ig)
Anode (A)
Cathode (K)
Gate (G)
Closing angle is a

18. Opening Conditions of SCR
1. Anode current is
below the holding
value (Ih)
AK
I
A
V
VRB
Ig = 0
Ih
Opening angle is 

19. Other Power Devices (Darlington
Transistor)
Ib1
Ib2
Ie2
(B)
(C)
(E)
b1
1
2
b2
2
e2 I
)
(1
)
(1
I
)
(1
I 

 




120
10
)
(1
)
(1
I
I
1
2
1
2
1
2
1
total
1
2
b1
e2






















total
total
;
If
region
saturation
in
low
is
I
I
B
C



20. Other Power Devices
Insulated Gate Bipolar Transistor
(IGBT)
I
b
Ie
(G)
(C)
(E)
(D)
VGS

21. IC
VCE
VG2
VG3
VG1 > VG2 > VG3
IC
VG
C
E
G
IC

23. Ratings of Power Electronic Devices
• Steady State Circuit ratings:
• The current and voltage of the circuit
should always be less than the
device ratings.

24. Ratings of Power Electronic Devices
• Junction temperature: Losses inside
solid-state devices are due to
impurities of their material as well as
the operating conditions of their
circuits.

25. Ratings of Power Electronic Devices
• During the conduction period, the voltage drop across
the solid-state device is about one volt. This voltage
drop multiplied by the current inside the device
produces losses.
• When the device is in the blocking mode (open), a
small amount of leakage current flows inside the
device which also produces losses.
• The gate circuits of the SCRs and FETs, and the
base circuits of the transistors, produce losses due to
their triggering signals.
• Every time the solid state device is turned on or off,
switching losses are produced. These losses are
usually higher for faster devices, and for devices
operating in high frequency modes.

28. Ratings of Power Electronic Devices
• Surge current: It is the absolute maximum
of the non-repetitive impulse current

29. Ratings of Power Electronic Devices
• Switching time:
• Turn-on time is the interval between applying
the triggering signal and the turn-on of the
device.
• The turn-off time is the interval from the on-
state to the off-state.
• The larger the switching time the smaller is the
operating frequency of the circuit.

30. Ratings of Power Electronic Devices
• Critical rate of rise of current (or
maximum di/dt): A solid-state device can
be damaged if the di/dt of the circuit
exceeds the maximum allowable value of
the device. di/dt damage can occur even if
the current is below the surge limit of the
device. To protect the device from this
damage, a snubbing circuit for di/dt must be
used.

31. Ratings of Power Electronic Devices
• Critical rate of rise of voltage (or
maximum dv/dt): When dv/dt across a
device exceeds its allowable limit, the
device is forced to close. This is a form of
false triggering. It may lead to excessive
current or excessive di/dt. To protect the
device against excessive dv/dt, a snubbing
circuit for dv/dt must be used.

32. di/dt and dv/dt Protection
Load
V
L s
R
s
C s
+ -
32

33. Closing Switch
C
j
L
j
R
ZL


1



Load impedance
Load
V
L s
R C
s s
I
1
+ -
I2
33

34. Closing Switch: Analysis of I1
Load
V
L s
I
1









CS
L
S
R
S
V
S
I
1
)
(
)
(
1
34
L
s L
L
L 

LL, RL, CL

35. Closing Switch: Analysis of I1
Load
V
L s
I
1
35
L
C
R
LC
n
2
;
1

 

 )
t
e
V
C
t
i n
t
n n
)
1
(
sin
)
1
(
)
( 2
2
1 


 



 

36. Snubbing Circuit: Ls
]
)
1
(
[
cos
]
)
1
(
[
sin
)
1
(
2
2
2
2
2
1
t
e
V
C
t
e
V
C
dt
di
n
t
n
n
t
n n
n







 








 

L
V
dt
di
max
1 






Worst Scenario for Maximum di/dt: When the load capacitor is not charged at t=0
L
s L
dt
di
V
L 







max
1
L
rating
BO
s L
dt
di
V
L 







1
.
0
2
max
1
n
V
C
dt
di


36
LC
n
1



37. Closing Switch: Analysis of I2
The fully charged cap discharges after the switch is closed
s
s C
R
t
s
o
2 e
R
V
i


s
s C
R
t
s
2
s
o
2 e
C
R
V
dt
di 


Load
V
L s
R C
s s
I2
+ -
37

38. Closing Switch: Analysis of I2
s
s C
R
t
s
2
s
o
2 e
C
R
V
dt
di 


s
s
o
C
R
V
dt
di
2
max
2 







Load
V
L s
R C
s s
I2
+ -
At t = 0
rating
dt
di
dt
di
Let 












1
.
0
max
2
38

39. Opened Switch
L
L
L
L
C
j
L
j
R
Z


1



Load impedance
Load
V
L s
R C
s s
I
3
+ -
39

40. Opened Switch









CS
L
S
R
S
V
S
I
1
)
(
)
(
3
L
s R
R
R 

L
s L
L
L 

L
s
L
s
C
C
C
C
C


Load
V
L s
R C
s s
+ -
I
3
40

41. Opened Switch
Assume the caps are initially discharged
3
i
R
V s
sw 
dt
di
R
dt
dV
s
sw 3

L
V
R
dt
dV
s
sw

41
Load
V
L s
R C
s s
+ -
I
3

42. Selection of the Snubbing Circuit Parameters
L
rating
BO
s L
dt
di
V
L 







1
.
0
s
s
o
rating C
R
V
dt
di
2
1
.
0








L
V
R
dt
dV
s
sw

Step 1: Compute snubbing inductance
Step 2: Compute snubbing Resistance
Step 3: Compute snubbing Capacitance
42