RISC-V is the most recent attempt (originally from UC Berkeley) to design a brand new instruction set architecture based on the reduced instruction set computing (RISC) principles. One of its goals is to be completely open and free (both as in free beer and as in free speech) for designers, users and manufacturers. HelenOS is an open source operating system designed and implemented from scratch based on the microkernel multiserver design principles. One of its goals is to provide excellent target platform portability and it currently supports 8 different hardware platforms.
Both projects are still in the process of maturing: While the unprivileged (user space) instruction set architecture of RISC-V has been declared stable in 2014, the privileged instruction set architecture is still in a stage of draft and is allowed to change in the future. Likewise, many major design features and building blocks of HelenOS are already in place, but no official commitment to ABI or API stability has been made yet.
This talk introduces both projects, presents the initial lessons learned from porting HelenOS to RISC-V and evaluates the portability of HelenOS on yet another porting effort.
HI-3220 ARINC 429 DATA MANAGEMENT ENGINE
16 x RECEIVERS, 8 x TRANSMITTERS, ADK-3220. Application Development Kit Users Guide and High Density 16Rx / 8Tx or 8Rx / 4Tx ARINC 429 HI-3220 datasheet.
The future of RISC-V Supervisor Binary Interface(SBI)Atish Patra
The document discusses the RISC-V Supervisor Binary Interface (SBI), which provides an interface to access machine mode registers from supervisor mode. It notes limitations with the current SBI specification and proposes extensions to make it more extensible. This includes developing an OpenSBI project to provide a standardized open source SBI implementation that bootloaders can use.
This document provides an overview of the ARM processor. It begins with a brief history, describing how ARM was developed in the 1980s by Acorn Computers in Cambridge, England. It then defines what a processor is and explains the differences between RISC and CISC architectures. The document discusses key features of ARM processors like pipelining and conditional execution. It specifically examines the ARM7TDMI processor, describing its instruction sets including ARM, Thumb, and operating modes. Application areas for ARM like mobile phones and automotive are listed. The document concludes with references used in its preparation.
This document provides an overview of ARM embedded systems, including the ARM processor architecture, instruction set, hardware components, and software stack. It describes the RISC design philosophy behind ARM and how its instruction set is optimized for embedded applications. It also discusses the ARM bus technology, memory, peripherals, boot code, operating systems, and common application areas for ARM processors like networking, automotive, mobile devices, and more.
This ppt is basically about the very basic knowledge of the Microcontroller, applications of Microcontroller, and the connections and components which are inbuilt in a Microcontroller.
The Raspberry Pi is a credit-card sized computer that can perform many of the functions of a desktop computer. It has a 700MHz processor, 512MB of RAM, HDMI and USB ports, and runs Linux-based operating systems from a microSD card. While less powerful than a laptop, the Raspberry Pi provides an inexpensive platform for learning programming through languages like Python and experimenting with electronics. It has found applications as a desktop computer, game console, web server, and more. Later versions of the Raspberry Pi, such as the Raspberry Pi 3, increased processing power while maintaining a low price point.
Raspberry Pi is a single board computer that is about the size of a credit card. It has various ports and connections that allow it to be used for many purposes like media center, office tasks, programming, and more. It uses Linux operating systems and can control physical devices like servos through its GPIO pins using Pulse Width Modulation. The document describes connecting a servo to the Raspberry Pi GPIO pin and using the WiringPi library to send PWM signals to control the servo position.
this ppt is related to the introductory part of assembly language and will be very useful for beginners of information technology students either at their graduation level or at post graduation level
HI-3220 ARINC 429 DATA MANAGEMENT ENGINE
16 x RECEIVERS, 8 x TRANSMITTERS, ADK-3220. Application Development Kit Users Guide and High Density 16Rx / 8Tx or 8Rx / 4Tx ARINC 429 HI-3220 datasheet.
The future of RISC-V Supervisor Binary Interface(SBI)Atish Patra
The document discusses the RISC-V Supervisor Binary Interface (SBI), which provides an interface to access machine mode registers from supervisor mode. It notes limitations with the current SBI specification and proposes extensions to make it more extensible. This includes developing an OpenSBI project to provide a standardized open source SBI implementation that bootloaders can use.
This document provides an overview of the ARM processor. It begins with a brief history, describing how ARM was developed in the 1980s by Acorn Computers in Cambridge, England. It then defines what a processor is and explains the differences between RISC and CISC architectures. The document discusses key features of ARM processors like pipelining and conditional execution. It specifically examines the ARM7TDMI processor, describing its instruction sets including ARM, Thumb, and operating modes. Application areas for ARM like mobile phones and automotive are listed. The document concludes with references used in its preparation.
This document provides an overview of ARM embedded systems, including the ARM processor architecture, instruction set, hardware components, and software stack. It describes the RISC design philosophy behind ARM and how its instruction set is optimized for embedded applications. It also discusses the ARM bus technology, memory, peripherals, boot code, operating systems, and common application areas for ARM processors like networking, automotive, mobile devices, and more.
This ppt is basically about the very basic knowledge of the Microcontroller, applications of Microcontroller, and the connections and components which are inbuilt in a Microcontroller.
The Raspberry Pi is a credit-card sized computer that can perform many of the functions of a desktop computer. It has a 700MHz processor, 512MB of RAM, HDMI and USB ports, and runs Linux-based operating systems from a microSD card. While less powerful than a laptop, the Raspberry Pi provides an inexpensive platform for learning programming through languages like Python and experimenting with electronics. It has found applications as a desktop computer, game console, web server, and more. Later versions of the Raspberry Pi, such as the Raspberry Pi 3, increased processing power while maintaining a low price point.
Raspberry Pi is a single board computer that is about the size of a credit card. It has various ports and connections that allow it to be used for many purposes like media center, office tasks, programming, and more. It uses Linux operating systems and can control physical devices like servos through its GPIO pins using Pulse Width Modulation. The document describes connecting a servo to the Raspberry Pi GPIO pin and using the WiringPi library to send PWM signals to control the servo position.
this ppt is related to the introductory part of assembly language and will be very useful for beginners of information technology students either at their graduation level or at post graduation level
Join this video course on udemy . Click here :
https://www.udemy.com/course/mastering-microcontroller-with-peripheral-driver-development/?couponCode=SLIDESHARE
Learn bare metal driver development systems using Embedded C: Writing drivers for STM32 GPIO,I2C,SPI,USART from scratch
Software/Hardware used:
In this course, the code is developed such a way that, It can be ported to any MCU you have at your hand.
If you need any help in porting these codes to different MCUs you can always reach out to me!
The course is strictly not bound to any 1 type of MCU. So, if you already have any Development board which runs with ARM-Cortex M3/M4 processor,
then I recommend you to continue using it.
But if you don’t have any Development board, then check out the below Development boards.
This document discusses parallel processing techniques in computer systems, including pipelining and vector processing. It provides information on parallel processing levels and Flynn's classification of computer architectures. Pipelining is described as a technique to decompose sequential processes into overlapping suboperations to improve computational speed. Vector processing involves performing the same operation on multiple data elements simultaneously. The document outlines various pipeline designs and hazards that can occur, such as structural hazards from resource conflicts and data hazards from data dependencies.
An unique module combining various previous modules you have learnt by combing Linux administration, Hardware knowledge, Linux as OS, C/Computer programming areas. This is a complete module on Embedded OS, as of now no books are written on this with such practical aspects. Here is a consolidated material to get real hands-on perspective about building custom Embedded Linux distribution in ARM.
The Opcode or the operation code is the part of the instruction that specifies the operation to be performed by the instruction. The CPU decodes (understands) the instruction with the help of the opcode. Copy the link given below and paste it in new browser window to get more information on Operand and Opcode:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/operand-and-opcode.aspx
Introduction to the 16-bit PIC24F Microcontroller FamilyPremier Farnell
The document introduces Microchip's 16-bit PIC24F microcontroller family. It provides an overview of the PIC24F architecture, including its 16-bit CPU core, block diagram, and peripherals. It also discusses the development tool support for the PIC24F family, including hardware tools like the MPLAB ICD 2 in-circuit debugger/programmer and MPLAB REAL ICE in-circuit emulator.
Embedded Systems are basically Single Board Computers (SBCs) with limited and specific functional capabilities. All the components that make up a computer like the Microprocessor, Memory Unit, I/O Unit etc. are hosted on a single board. Their functionality is subject to constraints, and is embedded as a part of the complete device including the hardware, in contrast to the Desktop and Laptop computers which are essentially general purpose (Read more about what is embedded system). The software part of embedded systems used to be vendor specific instruction sets built in as firmware. However, drastic changes have been brought about in the last decade driven by the spurt in technology, and thankfully, the Moore’s Law. New, smaller, smarter, elegant but more powerful and resource hungry devices like Smart-phones, PDAs and cell-phones have forced the vendors to make a decision between hosting System Firmware or full-featured Operating Systems embedded with devices. The choice is often crucial and is decided by parameters like scope, future expansion plans, molecularity, scalability, cost etc. Most of these features being inbuilt into Operating Systems, hosting operating systems more than compensates the slightly higher cost overhead associated with them. Among various Embedded System Operating Systems like VxWorks, pSOS, QNX, Integrity, VRTX, Symbian OS, Windows CE and many other commercial and open-source varieties, Linux has exploded into the computing scene. Owing to its popularity and open source nature, Linux is evolving as an architecturally neutral OS, with reliable support for popular standards and features
This document provides an introduction to PIC microcontrollers. It discusses the architecture of PIC microcontrollers, including the 16C6x and 16C7x architectures. It describes the registers, memory, and instruction set of PIC microcontrollers. Some key points covered include the Harvard architecture, pipelining, addressing modes, arithmetic, logical, and conditional instructions. Peripherals like timers and interrupts are also mentioned.
This document introduces the STM32 microcontroller. It will cover the ARM Cortex processor, the STM32 system-on-chip, and its basic building blocks. The course outline includes introductions to the Cortex architecture, CMSIS standard, STM32 system architecture, peripherals, low power operation, safety features, flash memory, and development tools.
This document discusses ARM assembly language programming. It describes different types of instructions in ARM assembly like arithmetic operations, bitwise logical operations, register movement, comparison operations, and data transfer instructions. It also explains the use of immediate operands, shifted register operands, and multiply instructions. The document concludes that it provides the basic concepts of ARM assembly language programming using these different instruction sets.
presentation By Daroko blog-where IT learners Apply skills.
This topic an presentation will introduce you to Computer graphics hardware types.
---------------------------------
• Daroko blog (www.professionalbloggertricks.com)
• Presentation by Daroko blog, to see More tutorials more than this one here, Daroko blog has all tutorials related with IT course, simply visit the site by simply Entering the phrase Daroko blog (www.professionalbloggertricks.com) to search engines such as Google or yahoo!, learn some Blogging, affiliate marketing ,and ways of making Money with the computer graphic Applications(it is useless to learn all these tutorials when you can apply them as a student you know),also learn where you can apply all IT skills in a real Business Environment after learning Graphics another computer realate courses.ly
• Be practically real, not just academic reader
Do Not just learn computer graphics an close your computer tab and go away..
APPLY them in real business,
Visit Daroko blog for real IT skills applications,androind, Computer graphics,Networking,Programming,IT jobs Types, IT news and applications,blogging,Builing a website, IT companies and how you can form yours, Technology news and very many More IT related subject.
-simply google:Daroko blog(professionalbloggertricks.com)
The document provides an overview of Arduino, including what it is, common Arduino boards, digital and analog input/output, and example projects. Arduino is an open-source electronics prototyping platform that can be used to create interactive objects. It uses a simple hardware and software environment to program and develop prototypes. The Arduino Uno is one of the most commonly used boards, which contains an Atmega328 microcontroller, digital and analog pins, and can be programmed via USB. The document describes how to connect various components like LEDs, buttons, sensors and motors to an Arduino board.
This document discusses bootloaders, specifically the Universal Boot Loader (U-Boot). It provides an overview of bootloader concepts, U-Boot specifics, the U-Boot initialization sequence, how U-Boot passes arguments to the kernel, hands-on with U-Boot commands, the U-Boot source code structure, configuring and compiling U-Boot for a board, and porting U-Boot to support a new board.
Processor Organization and ArchitectureDhaval Bagal
This document discusses processor organization and architecture. It covers the stored program concept where both instructions and data are stored in memory. It describes the Von Neumann architecture, which includes a main memory, ALU, control unit, and I/O. It discusses the registers used in processor control and execution like the program counter, accumulator, and instruction register. Finally, it examines addressing modes like immediate, direct, indirect, register, displacement, and stack addressing.
This chapter discusses processor structure and function. It covers the basic components of a CPU including registers, instruction cycles, and data flow. Key points include:
- A CPU must fetch, interpret, fetch operands for, process, and write data from instructions. It uses registers for temporary storage and a program counter to keep track of instructions.
- Common registers include general purpose, data, address, condition code, control/status, and program status registers. General purpose registers can vary in number, size, and whether they are general or specialized use.
- An instruction cycle involves fetching an instruction from memory, decoding it, fetching operands, executing the instruction, and writing results. Pipelining and branch prediction are
The document discusses instruction set architecture (ISA), which is part of computer architecture related to programming. It defines the native data types, instructions, registers, addressing modes, and other low-level aspects of a computer's operation. Well-known ISAs include x86, ARM, MIPS, and RISC. A good ISA lasts through many implementations, supports a variety of uses, and provides convenient functions while permitting efficient implementation. Assembly language is used to program at the level of an ISA's registers, instructions, and execution order.
Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and ...jycazihi6460
Read Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C PDF Third Edition
[PDF] Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C Ebook by Yifeng Zhu.ePUB / PDF
Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition ePUB / PDF / Mobi / SCRIBD.COM
(.PDF).| I have been an embedded design engineer since 1990, just before the introduction cell phones. A lot has changed and some things remained the same. This is a great book and easy to understand especially if your new to embedded engineering. ... (Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition PDF Yifeng Zhu EBOOK).
Play Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C Third Edition AUDIOBOOK.Download Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition Zip / RAR PDF.
Embedded Systems with ARM Cortex-M Microcontroller
This document provides an introduction to microcontrollers. It defines microcontrollers as small computers capable of performing specific tasks, like in appliances. Microcontrollers contain a CPU core, memory, input/output ports, timers and other peripherals on a single chip. They are classified as either microcontroller units (MCU) or microprocessor units (MPU) depending on whether external components are needed. Common microcontroller components and their functions are described, along with factors to consider when choosing a microcontroller for an application.
The document summarizes the state of the HelenOS operating system. The latest release, version 0.5.0 from August 2012, included significant hardware support improvements and integration of development branches for USB, networking, and file systems. Upcoming work focuses on graphics, IPC improvements, and self-hosting capabilities like compilers and virtual machines. Long-term goals include a graphical user interface, additional device support, and using HelenOS as both a hosted and hosting platform for Xen.
Join this video course on udemy . Click here :
https://www.udemy.com/course/mastering-microcontroller-with-peripheral-driver-development/?couponCode=SLIDESHARE
Learn bare metal driver development systems using Embedded C: Writing drivers for STM32 GPIO,I2C,SPI,USART from scratch
Software/Hardware used:
In this course, the code is developed such a way that, It can be ported to any MCU you have at your hand.
If you need any help in porting these codes to different MCUs you can always reach out to me!
The course is strictly not bound to any 1 type of MCU. So, if you already have any Development board which runs with ARM-Cortex M3/M4 processor,
then I recommend you to continue using it.
But if you don’t have any Development board, then check out the below Development boards.
This document discusses parallel processing techniques in computer systems, including pipelining and vector processing. It provides information on parallel processing levels and Flynn's classification of computer architectures. Pipelining is described as a technique to decompose sequential processes into overlapping suboperations to improve computational speed. Vector processing involves performing the same operation on multiple data elements simultaneously. The document outlines various pipeline designs and hazards that can occur, such as structural hazards from resource conflicts and data hazards from data dependencies.
An unique module combining various previous modules you have learnt by combing Linux administration, Hardware knowledge, Linux as OS, C/Computer programming areas. This is a complete module on Embedded OS, as of now no books are written on this with such practical aspects. Here is a consolidated material to get real hands-on perspective about building custom Embedded Linux distribution in ARM.
The Opcode or the operation code is the part of the instruction that specifies the operation to be performed by the instruction. The CPU decodes (understands) the instruction with the help of the opcode. Copy the link given below and paste it in new browser window to get more information on Operand and Opcode:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/operand-and-opcode.aspx
Introduction to the 16-bit PIC24F Microcontroller FamilyPremier Farnell
The document introduces Microchip's 16-bit PIC24F microcontroller family. It provides an overview of the PIC24F architecture, including its 16-bit CPU core, block diagram, and peripherals. It also discusses the development tool support for the PIC24F family, including hardware tools like the MPLAB ICD 2 in-circuit debugger/programmer and MPLAB REAL ICE in-circuit emulator.
Embedded Systems are basically Single Board Computers (SBCs) with limited and specific functional capabilities. All the components that make up a computer like the Microprocessor, Memory Unit, I/O Unit etc. are hosted on a single board. Their functionality is subject to constraints, and is embedded as a part of the complete device including the hardware, in contrast to the Desktop and Laptop computers which are essentially general purpose (Read more about what is embedded system). The software part of embedded systems used to be vendor specific instruction sets built in as firmware. However, drastic changes have been brought about in the last decade driven by the spurt in technology, and thankfully, the Moore’s Law. New, smaller, smarter, elegant but more powerful and resource hungry devices like Smart-phones, PDAs and cell-phones have forced the vendors to make a decision between hosting System Firmware or full-featured Operating Systems embedded with devices. The choice is often crucial and is decided by parameters like scope, future expansion plans, molecularity, scalability, cost etc. Most of these features being inbuilt into Operating Systems, hosting operating systems more than compensates the slightly higher cost overhead associated with them. Among various Embedded System Operating Systems like VxWorks, pSOS, QNX, Integrity, VRTX, Symbian OS, Windows CE and many other commercial and open-source varieties, Linux has exploded into the computing scene. Owing to its popularity and open source nature, Linux is evolving as an architecturally neutral OS, with reliable support for popular standards and features
This document provides an introduction to PIC microcontrollers. It discusses the architecture of PIC microcontrollers, including the 16C6x and 16C7x architectures. It describes the registers, memory, and instruction set of PIC microcontrollers. Some key points covered include the Harvard architecture, pipelining, addressing modes, arithmetic, logical, and conditional instructions. Peripherals like timers and interrupts are also mentioned.
This document introduces the STM32 microcontroller. It will cover the ARM Cortex processor, the STM32 system-on-chip, and its basic building blocks. The course outline includes introductions to the Cortex architecture, CMSIS standard, STM32 system architecture, peripherals, low power operation, safety features, flash memory, and development tools.
This document discusses ARM assembly language programming. It describes different types of instructions in ARM assembly like arithmetic operations, bitwise logical operations, register movement, comparison operations, and data transfer instructions. It also explains the use of immediate operands, shifted register operands, and multiply instructions. The document concludes that it provides the basic concepts of ARM assembly language programming using these different instruction sets.
presentation By Daroko blog-where IT learners Apply skills.
This topic an presentation will introduce you to Computer graphics hardware types.
---------------------------------
• Daroko blog (www.professionalbloggertricks.com)
• Presentation by Daroko blog, to see More tutorials more than this one here, Daroko blog has all tutorials related with IT course, simply visit the site by simply Entering the phrase Daroko blog (www.professionalbloggertricks.com) to search engines such as Google or yahoo!, learn some Blogging, affiliate marketing ,and ways of making Money with the computer graphic Applications(it is useless to learn all these tutorials when you can apply them as a student you know),also learn where you can apply all IT skills in a real Business Environment after learning Graphics another computer realate courses.ly
• Be practically real, not just academic reader
Do Not just learn computer graphics an close your computer tab and go away..
APPLY them in real business,
Visit Daroko blog for real IT skills applications,androind, Computer graphics,Networking,Programming,IT jobs Types, IT news and applications,blogging,Builing a website, IT companies and how you can form yours, Technology news and very many More IT related subject.
-simply google:Daroko blog(professionalbloggertricks.com)
The document provides an overview of Arduino, including what it is, common Arduino boards, digital and analog input/output, and example projects. Arduino is an open-source electronics prototyping platform that can be used to create interactive objects. It uses a simple hardware and software environment to program and develop prototypes. The Arduino Uno is one of the most commonly used boards, which contains an Atmega328 microcontroller, digital and analog pins, and can be programmed via USB. The document describes how to connect various components like LEDs, buttons, sensors and motors to an Arduino board.
This document discusses bootloaders, specifically the Universal Boot Loader (U-Boot). It provides an overview of bootloader concepts, U-Boot specifics, the U-Boot initialization sequence, how U-Boot passes arguments to the kernel, hands-on with U-Boot commands, the U-Boot source code structure, configuring and compiling U-Boot for a board, and porting U-Boot to support a new board.
Processor Organization and ArchitectureDhaval Bagal
This document discusses processor organization and architecture. It covers the stored program concept where both instructions and data are stored in memory. It describes the Von Neumann architecture, which includes a main memory, ALU, control unit, and I/O. It discusses the registers used in processor control and execution like the program counter, accumulator, and instruction register. Finally, it examines addressing modes like immediate, direct, indirect, register, displacement, and stack addressing.
This chapter discusses processor structure and function. It covers the basic components of a CPU including registers, instruction cycles, and data flow. Key points include:
- A CPU must fetch, interpret, fetch operands for, process, and write data from instructions. It uses registers for temporary storage and a program counter to keep track of instructions.
- Common registers include general purpose, data, address, condition code, control/status, and program status registers. General purpose registers can vary in number, size, and whether they are general or specialized use.
- An instruction cycle involves fetching an instruction from memory, decoding it, fetching operands, executing the instruction, and writing results. Pipelining and branch prediction are
The document discusses instruction set architecture (ISA), which is part of computer architecture related to programming. It defines the native data types, instructions, registers, addressing modes, and other low-level aspects of a computer's operation. Well-known ISAs include x86, ARM, MIPS, and RISC. A good ISA lasts through many implementations, supports a variety of uses, and provides convenient functions while permitting efficient implementation. Assembly language is used to program at the level of an ISA's registers, instructions, and execution order.
Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and ...jycazihi6460
Read Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C PDF Third Edition
[PDF] Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C Ebook by Yifeng Zhu.ePUB / PDF
Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition ePUB / PDF / Mobi / SCRIBD.COM
(.PDF).| I have been an embedded design engineer since 1990, just before the introduction cell phones. A lot has changed and some things remained the same. This is a great book and easy to understand especially if your new to embedded engineering. ... (Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition PDF Yifeng Zhu EBOOK).
Play Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C Third Edition AUDIOBOOK.Download Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C: Third Edition Zip / RAR PDF.
Embedded Systems with ARM Cortex-M Microcontroller
This document provides an introduction to microcontrollers. It defines microcontrollers as small computers capable of performing specific tasks, like in appliances. Microcontrollers contain a CPU core, memory, input/output ports, timers and other peripherals on a single chip. They are classified as either microcontroller units (MCU) or microprocessor units (MPU) depending on whether external components are needed. Common microcontroller components and their functions are described, along with factors to consider when choosing a microcontroller for an application.
The document summarizes the state of the HelenOS operating system. The latest release, version 0.5.0 from August 2012, included significant hardware support improvements and integration of development branches for USB, networking, and file systems. Upcoming work focuses on graphics, IPC improvements, and self-hosting capabilities like compilers and virtual machines. Long-term goals include a graphical user interface, additional device support, and using HelenOS as both a hosted and hosting platform for Xen.
What Could Microkernels Learn from Monolithic Kernels (and Vice Versa)Martin Děcký
Some developers of both microkernel and monolithic operating systems view the design of their system as absolutely superior to the other design. This black-white thinking and "holy war" attitude, while understandable to a certain degree, makes it hard to to acknowledge that one size does not necessarily fit all. Rather than striving for an unreachable goal of creating the best operating system design for all possible use cases it is vital to understand and reflect the trade-offs of the use cases at hand. This talk focuses on a few features and properties of the current monolithic operating systems that could be an inspiration for the current microkernel operating systems and vice versa. The talk should also initiate a discussion about some "non-goals" of microkernel operating systems that are nevertheless sometimes presented as goals of microkernel operating systems, to the detriment of its own cause.
El documento clasifica los elementos como obligatorios u opcionales para un proyecto. Algunos elementos son necesarios mientras que otros son opcionales y no requeridos.
La rúbrica contiene 5 criterios para autoevaluar una infografía: título, orden y claridad, licencia, tipografía y color, y seguridad. Cada criterio se clasifica en una escala del 1 al 4 para indicar el nivel de calidad. La rúbrica provee una guía para que el autor reflexione sobre su trabajo y identifique áreas de mejora.
Embedded Fest 2019. Wei Fu. Linux on RISC-V--Fedora and Firmware in practiceEmbeddedFest
The document discusses Fedora and firmware development for RISC-V platforms. It provides an overview of boot processes, toolchains, and images for running Fedora natively on RISC-V hardware. Key points include: the current boot flow uses OpenSBI and U-Boot firmware with EDK2; toolchain and QEMU packages are available to build Fedora via cross-compilation or natively; and Fedora images have been tested on various RISC-V boards running on QEMU or directly on hardware like the SiFive Unleashed.
Lessons Learned from Porting HelenOS to RISC-VMartin Děcký
HelenOS is an open source operating system based on the microkernel multiserver design principles. One of its goals is to provide excellent target platform portability. From the time of its inception, HelenOS already supported 4 different hardware platforms and currently it supports platforms as diverse as x86, SPARCv9 and ARM. This talk presents practical experiences and lessons learned from porting HelenOS to RISC-V.
While the unprivileged (user space) instruction set architecture of RISC-V has been declared stable in 2014, the privileged instruction set architecture is technically still allowed to change in the future. Likewise, many major design features and building blocks of HelenOS are already in place, but no official commitment to ABI or API stability has been made yet. This gives an interesting perspective on the pros and cons of both HelenOS and RISC-V. The talk also points to some possible research directions with respect to hardware/software co-design.
This document discusses using fuzzing to generate tests for RISC-V compliance testing. It proposes extending an LLVM-based fuzzer with custom mutators and coverage metrics tailored for RISC-V. Experimental results found bugs in several RISC-V simulators, demonstrating the effectiveness of fuzzing for negative compliance testing. The approach generates platform-independent assembly tests and filters invalid tests. It leverages an open-source RISC-V virtual prototype for test execution.
Linux on RISC-V with Open Hardware (ELC-E 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. I will highlight that OpenHW Group has adopted the PULP Ariane from ETH Zurich for its Core-V CVA64 implementation. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2020 and 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Linux on RISC-V with Open Source Hardware (Open Source Summit Japan 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Google Slides link https://tinyurl.com/y6j8lfyz
RISC-V-The Open New-Era of Computing-04-19-202.pptxAzharZahid1
This document discusses RISC-V, an open instruction set architecture (ISA) for processors. It provides an overview of RISC-V including its benefits over legacy ISAs such as design freedom, no license fees, and a growing ecosystem. The adoption of RISC-V is growing rapidly across industries like cloud, automotive, IoT, and more. Membership in RISC-V International provides benefits like technical insight, strategic advantage, and engagement with the global developer community.
The document discusses updates to the POSIX and C standards. Regarding POSIX, it summarizes the new features in POSIX:2008, including expanded API sets derived from Linux standards. For C, it outlines proposals and changes in C1X, the next revision of the C standard, such as new character types for UTF-16/32, bounds-checking interfaces, and dynamic memory allocation functions. It provides status updates on implementations in various operating systems.
Designing RISC-V-based Accelerators for next generation Computers (DRAC) is a 3-year project (2019-2022) funded by the ERDF Operational Program of Catalonia 2014-2020. DRAC will design, verify, implement and fabricate a high performance general purpose processor that will incorporate different accelerators based on the RISC-V technology, with specific applications in the field of post-quantum security, genomics and autonomous navigation. In this talk, we will provide an overview of the main achievements in the DRAC project, including the fabrication of Lagarto, the first RISC-V processor developed in Spain.
Evaluating HPX and Kokkos on RISC-V Using an Astrophysics Application Octo-TigerPatrick Diehl
In recent years, computers based on the RISC-V architecture have raised broad interest in the high-performance computing (HPC) community. As the RISC-V community develops the core instruction set architecture (ISA) along with ISA extensions, the HPC community has been actively ensuring HPC applications and environments are supported. In this context, assessing the performance of asynchronous many-task runtime systems (AMT) is important. We describe our experience with porting of a full 3D adaptive mesh-refinement, multi-scale, multi-model, and multi-physics application, Octo-Tiger, that is based on the HPX AMT, and we explore its performance characteristics on different RISC-V systems. The demonstrated results confirm that Octo-Tiger shows good scaling behavior on all tested systems. We, however, expect that exceptional hardware support based on dedicated ISA extensions (such as single-cycle context switches, extended atomic operations, and direct support for HPX's global address space) would allow for even better performance results.
RISC-V International is a global nonprofit organization founded in 2015 to support the free and open RISC-V instruction set architecture. It now has over 2,000 members in more than 70 countries. RISC-V aims to deliver a new level of free, extensible software and hardware freedom by supporting an open instruction set architecture. The organization is working to define technical standards and promote adoption across industries such as data centers, AI, automotive, and IoT.
seL4 is an open source, high-assurance microkernel that has been ported to run on RISC-V processors. It is one of the most secure and fastest microkernels available. seL4 has formal mathematical proofs of functional correctness and security properties. It is now available to use on RISC-V, making it the only operating system kernel for RISC-V that has undergone this level of formal verification. The porting process revealed that RISC-V's regular architecture makes the kernel code more simple and similar in size to ARM-based kernels compared to x86 kernels.
The document introduces RISC-V, an open instruction set architecture originated at UC Berkeley, outlines its design goals of being freely available and suitable for direct hardware implementation, and describes aspects of its ISA design including its load-store architecture, lack of condition codes, and support for 32, 64, and 128-bit addressing as well as its calling convention for passing arguments in registers and on the stack.
The document discusses Fedora on RISC-V, including:
1) The history and status of Fedora on RISC-V, including bootstrapping efforts and supported targets like QEMU and various RISC-V boards.
2) Details on the toolchain, QEMU, libvirt/VM tools, and development environment for building and running Fedora on RISC-V.
3) The boot flow and build process for firmware like OpenSBI and U-Boot when creating Fedora images for RISC-V platforms.
Deployment of an HPC Cloud based on Intel hardwareIntel IT Center
The document discusses a potential HPC cloud solution using Intel hardware for a technical university. It describes the customer's requirements for an IaaS solution that provides both physical and virtual deployment of computing resources and applications. The proposed solution involves using IBM software like PCM-AE, PAC and LSF on an Intel-based hardware cluster from transtec to provide self-service provisioning and management of HPC resources for the university's users. The implementation would include features like integration with the university's LDAP directory and deployment of Linux and Windows virtual clusters.
An embedded system is a microprocessor-based system designed to perform specific tasks and embedded as a component in a larger system. Common application areas include automotive electronics, aircraft electronics, trains, and telecommunications. The key design challenge is to optimize numerous design metrics like unit cost, size, performance, power consumption, and flexibility simultaneously. Common integrated circuit technologies used include full-custom/VLSI, semi-custom ASICs, and programmable logic devices like FPGAs. VHDL and Verilog are hardware description languages used to model and simulate the system at different levels of abstraction from transistors to functional behavior.
This document discusses Linux running on open source hardware using RISC-V processors and FPGAs. RISC-V is an open instruction set that provides an alternative to proprietary architectures like ARM. Projects are working to run Linux on low-cost RISC-V chips from SiFive and Kendryte. FPGAs can also run a Linux-capable RISC-V soft core called VexRiscv using open source tools. Several open source boards have been developed for the Lattice ECP5 FPGA featuring RISC-V support.
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Hardware/Software Co-Design for Efficient Microkernel ExecutionMartin Děcký
While the performance overhead of IPC in microkernel multiserver operating systems is no longer considered a blocker for their practical deployment (thanks to many optimization ideas that have been proposed and implemented over the years), it is undeniable that the overhead still does exist and the more fine-grained the architecture of the operating system is (which is desirable from the reliability, dependability, safety and security point of view), the more severe performance penalties due to the IPC overhead it suffers. A closely related issue is the overhead of handing hardware interrupts in user space device drivers. This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
One reason for the IPC overhead is the fact that current hardware and CPUs were never designed with microkernel multiserver operating systems in mind, but they were rather fitted for the traditional monolithic operating systems. This calls for an out-of-the-box thinking while designing instruction set architecture (ISA) extensions and other hardware features that would support (a) efficient communication between isolated virtual address spaces using synchronous and asynchronous IPC primitives, and (b) treating object references (e.g. capability references) as first-class entities on the hardware level. A good testbed for evaluating such approaches (with the potential to be eventually adopted as industry standard) is the still unspecified RV128 ISA (128-bit variant of RISC-V).
This talk discusses some specific hardware/software co-design ideas to improve the performance of microkernel multiserver operating systems.
Microkernels in the Era of Data-Centric ComputingMartin Děcký
Martin Děcký presented on microkernels in the era of data-centric computing. He discussed how emerging memory technologies and near-data processing can break away from the von Neumann architecture. Near-data processing provides benefits like reduced latency, increased throughput, and lower energy consumption. This leads to more distributed and heterogeneous systems that are well-matched to multi-microkernel architectures, with microkernels providing isolation and message passing between cores. The talk outlined an incremental approach from initial workload offloading to developing a full multi-microkernel system.
Formal Verification of Functional CodeMartin Děcký
This document discusses formal verification of functional code. It begins with motivations for formal verification like improving software dependability for mission-critical and safety-critical systems. It then provides an overview of formal verification, describing it as mathematically proving properties of a system's mathematical model. The document discusses examples of formal verification that programmers may already be familiar with, like proving properties of algorithms. It also covers formal verification methods in more depth, like model checking, theorem proving, and temporal logic. Finally, it discusses examples of projects that used formal verification like miTLS, F*, and seL4 microkernel.
This document discusses various techniques for instrumenting and monitoring computer systems, including interactive debugging, profiling, tracing, and post-mortem analysis. It describes approaches like inserting breakpoints, collecting stack traces, and analyzing core dumps. Dynamic tracing tools allow instrumenting running systems with minimal overhead through techniques like DTrace and SystemTap, which use probes to monitor events like system calls and kernel functions.
FOSDEM 2013: Operating Systems Hot TopicsMartin Děcký
The document discusses operating systems topics presented by Martin Děcký at FOSDEM 2013. It covers reliability, robustness, and dependability in operating systems. It discusses challenges for monolithic and microkernel systems and promises of formal verification. It also addresses topics like multicore/manycore systems, big data file systems, and ongoing work with the HelenOS microkernel.
Monitoring and Managing Anomaly Detection on OpenShift.pdfTosin Akinosho
Monitoring and Managing Anomaly Detection on OpenShift
Overview
Dive into the world of anomaly detection on edge devices with our comprehensive hands-on tutorial. This SlideShare presentation will guide you through the entire process, from data collection and model training to edge deployment and real-time monitoring. Perfect for those looking to implement robust anomaly detection systems on resource-constrained IoT/edge devices.
Key Topics Covered
1. Introduction to Anomaly Detection
- Understand the fundamentals of anomaly detection and its importance in identifying unusual behavior or failures in systems.
2. Understanding Edge (IoT)
- Learn about edge computing and IoT, and how they enable real-time data processing and decision-making at the source.
3. What is ArgoCD?
- Discover ArgoCD, a declarative, GitOps continuous delivery tool for Kubernetes, and its role in deploying applications on edge devices.
4. Deployment Using ArgoCD for Edge Devices
- Step-by-step guide on deploying anomaly detection models on edge devices using ArgoCD.
5. Introduction to Apache Kafka and S3
- Explore Apache Kafka for real-time data streaming and Amazon S3 for scalable storage solutions.
6. Viewing Kafka Messages in the Data Lake
- Learn how to view and analyze Kafka messages stored in a data lake for better insights.
7. What is Prometheus?
- Get to know Prometheus, an open-source monitoring and alerting toolkit, and its application in monitoring edge devices.
8. Monitoring Application Metrics with Prometheus
- Detailed instructions on setting up Prometheus to monitor the performance and health of your anomaly detection system.
9. What is Camel K?
- Introduction to Camel K, a lightweight integration framework built on Apache Camel, designed for Kubernetes.
10. Configuring Camel K Integrations for Data Pipelines
- Learn how to configure Camel K for seamless data pipeline integrations in your anomaly detection workflow.
11. What is a Jupyter Notebook?
- Overview of Jupyter Notebooks, an open-source web application for creating and sharing documents with live code, equations, visualizations, and narrative text.
12. Jupyter Notebooks with Code Examples
- Hands-on examples and code snippets in Jupyter Notebooks to help you implement and test anomaly detection models.
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
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Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Climate Impact of Software Testing at Nordic Testing DaysKari Kakkonen
My slides at Nordic Testing Days 6.6.2024
Climate impact / sustainability of software testing discussed on the talk. ICT and testing must carry their part of global responsibility to help with the climat warming. We can minimize the carbon footprint but we can also have a carbon handprint, a positive impact on the climate. Quality characteristics can be added with sustainability, and then measured continuously. Test environments can be used less, and in smaller scale and on demand. Test techniques can be used in optimizing or minimizing number of tests. Test automation can be used to speed up testing.
Unlock the Future of Search with MongoDB Atlas_ Vector Search Unleashed.pdfMalak Abu Hammad
Discover how MongoDB Atlas and vector search technology can revolutionize your application's search capabilities. This comprehensive presentation covers:
* What is Vector Search?
* Importance and benefits of vector search
* Practical use cases across various industries
* Step-by-step implementation guide
* Live demos with code snippets
* Enhancing LLM capabilities with vector search
* Best practices and optimization strategies
Perfect for developers, AI enthusiasts, and tech leaders. Learn how to leverage MongoDB Atlas to deliver highly relevant, context-aware search results, transforming your data retrieval process. Stay ahead in tech innovation and maximize the potential of your applications.
#MongoDB #VectorSearch #AI #SemanticSearch #TechInnovation #DataScience #LLM #MachineLearning #SearchTechnology
Cosa hanno in comune un mattoncino Lego e la backdoor XZ?Speck&Tech
ABSTRACT: A prima vista, un mattoncino Lego e la backdoor XZ potrebbero avere in comune il fatto di essere entrambi blocchi di costruzione, o dipendenze di progetti creativi e software. La realtà è che un mattoncino Lego e il caso della backdoor XZ hanno molto di più di tutto ciò in comune.
Partecipate alla presentazione per immergervi in una storia di interoperabilità, standard e formati aperti, per poi discutere del ruolo importante che i contributori hanno in una comunità open source sostenibile.
BIO: Sostenitrice del software libero e dei formati standard e aperti. È stata un membro attivo dei progetti Fedora e openSUSE e ha co-fondato l'Associazione LibreItalia dove è stata coinvolta in diversi eventi, migrazioni e formazione relativi a LibreOffice. In precedenza ha lavorato a migrazioni e corsi di formazione su LibreOffice per diverse amministrazioni pubbliche e privati. Da gennaio 2020 lavora in SUSE come Software Release Engineer per Uyuni e SUSE Manager e quando non segue la sua passione per i computer e per Geeko coltiva la sua curiosità per l'astronomia (da cui deriva il suo nickname deneb_alpha).
Building Production Ready Search Pipelines with Spark and MilvusZilliz
Spark is the widely used ETL tool for processing, indexing and ingesting data to serving stack for search. Milvus is the production-ready open-source vector database. In this talk we will show how to use Spark to process unstructured data to extract vector representations, and push the vectors to Milvus vector database for search serving.
Unlocking Productivity: Leveraging the Potential of Copilot in Microsoft 365, a presentation by Christoforos Vlachos, Senior Solutions Manager – Modern Workplace, Uni Systems
Infrastructure Challenges in Scaling RAG with Custom AI modelsZilliz
Building Retrieval-Augmented Generation (RAG) systems with open-source and custom AI models is a complex task. This talk explores the challenges in productionizing RAG systems, including retrieval performance, response synthesis, and evaluation. We’ll discuss how to leverage open-source models like text embeddings, language models, and custom fine-tuned models to enhance RAG performance. Additionally, we’ll cover how BentoML can help orchestrate and scale these AI components efficiently, ensuring seamless deployment and management of RAG systems in the cloud.
CAKE: Sharing Slices of Confidential Data on BlockchainClaudio Di Ciccio
Presented at the CAiSE 2024 Forum, Intelligent Information Systems, June 6th, Limassol, Cyprus.
Synopsis: Cooperative information systems typically involve various entities in a collaborative process within a distributed environment. Blockchain technology offers a mechanism for automating such processes, even when only partial trust exists among participants. The data stored on the blockchain is replicated across all nodes in the network, ensuring accessibility to all participants. While this aspect facilitates traceability, integrity, and persistence, it poses challenges for adopting public blockchains in enterprise settings due to confidentiality issues. In this paper, we present a software tool named Control Access via Key Encryption (CAKE), designed to ensure data confidentiality in scenarios involving public blockchains. After outlining its core components and functionalities, we showcase the application of CAKE in the context of a real-world cyber-security project within the logistics domain.
Paper: https://doi.org/10.1007/978-3-031-61000-4_16
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“An Outlook of the Ongoing and Future Relationship between Blockchain Technologies and Process-aware Information Systems.” Invited talk at the joint workshop on Blockchain for Information Systems (BC4IS) and Blockchain for Trusted Data Sharing (B4TDS), co-located with with the 36th International Conference on Advanced Information Systems Engineering (CAiSE), 3 June 2024, Limassol, Cyprus.
TrustArc Webinar - 2024 Global Privacy SurveyTrustArc
How does your privacy program stack up against your peers? What challenges are privacy teams tackling and prioritizing in 2024?
In the fifth annual Global Privacy Benchmarks Survey, we asked over 1,800 global privacy professionals and business executives to share their perspectives on the current state of privacy inside and outside of their organizations. This year’s report focused on emerging areas of importance for privacy and compliance professionals, including considerations and implications of Artificial Intelligence (AI) technologies, building brand trust, and different approaches for achieving higher privacy competence scores.
See how organizational priorities and strategic approaches to data security and privacy are evolving around the globe.
This webinar will review:
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2. 2Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projects
RISC-V is an instruction set architecture,
HelenOS is an operating system
3. 3Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projects
RISC-V is an instruction set architecture,
HelenOS is an operating system
Both originally started in academia
But with real-world motivations and ambitions
Both still in the process of maturing
Some parts already fixed, other parts can be still
affected
4. 4Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projects
RISC-V is an instruction set architecture,
HelenOS is an operating system
Both originally started in academia
But with real-world motivations and ambitions
Both still in the process of maturing
Some parts already fixed, other parts can be still
affected
→ Mutual evaluation of fitness
5. 5Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Martin Děcký
Computer science researcher
Operating systems
Charles University in Prague
Co-author of HelenOS (since 2004)
Original author of the PowerPC port
6.
7. 7Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V in a NutshellRISC-V in a Nutshell
Free (libre) instruction set architecture
BSD license, in development since 2014
Goal: No royalties for analyzing, designing,
manufacturing and selling chips (and related
software)
http://riscv.org
8. 8Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V in a Nutshell (2)RISC-V in a Nutshell (2)
Based on reduced instruction set (RISC) principles
Design based on time-proven ideas, but avoiding
mistakes and anachronisms
High-performance Z-scale, Rocket and BOOM prototype
chips manufactured (at 45 nm and 28 nm)
Scalable and extendable clean-slate design
From small embedded systems (low-power minimal 32-bit
implementations)
To large computers (powerful implementations, 64-bit or
even 128-bit, SIMD, VLIW, etc.)
9. 9Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Context of RISC-VContext of RISC-V
Comparison with previous free ISAs
OpenRISC, OpenSPARC, LaticeMico32, MMIX,
Amber, LEON
Goals of RISC-V
BSD instead of GPL
Modularity and scalability
Supporting 32 bits and 64 bits (128 bits in the future)
Not just for research and education
10. 10Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Comparison with commercial ISAs
IA-32, AMD64, IA-64, ARM
Complex or rather complex
Intellectual property minefield
SPARC, POWER, MIPS
Still intellectual property minefield
Old patent-free ISAs
(ARMv2, Berkeley RISC, Stanford MIPS)
Obsolete
11. 11Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Comparison with commercial ISAs
Goals of RISC-V
Free
Relevant
State-of-the-art
Practical
Reasonable complexity
12. 12Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Who Is behind RISC-VWho Is behind RISC-V
UC Berkeley, Computer Science Division
Krste Asanović
Principal designer
David Patterson
Coined the term RISC and led the original Berkeley RISC
project (1980)
Later exploited in SPARC, Alpha and ARM
Co-author of DLX (with John Hennessy for Computer
Architecture: A Quantitative Approach)
Funding from DARPA, Intel, Microsoft and others
13.
14. 14Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Who Is behind RISC-V (2)Who Is behind RISC-V (2)
RISC-V Foundation
Non-profit corporation
Rick O'Connor (Executive Director)
http://riscv.net
Governing the evolution of RISC-V ISA
Standardization of extensions
Intellectual property matters (patents, logos, trademarks, etc.)
Founding members
Google, Hewlett Packard Enterprise, Lattice, Oracle, lowRISC
and others
15. 15Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Implementors of RISC-VImplementors of RISC-V
Indian Institute of Technology Madras
Plan to produce six CPU designs based on RISC-V
Bluespec
Preliminary plan to produce RISC-V based CPUs
lowRISC
Non-profit organization (cooperating with University of
Cambridge and Raspberry Pi Foundation)
Implementing open source SoC based on 64 bit RISC-V
(scheduled for 2017)
Tagged memory
16. 16Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of RISC-VFeatures of RISC-V
RISC architecture
Word size of 32 or 64 bits
Word size of 128 bits possible in the future
32 general-purpose registers (word-sized)
Load/store architecture
R0 always contains 0
8 bit and 16 bit arithmetics via sign extension
Plain register file (no register windows, register stacks, etc.)
Optional 32 floating point registers (IEEE 754)
Little-endian, byte-addressable memory
17. 17Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of RISC-V (2)Features of RISC-V (2)
RISC architecture
32-bit instructions
Orthogonal instruction set
Limited number of instruction templates
Fixed positions for specific opcode bits for fast decoding and
immediate argument sign extension
Three-argument instructions
Synthetic instructions
R0 used to provide two-argument synthetic instructions
Implicit stack
Mandatory alignment of memory accesses
18. 18Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of RISC-V (3)Features of RISC-V (3)
Beyond RISC
No branch delay slots
No condition codes, flag registers, carry bits
Conditions evaluated in branch instructions
Practical design of instruction encoding
Opcode bits designed to reduce the number of
multiplexers
19. 19Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of RISC-V (4)Features of RISC-V (4)
Beyond RISC
Native support for position-independent code
Address calculation relative to the program counter
Fused multiply-add by future accelerated decoding
Instruction set extentions
Mandatory instruction set
Optional (non-conflicting) extentions
Green-field and brown-field allocations
20. 20Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Instruction SetRISC-V Instruction Set
op (7) rd (5) fnct3 (3) rs1 (5) rs2 (5) fnct7 (7)R-type
I-type op (7) rd (5) fnct3 (3) rs1 (5) immediate (12)
RV32I (Base Integer Instruction Set)
S-type op (7) imm (5) fnct3 (3) rs1 (5) rs2 (5) imm (7)
U-type op (7) rd (5) imm (20)
21. 21Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (2)RISC-V Instruction Set (2)
RV32I (Base Integer Instruction Set)
Computational
addition, subtraction, set less than, and, or, xor, shift left logical, shift right
logical, shift right arithmetic, load upper immediate, add upper immediate
to PC, no-op
Control transfer
unconditional jump (with link), branch (equal, not equal, less than, greater
or equal)
Load and store
load, store, memory fence
System
system call, breakpoint, CPU cycles, retired CPU instructions, wall-clock time
22. 22Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (3)RISC-V Instruction Set (3)
RV64I (Base Integer Instruction Set)
Essentially the same instructions as in RV32I (some variations
accommodating the 64-bit word size)
Standard extensions
M (Integer Multiplication and Division)
A (Atomic Instructions)
load-reserved, store-conditional, atomic memory operation (swap,
addition, and, or, xor, max, min)
F (Single-Precision Floating Point)
D (Double-Precision Floating Point)
General purpose ISA: RV64IMAFD = RV64G (164 instructions)
23. 23Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (4)RISC-V Instruction Set (4)
More standard extensions
Q (Quad-Precision Floating Point)
D (Decimal Floating Point)
C (16-bit Compressed Instructions)
B (Bit Manipulations)
T (Transactional Memory)
P (Packed-SIMD)
RV128I (Base Integer Instruction Set)
Sketched
24. 24Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of RISC-V (5)Features of RISC-V (5)
Beyond RISC
Reserved opcodes for non-32-bit instructions
64-bit instructions, variable-length instructions, even
instruction bundles (VLIW)
Compressed instruction set
16-bit instructions
No separate execution mode necessary
(intermixed with 32-bit instructions)
Code on average 20 % smaller than x86,
2 % smaller than ARM Thumb-2
29. 29Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Privileged Software StacksRISC-V Privileged Software Stacks
Privilege Levels
Machine (M)
Hypervisor (H)
Supervisor (S)
Same set of privileged
instructions
User/Application (U)
Each level own set of
Control and Status
Registers (CSR)
4×1024 I/O space
Supported combinations
M
Embedded systems
M+U
Embedded systems
with protection
M+S+U
Standard OS
M+H+S+U
Standard OS with
virtualization
30. 30Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V Machine-Level ISARISC-V Machine-Level ISA
CSRs
CPU and hardware thread ID
Machine status (privilege level, interrupts)
Memory management status
No memory translation
Single base-and-bound
Separate instruction/data base-and-bound
32-bit virtual addresses (2-level hierarchical page tables)
39-bit virtual addresses (3-level hierarchical page tables)
48-bit virtual addresses (4-level hierarchical page tables)
31.
32. 32Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS in a NutshellHelenOS in a Nutshell
Microkernel multiserver operating system
BSD license, in development since 2004
Goal: General-purpose usability, not limited by any
specific use case or hardware platform,
component-based design and implementation
http://helenos.org
33. 33Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS in a Nutshell (2)HelenOS in a Nutshell (2)
architectureindependent
sharedarchitecture
dependent
architecture
dependent
bootstrap
routines
CPU
mgmt
atomics
&
barriers
I/O
mgmt
platform
memory
mgmt
platform
drivers
debugging
support
context
switching
interrupt
handling
platform
library
routines
shared
platform
drivers
shared
debugging
support
hierarchical
page table
support
global page
hash table
support
hardware
layer
abstraction
kernel
unit
tests
memory
backends
memory
zones
mgmt
frame
allocator
slab
allocator
address
space
mgmt
memory
reservation
spinlocks
wait
queues
work
queues
interrupt &
syscall
dispatch
thread
scheduler
thread &
task
mgmt
kernel
lifecycle
mgmt
lists,
trees,
bitmaps
concurrent
hash
table
generic
resource
allocator
ELF
loader
string
routines
misc
routines
kernel
console
IPC
kernel
log
hardware
resource
mgmt
system
information
cycle &
time
mgmt
tracing
support
read-
copy-
update
task
capabilities
cache
coherency
synchro-
nization
interface
kernel
naming
service
loader task
monitor
kloglocation
service logger
device
manager
device drivers
client
session
vterm bdsh
vfs
file system
drivers
FAT exFAT ext4
ISO 9660 UDF MINIX FS
TMPFS Location FS
init
transport
layer protocols
tcp udp
link layer
protocols
loopip ethip
slip
inetsrv
networking
management
dnsrsrv dhcp
nconfsrv
human interface
clipboard audio
outputinput
console compositor
remote
console
remote
framebuffer
Kernel subsystems System components
34. 34Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Features of HelenOSFeatures of HelenOS
Design based on explicit design principles
Non-fundamentalistic metaprinciple
General-purpose principle
Microkernel principle
Full-fledged principle
Multiserver principle
Split of mechanism and policy principle
Encapsulation principle
Portability principle
Modularity principle
35. 35Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Portability of HelenOSPortability of HelenOS
Supporting 8 hardware platforms
IA-32, AMD64, IA-64, ARM, PowerPC, MIPS,
SPARC V8, SPARC V9
Portability case studies
Port to ARM in 53 days by 3 developers
Port to SPARC V8 in 13 weeks by 1 developer
Porting efforts improve portability
Portability simplifies future porting efforts
36. 36Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Portability of HelenOS (2)Portability of HelenOS (2)
Portability design principle
“Do not be biased by any single hardware
platform”
Reusable abstract algorithms
4-level page tables
ASID LRU management
interrupt routing
Hardware Abstraction Layer defined by a virtual
abs32le port
38. 38Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS abs32leHelenOS abs32le
NO_TRACE ATOMIC static inline void atomic_inc(atomic_t *val)
WRITES(&val->count)
REQUIRES_EXTENT_MUTABLE(val)
REQUIRES(val->count < ATOMIC_COUNT_MAX)
{
/*
* On real hardware the increment has to be done
* as an atomic action.
*/
val->count++;
}
Atomic increment behavior summary on abs32le
plain C behavior summary
semantic annotations
39. 39Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS RISC-V PortHelenOS RISC-V Port
Reasons
Future combined verification of HW/SW correctness
Current status
Started in January 2016
Finished: Boot loader, initial memory management
setup, kernel hand-off
Everything compiles
Memory management data structures in place
18 hours (net)
40. 40Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS RISC-V PortHelenOS RISC-V Port
Demo
41. 41Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (2)HelenOS RISC-V Port (2)
General approach
Cloning the abs32le virtual port
Changing names, endianity, word width, primitive types,
linker script and other basic definitions
Adding the new platform to the build system
Adding basic options to HelenOS.config
Adding the compiler toolchain to tools/autotool.py
Checking that everything compiles (mostly trivial)
Gradually adding actual working implementation
42. 42Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (3)HelenOS RISC-V Port (3)
#define EM_RISCV 243 /* RISC-V */
abi/include/abi/elf.h
.org DEFAULT_MTVEC + TRAP_VECTOR_RESET
start:
/* Set up stack, create stack frame */
la sp, boot_stack + BOOT_STACK_SIZE
addi sp, sp, -16
j bootstrap
#define EM_RISCV 243 /* RISC-V */#define EM_RISCV 243 /* RISC-V */
boot/arch/riscv64/src/asm.S
44. 44Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (4)HelenOS RISC-V Port (4)
Near future
Basic kernel functionality
Interrupt/exception handling
Context switching, atomics
ETA: 18 – 24 hours (net)
Basic user space functionality
Thread-local storage
User space context switching
I/O
ETA: 18 – 24 hours (net)
45. 45Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Current State of RISC-VCurrent State of RISC-V
User-level ISA
Version 2.0, frozen since May 6th 2014
Compressed ISA
Version 1.9, draft, to be frozen soon
Privileged ISA
Version 1.7, draft, expected to be frozen in mid-2016 or
later
Vector ISA
Only sketched so far
46. 46Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Current State of RISC-V (2)Current State of RISC-V (2)
Holes in the specification
Memory consistency model
Application Binary Interface (ABI)
Performance counters
Hypervisor support
Formal specification (for verification)
47. 47Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Current State of RISC-V (3)Current State of RISC-V (3)
Holes in the specification
Reference platform
Standard I/O locations (standard memory map)
Debugging support (hardware breakpoints, JTAG)
Interrupt controller, timer, RTC, reset mechanism, DMA,
IOMMU
Power management
Standard firmware (standard device tree)
Standard boot loader
48. 48Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Current State of RISC-V (4)Current State of RISC-V (4)
Available tooling
Development tools
GNU Binutils, GCC, GDB, LLVM, clang, Go, libf
Enviroments
Newlib, glibc
Simulators / Emulators
Spike (MSIM-like), QEMU (80 % of privileged ISA),
ANGEL (JavaScript), Simics, trace32
Not upstreamed yet
49. 49Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Current State of RISC-V (5)Current State of RISC-V (5)
Software stack
Firmware
coreboot (on Spike, upstreamed)
UEFI (a hack of EDKII on QEMU with PC peripherals)
Operating systems
Linux (with busybox), Yocto/OpenEmbedded
FreeBSD, NetBSD (to be upstreamed soon)
seL4
HelenOS (work-in-progress)
50. 50Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Preliminary Porting ObservationsPreliminary Porting Observations
RISC-V is like a mixture of MIPS and AMD64
HelenOS generic 4-level page tables suitable for
RISC-V
RISC-V compressed access permission field in page
tables is more cumbersome than access bits
No forced platform-independent code change
expected
HelenOS and RISC-V evaluate as good match for
each other
51. 51Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Preliminary Porting ObservationsPreliminary Porting Observations
RISC-V underspecification causes only minor
issues
Generally, the CPU specs are fine
“Reference platform” documented only in the
code of the Spike simulator
E.g. host-target interface implementing basic I/O
devices using CSRs
52. 52Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
ConclusionConclusion
RISC-V
Interesting and solid research/development effort
Great potential for both academia and industry
HelenOS
RISC-V port underway, no roadblock in sight
History of HelenOS portability improves future
portability
56. 56Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Context of RISC-VContext of RISC-V
Not the first free ISA, but the most degrees of
freedom
OpenRISC
2000, LGPL, based on DLX, fixed ISA (not extendable)
OpenSPARC
2005, GPL, based on UltraSPARC T1 (SPARC V9), fixed
configuration (i.e. number of cores, etc.)
LaticeMico32
2006, custom open source license (a mixture of several
licenses), 32-bit
57. 57Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Not the first free ISA, but the most degrees of
freedom
MMIX
2009, a non-free open source license, Donald Knuth, John
Hennessy and Richard Sites (inspired by Knuth's MIX), 64-bit,
for educational purposes
Amber
2010, LGPL, ARMv2 compatible (32-bit)
LEON
2000-2010, LGPL + dual licensing, SPARC V8 compatible (32-bit)
58. 58Martin Děcký, FOSDEM, January 30th
2016 Porting HelenOS to RISC-V
RISC-V in AcademiaRISC-V in Academia
Highlights of research projects based on RISC-V
Formal specification & verification
Chisel open source hardware construction language
[UC Berkeley]
Novel bespoke weak memory consistency models [MIT]
Novel manycore configurations [Gray Research]
First experimental photonic CPU [UC Berkeley]
Experimental ISA extensions [ETH Zürich]
Hardware loops
Faster ISA simulators using JIT [Cornell]