Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project.

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The FOSS EDA
ecosystem
(and GHDL)
A short introduction
Tristan Gingold – ISC 2020

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FOSS EDA Ecosystem
Free Open Source Software
Any software whose source code is
available for any (including commercial)
purpose.
Can be:
●
Used
●
Modified
●
Redistributed

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EDA
Electronic Design Automation
Any software to help (via automation) the
electronic hardware designer
This is a vast domain, so let’s clarify

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EDAPrinted
Circuit
Board
PCBs
Integrated
Circuit
ICs
Ex:
Analog
Coriolis
Magic Qflow

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What are Integrated
Circuits ?
●
Logical gates
●
Flip-flop and latches
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Memories
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Wires
●
Some analog components (PLLs, pads, …)
That’s the netlist!

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How are ICs designed ?
●
Not anymore by drawings
– Doesn’t scale
– Still used for high-level view
●
Use of Hardware Description Language
– Verilog/SystemVerilog
– VHDL

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The design flow
HDL
Simulation
Synthesis
Map
Place &
Route
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Write the design
●
Check the design
●
Generate a generic netlist
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Target specific netlist
●
Physical implementation

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ICs
Application
Specific IC
ASIC
Field
Programmable
Gate
Array
FPGA

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FOSS for the design flow
HDL
Simulation
Standard languages:
●
Verilog
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Verilator
●
Icarus Verilog
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VHDL
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GHDL
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nvc
New/DSL languages:
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Chisel
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SpinalHDL (Scala)
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Clash (Haskell)
●
MyHDL (Python)
●
...
Verification frameworks:
●
Cocotb (python)
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uvm
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osvvm
●
uvvm
●
vunit
●
...
Waveform viewer:
●
GtkWave

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FOSS for the design flow
Synthesis
Map
Place &
Route
Front-end:
●
Yosys
●
GHDL
●
ODIN-II
Yosys + ABC
Nextpnr
VPR

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Why FOSS EDA (1/2) ?
●
Prioprietary FPGA tool chains are complete
●
They are often free
– (at least for entry-level FPGA)
●
For many flows, they are still required
– Bitstreams are not documented
●
Vendor IPs are often encrypted
●
Ecosystem

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Why FOSS EDA (2/2) ?
●
Coherency if your design is also open-source
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Ideology – contribution
●
Price
●
Performance (in some cases)
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Avoid vendor-locking
●
Features
●
Support / Fixes time
●
Flexibility