FPGA• A field-programmable gate array (FPGA) is an integrated circuitdesigned to be configured by a designer after manufacturing.• It contain programmable logic components called "logic blocks“.
Why FPGA…• Efficient resources utilization• Very high complexities possible• Fast and efficient systems• The low non-recurring engineering costs relative to anASIC design
Vendors- Xilinx has traditionally been the FPGA leader.Altera is the second FPGA heavyweight.- Lattice Semiconductor focuses on low-cost, feature-optimized FPGAs and non-volatile, flash-based FPGAs.- Actel has antifuse and reprogrammable flash-based FPGAs.- QuickLogic has antifuse (programmable-only-once)products.- Cypress Semiconductor
XilinxXilinx is programmed to give you control. The companyis a top supplier of field-programmable gate arrays (FPGAs)and complex programmable logic devices (CPLDs).
The Xilinx FPGA Families:• Virtex Family: This family is advised for applications that demandshigher bandwidth and higher performance.• Spartan Family: This family is advised for low cost, low power, and highperformance for cost-sensitive applications which will be used in highamounts of productions.
• High Performance at different voltages• Footprint Compatibility- Devices within each family are compatible.• Low power consumption/high performance• Integrated Software• Technology independence- EDIF, VHDL, Verilog, SDF interfaces.Xilinx FPGAs - Generic Features
• Silicon Family Name: Virtex II, Spartan II Core Architecture:• Product Type: Programmer, In-Circuit• Supply Voltage: 5.25V• Synchronous Single and Dual-Port RAM• Internal Three-state buffers.• JTAG Boundary Scan• System performance to 80 MHz• 0.5 µ SRAM Process TechnologyXC4000
Application (Half Adder On VHDL)VHDL stands for VHSIC Hardware Definition Language where VHSICstands for Very High Speed Integrated Circuit.VHDL can be used for two purposes:•Synthesis•Simulation
VHDL CODE• library IEEE;use IEEE.STD_LOGIC_1164.ALL;• entity HALF_ADDER isPort ( A : in STD_LOGIC;B : in STD_LOGIC;SUM : out STD_LOGIC;CARRY : out STD_LOGIC);end HALF_ADDER;• architecture Behavioral of HALF_ADDER isbeginSUM <= A XOR B;CARRY <= A AND B;end Behavioral;