The document provides a detailed analysis of memory system design, focusing on memory chips and their interfacing with a microprocessor through various operational states like read and write. It outlines the requirements and configurations needed for specific memory sizes and bus widths, highlighting different cases where address and data lines correspond or differ. Examples are given for interfacing memory with microprocessors based on chip select and enable signals, using logical address spaces for effective memory management.

1. Memory System Design

2. Memory
2
Memory Chip
m w
2m × w
m: width of the address bus
w: width of the data bus
CS: Chip Select
OE: Output Enable
WE: Write Enable
Memory contains 2m locations
each of w bits
CS OE WE
CS
0
Chip is disabled
1
OE = 0
WE = 0
No Read/
No Write
OE = 0
WE = 1
Write operation
OE = 1
WE = 0
Read operation
OE = 1
WE = 1
Invalid
Address
m
Data
w

3. Access Example
Memory Chip
m = 3 w = 4
2m × w
CS OE WE
1 0 1 0
Memory contains 2m = 23 = 8
locations each of w = 4 bits
Data width = 4
000
0 0 0 1
0 0 0 0
1 0 1 1
001
010
011
1 1 1 1
100
0 0 1 1
1 0 0 0
0 0 1 1
101
110
111
m = 101 CS = 0 OE = 0 WE = 0
No read or write operation
Address
lines m
Data
lines w
m = 101 CS = 1 OE = 1 WE = 0
Read Operation at location 101
w3 w2 w1 w0
= 0 0 1 1
w3 w2 w1 w0
= 1 1 1 0
m = 111 CS = 1 OE = 0 WE = 1
Write Operation at location 111
1 1 1 0

4. Microprocessor
Microprocessor
Address lines (A)
Data lines (D)
R/W*
AS (Address strobe)
Address lines : To address a particular location in memory
R/W* : To perform a read (R/W* = 1) or a write operation (R/W* = 0)
Data lines: Direction of data determined by R/W* signal
AS = 1 Microprocessor has generated a valid address
AS = 0 The address is invalid

5. Microprocessor (Instruction Fetch)
Microprocessor
Address-lines (A)
Data lines (D)
R/W*
AS
Instruction Fetch
Read Operation (AS = 1, R/W* = 1)
Address-lines = [MAR] which is loaded with PC address
Data-lines = Content of memory at location specified by address

6. Microprocessor (Instruction Decode)
Microprocessor
Address-lines (A)
Data lines (D)
R/W*
AS
Instruction Decode
Does not need an operation from memory
AS = 0 Microprocessor does not need an access to memory

7. Microprocessor (Operand Store)
Microprocessor
Address-lines (A)
Data lines (D)
R/W*
AS
Operand Store (Destination is memory) MOV $1056, # $98
Address lines = $1056 (Addressing mode is absolute)
Data Lines = $98
AS = 1 Microprocessor generate a valid address
R/W* = 0 because it is a Write operation
Direction of data will be towards memory
$AB11
$1056
$0098

8. Case-1 Address lines and data lines are same A = m, D = w
Q: Memory requirement of microprocessor is 4KBytes and width of the data bus is 8
bits. Memory available is 212 × 8. How can we interface the memory with
microprocessor?
Memory Chip
m=12 w = 8
2m × w
CS OE WE
Memory requirement = 4 KB = 2A × D
22 × 210 Bytes = 2A × 8
22 × 210 × 23 = 2A × 8
212 × 8 = 2A × 8
A = 12
A = m = 12
D = w = 8
Microprocessor
A
D = 8 (D07-D00
)
2A × D
R/W*
AS
Memory available = 212 × 8
m = 12
w = 8

9. Case-1 Address lines and data lines are same A = m, D = w
A11-A00
D07-D00
2A × D
212 × 8
Microprocessor
R/W*
AS
w = 8
m=12
2m × w
212 × 8
Memory Chip
CS OE WE
R/W* = 1/0
0/1

10. Case-2 Address lines are different and data lines are same A > m, D = w
Q: Memory requirement of microprocessor is 16KBytes and width of the data bus is
8 bits. Memory available is 212 × 8. How can we interface the memory with
microprocessor?
Memory requirement = 16 KB = 2A × D
24 × 210 Bytes = 2A × 8
24 × 210 × 23 = 2A × 8
214 × 8 = 2A × 8
A = 14
A > m
D = w = 8
Memory available = 212 × 8 = 4KB
m = 12
w = 8
Memory Chip
m=12 w = 8
2m × w
CS OE WE
Microprocessor
A
D = 8 (D07-D00)
2A × D
R/W*
AS
214 × 8 = 22 × 212 × 8
214 × 8 = 4 × (212 × 8)
214 × 8 = 4 memory chips

11. Case-2 Address lines are different and data lines are same A > m, D = w
A13-A00 (14 bits)
D07-D00
2A × D
214 × 8
Microprocessor
R/W*
AS
w = 8
m=12 212 × 8
Memory Chip 1
CS1 OE1 WE1
w = 8
m=12 212 × 8
Memory Chip 2
CS2 OE2 WE2
w = 8
m=12 212 × 8
Memory Chip 3
CS3 OE3 WE3
w = 8
m=12 212 × 8
Memory Chip 4
CS4 OE4 WE4
• R/W* is connected to OE1, OE2, OE3 and OE4
• Invert of R/W* is connected to WE1, WE2, WE3
and WE4
A11-A00 (12 bits)
A13-A12 (2 bits)
2 to 4
decoder
A13
A12
En 00
01
10
11
CS1
CS2
CS3
CS4

12. Case-2 Address lines are different and data lines are same A > m, D = w
A13-A00 (14 bits)
D07-D00
2A × D
214 × 8
Microprocessor
16KB
16384 x 8
R/W*
AS
Memory Chip
(4KB)
4096 x 8
m=12 w = 8
212 × 8
CS OE WE
• Min Address is %0000 0000 0000 ($000)
• Max Address is %1111 1111 1111 ($FFF)
$F0 (%11110000)
Data width = 8 bits
$000
$23
$001
$67
$8C
$FFE
$FFF
(4095)
…
• Min Address is %00 0000 0000 0000 ($0000)
• Max Address is %11 1111 1111 1111 ($3FFF)
…
$68
$0000
…
$74
$0001
…
$93
$3FFE
$A2
$3FFF
Data width = 8 bits

13. Case-2
Memory Logical
address Space
212 × 8
$000
$FFF
…
Address lines are different and data lines are same A > m, D = w
$0000
$3FFF
…
Microprocessor Logical
address Space
214 × 8
requires 4 mem chips
Memory Chip 1
$0000
$0FFF
…
$1000
$1FFF
…
$2000
$2FFF
…
$3000
$3FFF
…
Memory Chip 2
Memory Chip 3
Memory Chip 4
Enabled (CS1) when A13-A12 = 00
Enabled when A13-A12 = 01
Enabled when A13-A12 = 10
Enabled when A13-A12 = 11
A = $1568 then
A13-A12 = $1 (%01)
A11-A00 = $568
A13-A12 will go to 2-to-4 decoder and CS2
will be enabled
A11-A00 will be provided to all memory chips
while memory chip 2 will provide the data
and the remaining chips disabled (CS1,
CS3, and CS4 are all assigned zero value)

14. Case-3 Address lines are same and data lines are different A = m, D > w
Q: Memory requirement of microprocessor is 16KBytes and width of the data bus is
32 bits. Memory available is 212 × 8. How can we interface the memory with
microprocessor?
Memory requirement = 16 KB = 2A × D
24 × 210 Bytes = 2A × 32
24 × 210 × 23 = 2A × 32
217 = 2A × 32
212 × 25 = 2A × 32
A = 12 this implies A = m
D = 32 this implies D > w
Memory available = 212 × 8 = 4KB
m = 12
w = 8
Memory Chip
m=12 w = 8
2m × w
CS OE WE
Microprocessor
A
D = 32 (D31-D00)
2A × D
R/W*
AS
16 KB = 214 × 8 = 22 × 212 × 8
214 × 8 = 4 × (212 × 8)
214 × 8 = 4 memory chips

15. Case-3 Address lines are same and data lines are same A = m, D > w
A = 12 (A11-A00)
D = 32 (D31-D00)
R/W*
AS
2A × D
212 × 32
Microprocessor
16KB
m=12 w = 8
CS OE WE
Memory
Chip 2
(4KB)
m=12 w = 8
CS OE WE
Memory
Chip 1
(4KB)
12 8
CS OE WE
Memory
Chip 4
(4KB)
12 8
CS OE WE
Memory
Chip 3
(4KB)
CS1, CS2, CS3, CS4
OE1, OE2, OE3, OE4
WE1, WE2, WE3, WE4
D31-D24 D23-D16 D15-D08 D07-D00

16. Case-4 Address and data lines are both different A > m, D > w
Please see page 76 of the notes
A > m
D > w
If A = m + n
If D = w + k
If n = 0 Case-1, Case-3 A = m
If k =0 Case-2
For n >=1 We need n to 2^n decoder We need 2^n
rows
You need D/w columns