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Introduction to
CMOS VLSI
Design
Lecture 21:
Scaling and Economics
David Harris
Harvey Mudd College
Spring 2004
21: Scaling and Economics Slide 2CMOS VLSI Design
Outline
 Scaling
– Transistors
– Interconnect
– Future Challenges
 VLSI Economics
21: Scaling and Economics Slide 3CMOS VLSI Design
Moore’s Law
 In 1965, Gordon Moore predicted the exponential
growth of the number of transistors on an IC
 Transistor count doubled
every year since invention
 Predicted > 65,000
transistors by 1975!
 Growth limited by power
[Moore65]
21: Scaling and Economics Slide 4CMOS VLSI Design
More Moore
 Transistor counts have doubled every 26 months for
the past three decades.
Year
Transistors
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro
Pentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
21: Scaling and Economics Slide 5CMOS VLSI Design
Speed Improvement
 Clock frequencies have also increased exponentially
– A corollary of Moore’s Law
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
ClockSpeed(MHz)
21: Scaling and Economics Slide 6CMOS VLSI Design
Why?
 Why more transistors per IC?
 Why faster computers?
21: Scaling and Economics Slide 7CMOS VLSI Design
Why?
 Why more transistors per IC?
– Smaller transistors
– Larger dice
 Why faster computers?
21: Scaling and Economics Slide 8CMOS VLSI Design
Why?
 Why more transistors per IC?
– Smaller transistors
– Larger dice
 Why faster computers?
– Smaller, faster transistors
– Better microarchitecture (more IPC)
– Fewer gate delays per cycle
21: Scaling and Economics Slide 9CMOS VLSI Design
Scaling
 The only constant in VLSI is constant change
 Feature size shrinks by 30% every 2-3 years
– Transistors become cheaper
– Transistors become faster
– Wires do not improve
(and may get worse)
 Scale factor S
– Typically
– Technology nodes
Year
0.1
1
10
1965 1970 1975 1980 1985 1990 1995 2000 2005
FeatureSize(µm)
10
6
3
1.5
1
0.8
0.6
0.35
0.25
0.18
0.13
0.09
2S =
21: Scaling and Economics Slide 10CMOS VLSI Design
Scaling Assumptions
 What changes between technology nodes?
 Constant Field Scaling
– All dimensions (x, y, z => W, L, tox)
– Voltage (VDD)
– Doping levels
 Lateral Scaling
– Only gate length L
– Often done as a quick gate shrink (S = 1.05)
21: Scaling and Economics Slide 11CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 12CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 13CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 14CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 15CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 16CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 17CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 18CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 19CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 20CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 21CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 22CMOS VLSI Design
Device Scaling
21: Scaling and Economics Slide 23CMOS VLSI Design
Observations
 Gate capacitance per micron is nearly independent
of process
 But ON resistance * micron improves with process
 Gates get faster with scaling (good)
 Dynamic power goes down with scaling (good)
 Current density goes up with scaling (bad)
 Velocity saturation makes lateral scaling
unsustainable
21: Scaling and Economics Slide 24CMOS VLSI Design
Example
 Gate capacitance is typically about 2 fF/µm
 The FO4 inverter delay in the TT corner for a
process of feature size f (in nm) is about 0.5f ps
 Estimate the ON resistance of a unit (4/2 λ)
transistor.
21: Scaling and Economics Slide 25CMOS VLSI Design
Solution
 Gate capacitance is typically about 2 fF/µm
 The FO4 inverter delay in the TT corner for a
process of feature size f (in nm) is about 0.5f ps
 Estimate the ON resistance of a unit (4/2 λ)
transistor.
 FO4 = 5 τ = 15 RC
 RC = (0.5f) / 15 = (f/30) ps/nm
 If W = 2f, R = 8.33 kΩ
– Unit resistance is roughly independent of f
21: Scaling and Economics Slide 26CMOS VLSI Design
Scaling Assumptions
 Wire thickness
– Hold constant vs. reduce in thickness
 Wire length
– Local / scaled interconnect
– Global interconnect
• Die size scaled by Dc ≈ 1.1
21: Scaling and Economics Slide 27CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 28CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 29CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 30CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 31CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 32CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 33CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 34CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 35CMOS VLSI Design
Interconnect Scaling
21: Scaling and Economics Slide 36CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 37CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 38CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 39CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 40CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 41CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 42CMOS VLSI Design
Interconnect Delay
21: Scaling and Economics Slide 43CMOS VLSI Design
Observations
 Capacitance per micron is remaining constant
– About 0.2 fF/µm
– Roughly 1/10 of gate capacitance
 Local wires are getting faster
– Not quite tracking transistor improvement
– But not a major problem
 Global wires are getting slower
– No longer possible to cross chip in one cycle
21: Scaling and Economics Slide 44CMOS VLSI Design
ITRS
 Semiconductor Industry Association forecast
– Intl. Technology Roadmap for Semiconductors
21: Scaling and Economics Slide 45CMOS VLSI Design
Scaling Implications
 Improved Performance
 Improved Cost
 Interconnect Woes
 Power Woes
 Productivity Challenges
 Physical Limits
21: Scaling and Economics Slide 46CMOS VLSI Design
Cost Improvement
 In 2003, $0.01 bought you 100,000 transistors
– Moore’s Law is still going strong
[Moore03]
21: Scaling and Economics Slide 47CMOS VLSI Design
Interconnect Woes
 SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm,
then get worse because of wires
 But…
[SIA97]
21: Scaling and Economics Slide 48CMOS VLSI Design
Interconnect Woes
 SIA made a gloomy forecast in 1997
– Delay would reach minimum at 250 – 180 nm,
then get worse because of wires
 But…
– Misleading scale
– Global wires
 100 kgate blocks ok
21: Scaling and Economics Slide 49CMOS VLSI Design
Reachable Radius
 We can’t send a signal across a large fast chip in
one cycle anymore
 But the microarchitect can plan around this
– Just as off-chip memory latencies were tolerated
Chip size
Scaling of
reachable radius
21: Scaling and Economics Slide 50CMOS VLSI Design
Dynamic Power
 Intel VP Patrick Gelsinger (ISSCC 2001)
– If scaling continues at present pace, by 2005,
high speed processors would have power density
of nuclear reactor, by 2010, a rocket nozzle, and
by 2015, surface of sun.
– “Business as usual will not work in the future.”
 Intel stock dropped 8%
on the next day
 But attention to power is
increasing
[Moore03]
21: Scaling and Economics Slide 51CMOS VLSI Design
Static Power
 VDD decreases
– Save dynamic power
– Protect thin gate oxides and short channels
– No point in high value because of velocity sat.
 Vt must decrease to
maintain device performance
 But this causes exponential
increase in OFF leakage
 Major future challenge
Static
Dynamic
[Moore03]
21: Scaling and Economics Slide 52CMOS VLSI Design
Productivity
 Transistor count is increasing faster than designer
productivity (gates / week)
– Bigger design teams
• Up to 500 for a high-end microprocessor
– More expensive design cost
– Pressure to raise productivity
• Rely on synthesis, IP blocks
– Need for good engineering managers
21: Scaling and Economics Slide 53CMOS VLSI Design
Physical Limits
 Will Moore’s Law run out of steam?
– Can’t build transistors smaller than an atom…
 Many reasons have been predicted for end of scaling
– Dynamic power
– Subthreshold leakage, tunneling
– Short channel effects
– Fabrication costs
– Electromigration
– Interconnect delay
 Rumors of demise have been exaggerated
21: Scaling and Economics Slide 54CMOS VLSI Design
VLSI Economics
 Selling price Stotal
– Stotal = Ctotal / (1-m)
 m = profit margin
 Ctotal = total cost
– Nonrecurring engineering cost (NRE)
– Recurring cost
– Fixed cost
21: Scaling and Economics Slide 55CMOS VLSI Design
NRE
 Engineering cost
– Depends on size of design team
– Include benefits, training, computers
– CAD tools:
• Digital front end: $10K
• Analog front end: $100K
• Digital back end: $1M
 Prototype manufacturing
– Mask costs: $500k – 1M in 130 nm process
– Test fixture and package tooling
21: Scaling and Economics Slide 56CMOS VLSI Design
Recurring Costs
 Fabrication
– Wafer cost / (Dice per wafer * Yield)
– Wafer cost: $500 - $3000
– Dice per wafer:
– Yield: Y = e-AD
• For small A, Y ≈ 1, cost proportional to area
• For large A, Y → 0, cost increases exponentially
 Packaging
 Test
2
2
2
r r
N
A A
π
 
= − 
 
21: Scaling and Economics Slide 57CMOS VLSI Design
Fixed Costs
 Data sheets and application notes
 Marketing and advertising
 Yield analysis
21: Scaling and Economics Slide 58CMOS VLSI Design
Example
 You want to start a company to build a wireless
communications chip. How much venture capital
must you raise?
 Because you are smarter than everyone else, you
can get away with a small team in just two years:
– Seven digital designers
– Three analog designers
– Five support personnel
21: Scaling and Economics Slide 59CMOS VLSI Design
Solution
 Digital designers:
– salary
– overhead
– computer
– CAD tools
– Total:
 Analog designers
– salary
– overhead
– computer
– CAD tools
– Total:
 Support staff
– salary
– overhead
– computer
– Total:
 Fabrication
– Back-end tools:
– Masks:
– Total:
 Summary
21: Scaling and Economics Slide 60CMOS VLSI Design
Solution
 Digital designers:
– $70k salary
– $30k overhead
– $10k computer
– $10k CAD tools
– Total: $120k * 7 = $840k
 Analog designers
– $100k salary
– $30k overhead
– $10k computer
– $100k CAD tools
– Total: $240k * 3 = $720k
 Support staff
– $45k salary
– $20k overhead
– $5k computer
– Total: $70k * 5 = $350k
 Fabrication
– Back-end tools: $1M
– Masks: $1M
– Total: $2M / year
 Summary
– 2 years @ $3.91M / year
– $8M design & prototype
21: Scaling and Economics Slide 61CMOS VLSI Design
Cost Breakdown
 New chip design is fairly capital-intensive
 Maybe you can do it for less?
salary
overhead
computer
entrytools
backendtools
fab
25%
25%
26%
9%
4%
11%

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Lect21

  • 1. Introduction to CMOS VLSI Design Lecture 21: Scaling and Economics David Harris Harvey Mudd College Spring 2004
  • 2. 21: Scaling and Economics Slide 2CMOS VLSI Design Outline  Scaling – Transistors – Interconnect – Future Challenges  VLSI Economics
  • 3. 21: Scaling and Economics Slide 3CMOS VLSI Design Moore’s Law  In 1965, Gordon Moore predicted the exponential growth of the number of transistors on an IC  Transistor count doubled every year since invention  Predicted > 65,000 transistors by 1975!  Growth limited by power [Moore65]
  • 4. 21: Scaling and Economics Slide 4CMOS VLSI Design More Moore  Transistor counts have doubled every 26 months for the past three decades. Year Transistors 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro Pentium II Pentium III Pentium 4 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 1970 1975 1980 1985 1990 1995 2000
  • 5. 21: Scaling and Economics Slide 5CMOS VLSI Design Speed Improvement  Clock frequencies have also increased exponentially – A corollary of Moore’s Law Year 1 10 100 1,000 10,000 1970 1975 1980 1985 1990 1995 2000 2005 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 ClockSpeed(MHz)
  • 6. 21: Scaling and Economics Slide 6CMOS VLSI Design Why?  Why more transistors per IC?  Why faster computers?
  • 7. 21: Scaling and Economics Slide 7CMOS VLSI Design Why?  Why more transistors per IC? – Smaller transistors – Larger dice  Why faster computers?
  • 8. 21: Scaling and Economics Slide 8CMOS VLSI Design Why?  Why more transistors per IC? – Smaller transistors – Larger dice  Why faster computers? – Smaller, faster transistors – Better microarchitecture (more IPC) – Fewer gate delays per cycle
  • 9. 21: Scaling and Economics Slide 9CMOS VLSI Design Scaling  The only constant in VLSI is constant change  Feature size shrinks by 30% every 2-3 years – Transistors become cheaper – Transistors become faster – Wires do not improve (and may get worse)  Scale factor S – Typically – Technology nodes Year 0.1 1 10 1965 1970 1975 1980 1985 1990 1995 2000 2005 FeatureSize(µm) 10 6 3 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 0.09 2S =
  • 10. 21: Scaling and Economics Slide 10CMOS VLSI Design Scaling Assumptions  What changes between technology nodes?  Constant Field Scaling – All dimensions (x, y, z => W, L, tox) – Voltage (VDD) – Doping levels  Lateral Scaling – Only gate length L – Often done as a quick gate shrink (S = 1.05)
  • 11. 21: Scaling and Economics Slide 11CMOS VLSI Design Device Scaling
  • 12. 21: Scaling and Economics Slide 12CMOS VLSI Design Device Scaling
  • 13. 21: Scaling and Economics Slide 13CMOS VLSI Design Device Scaling
  • 14. 21: Scaling and Economics Slide 14CMOS VLSI Design Device Scaling
  • 15. 21: Scaling and Economics Slide 15CMOS VLSI Design Device Scaling
  • 16. 21: Scaling and Economics Slide 16CMOS VLSI Design Device Scaling
  • 17. 21: Scaling and Economics Slide 17CMOS VLSI Design Device Scaling
  • 18. 21: Scaling and Economics Slide 18CMOS VLSI Design Device Scaling
  • 19. 21: Scaling and Economics Slide 19CMOS VLSI Design Device Scaling
  • 20. 21: Scaling and Economics Slide 20CMOS VLSI Design Device Scaling
  • 21. 21: Scaling and Economics Slide 21CMOS VLSI Design Device Scaling
  • 22. 21: Scaling and Economics Slide 22CMOS VLSI Design Device Scaling
  • 23. 21: Scaling and Economics Slide 23CMOS VLSI Design Observations  Gate capacitance per micron is nearly independent of process  But ON resistance * micron improves with process  Gates get faster with scaling (good)  Dynamic power goes down with scaling (good)  Current density goes up with scaling (bad)  Velocity saturation makes lateral scaling unsustainable
  • 24. 21: Scaling and Economics Slide 24CMOS VLSI Design Example  Gate capacitance is typically about 2 fF/µm  The FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5f ps  Estimate the ON resistance of a unit (4/2 λ) transistor.
  • 25. 21: Scaling and Economics Slide 25CMOS VLSI Design Solution  Gate capacitance is typically about 2 fF/µm  The FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5f ps  Estimate the ON resistance of a unit (4/2 λ) transistor.  FO4 = 5 τ = 15 RC  RC = (0.5f) / 15 = (f/30) ps/nm  If W = 2f, R = 8.33 kΩ – Unit resistance is roughly independent of f
  • 26. 21: Scaling and Economics Slide 26CMOS VLSI Design Scaling Assumptions  Wire thickness – Hold constant vs. reduce in thickness  Wire length – Local / scaled interconnect – Global interconnect • Die size scaled by Dc ≈ 1.1
  • 27. 21: Scaling and Economics Slide 27CMOS VLSI Design Interconnect Scaling
  • 28. 21: Scaling and Economics Slide 28CMOS VLSI Design Interconnect Scaling
  • 29. 21: Scaling and Economics Slide 29CMOS VLSI Design Interconnect Scaling
  • 30. 21: Scaling and Economics Slide 30CMOS VLSI Design Interconnect Scaling
  • 31. 21: Scaling and Economics Slide 31CMOS VLSI Design Interconnect Scaling
  • 32. 21: Scaling and Economics Slide 32CMOS VLSI Design Interconnect Scaling
  • 33. 21: Scaling and Economics Slide 33CMOS VLSI Design Interconnect Scaling
  • 34. 21: Scaling and Economics Slide 34CMOS VLSI Design Interconnect Scaling
  • 35. 21: Scaling and Economics Slide 35CMOS VLSI Design Interconnect Scaling
  • 36. 21: Scaling and Economics Slide 36CMOS VLSI Design Interconnect Delay
  • 37. 21: Scaling and Economics Slide 37CMOS VLSI Design Interconnect Delay
  • 38. 21: Scaling and Economics Slide 38CMOS VLSI Design Interconnect Delay
  • 39. 21: Scaling and Economics Slide 39CMOS VLSI Design Interconnect Delay
  • 40. 21: Scaling and Economics Slide 40CMOS VLSI Design Interconnect Delay
  • 41. 21: Scaling and Economics Slide 41CMOS VLSI Design Interconnect Delay
  • 42. 21: Scaling and Economics Slide 42CMOS VLSI Design Interconnect Delay
  • 43. 21: Scaling and Economics Slide 43CMOS VLSI Design Observations  Capacitance per micron is remaining constant – About 0.2 fF/µm – Roughly 1/10 of gate capacitance  Local wires are getting faster – Not quite tracking transistor improvement – But not a major problem  Global wires are getting slower – No longer possible to cross chip in one cycle
  • 44. 21: Scaling and Economics Slide 44CMOS VLSI Design ITRS  Semiconductor Industry Association forecast – Intl. Technology Roadmap for Semiconductors
  • 45. 21: Scaling and Economics Slide 45CMOS VLSI Design Scaling Implications  Improved Performance  Improved Cost  Interconnect Woes  Power Woes  Productivity Challenges  Physical Limits
  • 46. 21: Scaling and Economics Slide 46CMOS VLSI Design Cost Improvement  In 2003, $0.01 bought you 100,000 transistors – Moore’s Law is still going strong [Moore03]
  • 47. 21: Scaling and Economics Slide 47CMOS VLSI Design Interconnect Woes  SIA made a gloomy forecast in 1997 – Delay would reach minimum at 250 – 180 nm, then get worse because of wires  But… [SIA97]
  • 48. 21: Scaling and Economics Slide 48CMOS VLSI Design Interconnect Woes  SIA made a gloomy forecast in 1997 – Delay would reach minimum at 250 – 180 nm, then get worse because of wires  But… – Misleading scale – Global wires  100 kgate blocks ok
  • 49. 21: Scaling and Economics Slide 49CMOS VLSI Design Reachable Radius  We can’t send a signal across a large fast chip in one cycle anymore  But the microarchitect can plan around this – Just as off-chip memory latencies were tolerated Chip size Scaling of reachable radius
  • 50. 21: Scaling and Economics Slide 50CMOS VLSI Design Dynamic Power  Intel VP Patrick Gelsinger (ISSCC 2001) – If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun. – “Business as usual will not work in the future.”  Intel stock dropped 8% on the next day  But attention to power is increasing [Moore03]
  • 51. 21: Scaling and Economics Slide 51CMOS VLSI Design Static Power  VDD decreases – Save dynamic power – Protect thin gate oxides and short channels – No point in high value because of velocity sat.  Vt must decrease to maintain device performance  But this causes exponential increase in OFF leakage  Major future challenge Static Dynamic [Moore03]
  • 52. 21: Scaling and Economics Slide 52CMOS VLSI Design Productivity  Transistor count is increasing faster than designer productivity (gates / week) – Bigger design teams • Up to 500 for a high-end microprocessor – More expensive design cost – Pressure to raise productivity • Rely on synthesis, IP blocks – Need for good engineering managers
  • 53. 21: Scaling and Economics Slide 53CMOS VLSI Design Physical Limits  Will Moore’s Law run out of steam? – Can’t build transistors smaller than an atom…  Many reasons have been predicted for end of scaling – Dynamic power – Subthreshold leakage, tunneling – Short channel effects – Fabrication costs – Electromigration – Interconnect delay  Rumors of demise have been exaggerated
  • 54. 21: Scaling and Economics Slide 54CMOS VLSI Design VLSI Economics  Selling price Stotal – Stotal = Ctotal / (1-m)  m = profit margin  Ctotal = total cost – Nonrecurring engineering cost (NRE) – Recurring cost – Fixed cost
  • 55. 21: Scaling and Economics Slide 55CMOS VLSI Design NRE  Engineering cost – Depends on size of design team – Include benefits, training, computers – CAD tools: • Digital front end: $10K • Analog front end: $100K • Digital back end: $1M  Prototype manufacturing – Mask costs: $500k – 1M in 130 nm process – Test fixture and package tooling
  • 56. 21: Scaling and Economics Slide 56CMOS VLSI Design Recurring Costs  Fabrication – Wafer cost / (Dice per wafer * Yield) – Wafer cost: $500 - $3000 – Dice per wafer: – Yield: Y = e-AD • For small A, Y ≈ 1, cost proportional to area • For large A, Y → 0, cost increases exponentially  Packaging  Test 2 2 2 r r N A A π   = −   
  • 57. 21: Scaling and Economics Slide 57CMOS VLSI Design Fixed Costs  Data sheets and application notes  Marketing and advertising  Yield analysis
  • 58. 21: Scaling and Economics Slide 58CMOS VLSI Design Example  You want to start a company to build a wireless communications chip. How much venture capital must you raise?  Because you are smarter than everyone else, you can get away with a small team in just two years: – Seven digital designers – Three analog designers – Five support personnel
  • 59. 21: Scaling and Economics Slide 59CMOS VLSI Design Solution  Digital designers: – salary – overhead – computer – CAD tools – Total:  Analog designers – salary – overhead – computer – CAD tools – Total:  Support staff – salary – overhead – computer – Total:  Fabrication – Back-end tools: – Masks: – Total:  Summary
  • 60. 21: Scaling and Economics Slide 60CMOS VLSI Design Solution  Digital designers: – $70k salary – $30k overhead – $10k computer – $10k CAD tools – Total: $120k * 7 = $840k  Analog designers – $100k salary – $30k overhead – $10k computer – $100k CAD tools – Total: $240k * 3 = $720k  Support staff – $45k salary – $20k overhead – $5k computer – Total: $70k * 5 = $350k  Fabrication – Back-end tools: $1M – Masks: $1M – Total: $2M / year  Summary – 2 years @ $3.91M / year – $8M design & prototype
  • 61. 21: Scaling and Economics Slide 61CMOS VLSI Design Cost Breakdown  New chip design is fairly capital-intensive  Maybe you can do it for less? salary overhead computer entrytools backendtools fab 25% 25% 26% 9% 4% 11%