This document summarizes code for a lab experiment on a Tiva C Series microcontroller. It includes header files for variable definitions, Boolean logic, the microcontroller hardware, memory mapping, common types and macros, GPIO, timer, UART, and pin mapping functionality. It declares functions for initializing LEDs, buttons, timers, and UART. It sets constants for LED pins, button pins, debounce checks, timer frequencies, and UART baud rate. The main function initializes clocks, LEDs, buttons, UART, and timers. It enables interrupts and timers, and uses a for loop to display text on the UART console.
This document describes Lab 3 of an embedded systems course. It introduces header files, constants, variables and functions used to initialize and control an MCU's peripherals like LEDs, timers, UART, and ADC. The code configures the MCU's clock, enables interrupts, and implements a state machine to control the LEDs and read the ADC based on UART input from a user. Functions are defined to initialize each peripheral and an ISR handles timer interrupts.
This document summarizes code for a digital signal processing lab that uses a Tiva C Series microcontroller. The code includes header files for variable definitions, Boolean definitions, and APIs for the microcontroller, memory map, common types, and peripherals like system control, GPIO, and timers. Functions are declared to initialize LEDs and a timer. The timer is configured to generate interrupts at different frequencies by changing the TIMER0_FREQ definition, and an interrupt service routine toggles the LEDs.
The document discusses signals and daemon processes in Unix system programming. It covers:
1) Signals are software interrupts that allow processes to handle asynchronous events. Processes can accept default signal actions, ignore signals, or catch signals using user-defined handlers.
2) Common signals include SIGINT, SIGTERM, SIGKILL. The signal() function allows processes to set handlers for signals.
3) Daemons are long-running background processes that handle system services. Daemons detach from the controlling terminal and session.
1) The document describes a system for monitoring and controlling a petrol pumping process using an FPGA platform. Smart sensors are installed on the pumping pipes to monitor temperature, pressure, and flow rate.
2) The FPGA receives data from the sensors through a data acquisition interface. It analyzes the data and controls the pumping machine speed accordingly. If sensor values are normal, it runs a standard pumping subroutine. If values are abnormal, it runs emergency subroutines to slow or shut down the pump.
3) The system was tested under different conditions and responded appropriately based on sensor data, demonstrating it can provide real-time monitoring and control for safe petrol pumping. The FPGA was determined to be a suitable
TAE Technologies is working to develop commercial, cutting-
edge nuclear fusion power. This research depends on a network
of equipment to create an ultra-high vacuum within their plasma
generator. A single day of downtime costs up to $150,000, so they
require a control system that is reliable and flexible enough to
simplify the addition of new equipment. Using ControlLogix®,
Studio 5000® programming environment and FactoryTalk®
View SE, TAE has developed a distributed and structured control
system and has not experienced a day of downtime for the past
eight years
Implementation of the ZigBee ZCL Reporting Configuration FeaturesSimen Li
This slide presents the implementation of the ZigBee ZCL Reporting Configuration features by taking TI Z-Stack Home 1.2.1 SampleLight project as an example.
The Rockwell Automation® Library of Process Objects helps
you quickly develop process solutions with rich functionality
and known performance. In this session, how to build a control
strategy using Library objects will be demonstrated. The Library
objects and their functions within a typical control system will
be presented, highlighting features for operators, maintainers
and engineers. Walk away understanding the value of using the
Library to develop process solutions.
This document describes Lab 3 of an embedded systems course. It introduces header files, constants, variables and functions used to initialize and control an MCU's peripherals like LEDs, timers, UART, and ADC. The code configures the MCU's clock, enables interrupts, and implements a state machine to control the LEDs and read the ADC based on UART input from a user. Functions are defined to initialize each peripheral and an ISR handles timer interrupts.
This document summarizes code for a digital signal processing lab that uses a Tiva C Series microcontroller. The code includes header files for variable definitions, Boolean definitions, and APIs for the microcontroller, memory map, common types, and peripherals like system control, GPIO, and timers. Functions are declared to initialize LEDs and a timer. The timer is configured to generate interrupts at different frequencies by changing the TIMER0_FREQ definition, and an interrupt service routine toggles the LEDs.
The document discusses signals and daemon processes in Unix system programming. It covers:
1) Signals are software interrupts that allow processes to handle asynchronous events. Processes can accept default signal actions, ignore signals, or catch signals using user-defined handlers.
2) Common signals include SIGINT, SIGTERM, SIGKILL. The signal() function allows processes to set handlers for signals.
3) Daemons are long-running background processes that handle system services. Daemons detach from the controlling terminal and session.
1) The document describes a system for monitoring and controlling a petrol pumping process using an FPGA platform. Smart sensors are installed on the pumping pipes to monitor temperature, pressure, and flow rate.
2) The FPGA receives data from the sensors through a data acquisition interface. It analyzes the data and controls the pumping machine speed accordingly. If sensor values are normal, it runs a standard pumping subroutine. If values are abnormal, it runs emergency subroutines to slow or shut down the pump.
3) The system was tested under different conditions and responded appropriately based on sensor data, demonstrating it can provide real-time monitoring and control for safe petrol pumping. The FPGA was determined to be a suitable
TAE Technologies is working to develop commercial, cutting-
edge nuclear fusion power. This research depends on a network
of equipment to create an ultra-high vacuum within their plasma
generator. A single day of downtime costs up to $150,000, so they
require a control system that is reliable and flexible enough to
simplify the addition of new equipment. Using ControlLogix®,
Studio 5000® programming environment and FactoryTalk®
View SE, TAE has developed a distributed and structured control
system and has not experienced a day of downtime for the past
eight years
Implementation of the ZigBee ZCL Reporting Configuration FeaturesSimen Li
This slide presents the implementation of the ZigBee ZCL Reporting Configuration features by taking TI Z-Stack Home 1.2.1 SampleLight project as an example.
The Rockwell Automation® Library of Process Objects helps
you quickly develop process solutions with rich functionality
and known performance. In this session, how to build a control
strategy using Library objects will be demonstrated. The Library
objects and their functions within a typical control system will
be presented, highlighting features for operators, maintainers
and engineers. Walk away understanding the value of using the
Library to develop process solutions.
The document summarizes key concepts about processes from an operating systems textbook. It discusses process concepts like process state, process control blocks (PCB), and process scheduling queues. It also covers process creation, termination, and cooperation between processes. Interprocess communication methods like message passing and synchronization are presented. The document concludes with an overview of client-server communication techniques using sockets, remote procedure calls, and remote method invocation.
AirSensEUR: AirQuality monitoring open framework technical presentationMarco Signorini
AirSensEUR is an open framework focused on air quality monitoring using low cost sensors. The project started on 2014 from a group of passionate researchers and engineers. The framework is composed by a set of electronic boards, firmware, and several software applications. The slides present the technical solutions adopted in the framework by entering on hardware and software related details. For more info, look at the project website www.airsenseur.org
Klessydra t - designing vector coprocessors for multi-threaded edge-computing...RISC-V International
The document describes a proposed Klessydra-T1 vector coprocessor architecture designed for multi-threaded edge computing cores. It achieves a 3x speedup over a baseline core through configurable SIMD and MIMD vector acceleration schemes. Benchmark results show cycle count reductions for workloads like convolution and matrix multiplication when using the coprocessor in various SISD, SIMD, and MIMD configurations. Resource utilization and maximum frequency are also analyzed.
This document discusses the challenges of building and optimizing open RAN systems for 5G networks. It describes Picocom's 5G baseband system-on-chip architecture using multiple RISC-V clusters and hardware accelerators. Maintaining performance and detecting problems is difficult due to the complex timing requirements across hundreds of users. Mentor's embedded analytics solution monitors the system non-intrusively using on-chip sensors to detect issues like timing overruns and help optimize performance both during development and over the lifetime of deployments.
The document summarizes an online test program generator for RISC-V microprocessors called MicroTESK. It describes how the generator works offline by translating specifications into test programs, and online by executing directly on the device under test to generate and run tests. The generator uses techniques like combinatorial brute-force and randomization to generate diverse test cases and checks results with signatures and transformations to detect errors. Future work areas include supporting more RISC-V instruction subsets and advanced techniques like model-based generation, mutations, and equivalence checking.
[ZigBee 嵌入式系統] ZigBee 應用實作 - 使用 TI Z-Stack FirmwareSimen Li
The document outlines an application called BasicApp that is used to understand the basic operations of the OSAL (Operating System Abstraction Layer) embedded in the ZigBee firmware. It describes initializing tasks using OSAL, processing events, and handling key presses to control an LED using the HAL (Hardware Abstraction Layer) APIs. The code files for the BasicApp include OSAL_BasicApp.c for task initialization, BasicApp.h for constants and function declarations, and BasicApp.c which implements the task event processing and key handling functions.
The document contains information about various digital circuits that can be used for a VHDL practical exam, including code and simulations for:
1. A 4-bit by 4-bit multiplier circuit with VHDL code and a simulation forcing inputs and displaying outputs.
2. An 8-bit by 8-bit multiplier circuit with similar VHDL code and simulation.
3. A 128-bit by 8-bit RAM circuit with 1024 bits of memory, VHDL code, and a simulation storing values and reading them back out.
A high level look at how to convert a cheap Chinese laser cutter to LinuxCNC.
The accompanying demo video can be found at: https://youtu.be/U3kADpXyDE8
The document discusses modules and ports in Verilog. It describes that a module defines distinct parts including module name, port list, port declarations, and optional parameters. Ports provide the interface for a module to communicate with its environment. There are two methods for connecting ports to external signals - by ordered list where signals must appear in the same order as ports, and by name where the order does not matter as long as port names match. Hierarchical names provide unique names for every identifier by denoting the design hierarchy with identifiers separated by periods.
This document provides an introduction to Verilog HDL including:
- An overview of Verilog keywords, data types, abstraction levels, and design methodology.
- Details on the history of Verilog including its development over time and transitions to newer standards.
- Explanations of key Verilog concepts like modules, ports, instantiation, stimuli, and lexical conventions.
Modules are the basic building blocks, ports define module interfaces, and instantiation replicates modules. Stimuli provide test inputs and lexical conventions cover syntax rules.
Design and Implementation of 64 Bit RISC Processor Using System.pdfChowdappaKv1
The document describes the design and implementation of a 64-bit RISC processor using a system on chip. It includes a built-in self-test feature. The processor was designed for applications requiring automation and control, such as in bottling plants. The design includes a 64-bit architecture and instruction set. It was implemented in Verilog and tested in a Cadence simulator. Simulation results and analysis of area, power usage, and timing are presented.
This document describes a chemical extraction system controlled by an FPGA programmed using VHDL. The system extracts acetone from a water/acetone solution based on the different boiling points. The FPGA controls valves and monitors temperature and concentration sensors. A VHDL program was developed and divided into four parts to control the system. The program was synthesized and downloaded to the FPGA. The system successfully extracted 99% pure acetone by opening and closing valves based on sensor readings. FPGAs provide facilities to control systems in parallel, allowing control of many elements with minimal delay.
32 bit ALU Chip Design using IBM 130nm process technologyBharat Biyani
- Implemented a 32 bit Arithmetic/Logic unit in VHDL using behavioral Modeling which involves all basic ALU operations including special functionality like binary-to-grey code conversion, parity check, sum of first N numbers. Simulation is performed in ModelSim IDE.
- Involved design using Cadence (Virtuoso Layout/Schematic) and Hspice simulation of standard library cell.
- Involved library characterization using NCX, RTL synthesis of VHDL code using Synopsys Design Vision, auto placement & routing using Encounter, static timing analysis using Synopsys Primetime.
This document describes the design and characterization of a D flip-flop cell. It includes the layout, schematic, simulation waveforms, and timing analysis of the D flip-flop. The layout uses two metal layers and occupies an area of 76.8 μm2. Timing parameters such as setup time, clock-to-output time, and delay are calculated through HSPICE simulation and optimization curves.
The document describes designing all basic logic gates including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It provides the circuit symbol, logic table, and function of each gate. The aim is to design the basic logic gates using Verilog code, synthesize them using the Xilinx ISE simulator, and verify the outputs through simulation test benches. The document includes the Verilog code, RTL schematic, technology schematic, and simulations of the basic logic gates.
The document discusses the 8051 microcontroller. It describes the basic components of the 8051 including 4K bytes of internal ROM, 128 bytes of internal RAM, four 8-bit I/O ports, two 16-bit timers/counters, and one serial interface. It also provides details on the block diagram, important pins like ports and serial interface pins, and how to connect an external clock source to the 8051.
The document discusses the 8051 microcontroller. It describes the basic components of the 8051 including 4K bytes of internal ROM, 128 bytes of internal RAM, four 8-bit I/O ports, two 16-bit timers/counters, and one serial interface. It also provides details on the block diagram, important pins like ports and serial interface pins, and how to connect an external clock source to the 8051.
This paper presents interfaces required in wireless sensor node (WSN) implementation. Here keyboard,
LCD, ADC and Wi-Fi module interfaces are presented. These interfaces are developed as hardware prototypes in
the application of wireless sensor node as a single chip solution. Protocols of these interfaces have been described
with the help of their hardware simulations and synthesis reports.
The end application is proposed to monitor physical parameters remotely using wireless protocol. The sensor node
has to be implemented on Field Programmable Gate Array (FPGA). The proposed node design is reconfigurable,
and hence flexible in context of future modification. Xilinx platform is proposed for synthesis, simulation and
implementation.
Keywords — FPGA, wireless sensor node.
The document discusses several POSIX feature test macros like _POSIX_JOB_CONTROL and _POSIX_SAVED_IDS. It explains that these macros define whether a system supports features like job control and each process saving UID and GID. It also discusses using sysconf(), pathconf() and fpathconf() to check runtime limits and configuration values set by these macros.
This is a presentation that identifies the various components of the 11i technology stack and how to generate log files for them for troubleshooting and debugging.
The document summarizes key concepts about processes from an operating systems textbook. It discusses process concepts like process state, process control blocks (PCB), and process scheduling queues. It also covers process creation, termination, and cooperation between processes. Interprocess communication methods like message passing and synchronization are presented. The document concludes with an overview of client-server communication techniques using sockets, remote procedure calls, and remote method invocation.
AirSensEUR: AirQuality monitoring open framework technical presentationMarco Signorini
AirSensEUR is an open framework focused on air quality monitoring using low cost sensors. The project started on 2014 from a group of passionate researchers and engineers. The framework is composed by a set of electronic boards, firmware, and several software applications. The slides present the technical solutions adopted in the framework by entering on hardware and software related details. For more info, look at the project website www.airsenseur.org
Klessydra t - designing vector coprocessors for multi-threaded edge-computing...RISC-V International
The document describes a proposed Klessydra-T1 vector coprocessor architecture designed for multi-threaded edge computing cores. It achieves a 3x speedup over a baseline core through configurable SIMD and MIMD vector acceleration schemes. Benchmark results show cycle count reductions for workloads like convolution and matrix multiplication when using the coprocessor in various SISD, SIMD, and MIMD configurations. Resource utilization and maximum frequency are also analyzed.
This document discusses the challenges of building and optimizing open RAN systems for 5G networks. It describes Picocom's 5G baseband system-on-chip architecture using multiple RISC-V clusters and hardware accelerators. Maintaining performance and detecting problems is difficult due to the complex timing requirements across hundreds of users. Mentor's embedded analytics solution monitors the system non-intrusively using on-chip sensors to detect issues like timing overruns and help optimize performance both during development and over the lifetime of deployments.
The document summarizes an online test program generator for RISC-V microprocessors called MicroTESK. It describes how the generator works offline by translating specifications into test programs, and online by executing directly on the device under test to generate and run tests. The generator uses techniques like combinatorial brute-force and randomization to generate diverse test cases and checks results with signatures and transformations to detect errors. Future work areas include supporting more RISC-V instruction subsets and advanced techniques like model-based generation, mutations, and equivalence checking.
[ZigBee 嵌入式系統] ZigBee 應用實作 - 使用 TI Z-Stack FirmwareSimen Li
The document outlines an application called BasicApp that is used to understand the basic operations of the OSAL (Operating System Abstraction Layer) embedded in the ZigBee firmware. It describes initializing tasks using OSAL, processing events, and handling key presses to control an LED using the HAL (Hardware Abstraction Layer) APIs. The code files for the BasicApp include OSAL_BasicApp.c for task initialization, BasicApp.h for constants and function declarations, and BasicApp.c which implements the task event processing and key handling functions.
The document contains information about various digital circuits that can be used for a VHDL practical exam, including code and simulations for:
1. A 4-bit by 4-bit multiplier circuit with VHDL code and a simulation forcing inputs and displaying outputs.
2. An 8-bit by 8-bit multiplier circuit with similar VHDL code and simulation.
3. A 128-bit by 8-bit RAM circuit with 1024 bits of memory, VHDL code, and a simulation storing values and reading them back out.
A high level look at how to convert a cheap Chinese laser cutter to LinuxCNC.
The accompanying demo video can be found at: https://youtu.be/U3kADpXyDE8
The document discusses modules and ports in Verilog. It describes that a module defines distinct parts including module name, port list, port declarations, and optional parameters. Ports provide the interface for a module to communicate with its environment. There are two methods for connecting ports to external signals - by ordered list where signals must appear in the same order as ports, and by name where the order does not matter as long as port names match. Hierarchical names provide unique names for every identifier by denoting the design hierarchy with identifiers separated by periods.
This document provides an introduction to Verilog HDL including:
- An overview of Verilog keywords, data types, abstraction levels, and design methodology.
- Details on the history of Verilog including its development over time and transitions to newer standards.
- Explanations of key Verilog concepts like modules, ports, instantiation, stimuli, and lexical conventions.
Modules are the basic building blocks, ports define module interfaces, and instantiation replicates modules. Stimuli provide test inputs and lexical conventions cover syntax rules.
Design and Implementation of 64 Bit RISC Processor Using System.pdfChowdappaKv1
The document describes the design and implementation of a 64-bit RISC processor using a system on chip. It includes a built-in self-test feature. The processor was designed for applications requiring automation and control, such as in bottling plants. The design includes a 64-bit architecture and instruction set. It was implemented in Verilog and tested in a Cadence simulator. Simulation results and analysis of area, power usage, and timing are presented.
This document describes a chemical extraction system controlled by an FPGA programmed using VHDL. The system extracts acetone from a water/acetone solution based on the different boiling points. The FPGA controls valves and monitors temperature and concentration sensors. A VHDL program was developed and divided into four parts to control the system. The program was synthesized and downloaded to the FPGA. The system successfully extracted 99% pure acetone by opening and closing valves based on sensor readings. FPGAs provide facilities to control systems in parallel, allowing control of many elements with minimal delay.
32 bit ALU Chip Design using IBM 130nm process technologyBharat Biyani
- Implemented a 32 bit Arithmetic/Logic unit in VHDL using behavioral Modeling which involves all basic ALU operations including special functionality like binary-to-grey code conversion, parity check, sum of first N numbers. Simulation is performed in ModelSim IDE.
- Involved design using Cadence (Virtuoso Layout/Schematic) and Hspice simulation of standard library cell.
- Involved library characterization using NCX, RTL synthesis of VHDL code using Synopsys Design Vision, auto placement & routing using Encounter, static timing analysis using Synopsys Primetime.
This document describes the design and characterization of a D flip-flop cell. It includes the layout, schematic, simulation waveforms, and timing analysis of the D flip-flop. The layout uses two metal layers and occupies an area of 76.8 μm2. Timing parameters such as setup time, clock-to-output time, and delay are calculated through HSPICE simulation and optimization curves.
The document describes designing all basic logic gates including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It provides the circuit symbol, logic table, and function of each gate. The aim is to design the basic logic gates using Verilog code, synthesize them using the Xilinx ISE simulator, and verify the outputs through simulation test benches. The document includes the Verilog code, RTL schematic, technology schematic, and simulations of the basic logic gates.
The document discusses the 8051 microcontroller. It describes the basic components of the 8051 including 4K bytes of internal ROM, 128 bytes of internal RAM, four 8-bit I/O ports, two 16-bit timers/counters, and one serial interface. It also provides details on the block diagram, important pins like ports and serial interface pins, and how to connect an external clock source to the 8051.
The document discusses the 8051 microcontroller. It describes the basic components of the 8051 including 4K bytes of internal ROM, 128 bytes of internal RAM, four 8-bit I/O ports, two 16-bit timers/counters, and one serial interface. It also provides details on the block diagram, important pins like ports and serial interface pins, and how to connect an external clock source to the 8051.
This paper presents interfaces required in wireless sensor node (WSN) implementation. Here keyboard,
LCD, ADC and Wi-Fi module interfaces are presented. These interfaces are developed as hardware prototypes in
the application of wireless sensor node as a single chip solution. Protocols of these interfaces have been described
with the help of their hardware simulations and synthesis reports.
The end application is proposed to monitor physical parameters remotely using wireless protocol. The sensor node
has to be implemented on Field Programmable Gate Array (FPGA). The proposed node design is reconfigurable,
and hence flexible in context of future modification. Xilinx platform is proposed for synthesis, simulation and
implementation.
Keywords — FPGA, wireless sensor node.
The document discusses several POSIX feature test macros like _POSIX_JOB_CONTROL and _POSIX_SAVED_IDS. It explains that these macros define whether a system supports features like job control and each process saving UID and GID. It also discusses using sysconf(), pathconf() and fpathconf() to check runtime limits and configuration values set by these macros.
This is a presentation that identifies the various components of the 11i technology stack and how to generate log files for them for troubleshooting and debugging.
This document provides a consolidated list of kernel parameters organized alphabetically with descriptions of what they control. It notes that some parameters only apply if certain kernel configurations or hardware is enabled. Parameters can control modules, device drivers, architectures, and other kernel features. The document also distinguishes between parameters interpreted by the kernel versus the boot loader.
The document discusses functions in C programming. It focuses on when to declare functions, how to declare them, and different techniques for using them efficiently. The key points are that functions are the building blocks of C, mastering functions is essential, and the chapter provides tips to write better functions and squeeze more efficiency out of existing functions.
This document provides release notes and supplementary information for Delphi 7. It notes that some components have been deprecated and recommends newer alternatives. It also describes changes made to string handling functions, warnings added by the compiler, and issues fixed in streaming of subcomponents. Finally, it provides notes on various other topics like Apache, UDDI, Windows XP input, and databases.
Introduction to freebsd_6_kernel_hackingSusant Sahani
This document provides an introduction to customizing the FreeBSD 6 kernel through kernel module programming. It discusses topics such as the anatomy of a kernel module, including the use of DECLARE_MODULE and Makefiles. It also covers exporting configuration parameters through sysctl variables, and installing packet filters (PFIL) hooks. The document is intended to act as a primer for those new to FreeBSD kernel programming.
Here is a recursive C function that solves the Tower of Hanoi problem:
#include <stdio.h>
void towerOfHanoi(int n, char from_rod, char to_rod, char aux_rod)
{
if (n == 0)
return;
towerOfHanoi(n-1, from_rod, aux_rod, to_rod);
printf("Move disk %d from rod %c to rod %c\n", n, from_rod, to_rod);
towerOfHanoi(n-1, aux_rod, to_rod, from_rod);
}
int main()
{
int
This document discusses various tools for programming in Linux, including:
1. The GNU C Compiler (gcc) which compiles C, C++, and Objective-C programs. It performs preprocessing, compilation, assembly, and linking.
2. Make and automake which simplify building projects with multiple source files by tracking dependencies and only rebuilding changed files. Makefiles define rules and variables to build targets.
3. Popular programming languages for Linux including Java, JavaScript, PHP, Python, and others.
4. Graphical development tools like IDEs, SDKs, and clients for developing KDE and GNOME applications. Eclipse, NetBeans, and Visual Studio Code are mentioned as IDE options.
This document discusses building a virtual platform for the OpenRISC architecture using SystemC and transaction-level modeling. It covers setting up the toolchain, writing test programs, and simulating the platform using event-driven or cycle-accurate simulation with Icarus Verilog or the Vorpsoc simulator. The virtual platform allows fast development and debugging of OpenRISC code without requiring physical hardware.
This document discusses the key differences between ANSI C and K&R C. It covers four main points: 1) Function prototyping in ANSI C allows compilers to check for invalid function calls, unlike in K&R C. 2) ANSI C supports the const and volatile qualifiers. 3) ANSI C supports internationalization with wide characters and setlocale. 4) ANSI C allows function pointers to be used without dereferencing. The document provides examples to illustrate each point.
The document discusses intermediate code generation in compilers. It describes various intermediate representations like syntax trees, DAGs, postfix notation, and 3-address code. Syntax trees represent the hierarchical structure of a program and are constructed using functions like mknode() and mkleaf(). DAGs provide a more compact representation by identifying common subexpressions. Postfix notation linearizes the syntax tree. The document also discusses run-time environments, storage allocation strategies like static, stack and heap allocation, and activation records.
The document provides an introduction to the C programming language, including its history and development, features, basic structure of a C program, input/output functions like printf() and scanf(), variables, data types, operators, control statements like if-else, and loops. It explains that C is a procedural, machine-independent language developed in the early 1970s to be used in UNIX operating systems and describes the basic "Hello World" program as an example.
The document contains questions and answers related to network programming and UNIX system concepts. Some key points covered include:
- File descriptors are integers used by the kernel to identify open files for a process. A program is executed as a process, which has a unique process ID.
- There are two types of CPU times in UNIX - user CPU time for user instructions, and system CPU time for when the kernel executes on behalf of the process.
- Common IPC methods in UNIX include pipes, message queues, semaphores and shared memory. Message queues store prioritized messages in a linked list.
The document discusses the POSIX standards for operating system interfaces and APIs. It covers the history and development of POSIX, differences between ANSI C and C++, POSIX standards like POSIX.1 for file manipulation, POSIX feature test macros, limits checking APIs, and common characteristics of UNIX and POSIX APIs.
The document discusses object oriented programming concepts. It describes key object oriented programming concepts like encapsulation, inheritance, polymorphism, and message passing. It also discusses benefits of object oriented programming like modularity, reusability and extensibility. Some disadvantages discussed are compiler overhead, runtime overhead and need for reorientation of developers to object oriented thinking. The document also covers C++ programming concepts like data types, control flow, functions, arrays, strings, pointers and storage classes.
VHDL is a hardware description language used to model digital systems. It allows modeling at different levels of abstraction like gate level, register transfer level, and behavioral level. In VHDL, an entity declares the interface of a design unit with ports, an architecture describes the internal functionality using different styles like dataflow, behavioral, structural. Components can be instantiated and interconnected in structural modeling. Testbenches are used to check designs by applying test inputs and observing outputs.
The document discusses the basic structure of C programs. It explains that a C program contains functions that are organized into different sections, including a documentation section, link section, definition section, main function section, and optional subprogram section. It provides details on what each section is used for and example code to demonstrate the main components of a C program, including functions, variables, data types, and memory organization.
The document discusses the basic structure of C programs. It explains that a C program contains functions that are organized into different sections, including a documentation section, link section, definition section, main function section, and optional subprogram section. It provides details on what each section is used for and example code to demonstrate the main components of a C program, including functions, variables, data types, and memory organization.
This document discusses embedded C programming. It defines embedded C and compares it to conventional C and assembly programming. Key differences between embedded C and other languages include embedded C being microcontroller dependent rather than processor dependent, more portable code, and easier readability. Embedded C allows direct hardware access and optimization for limited embedded systems. The document outlines rules for developing optimized embedded C programs, including scope of variable declarations, function parameters, and register usage. Cross-compilers are used to compile embedded C code into executable hex files for microcontrollers.
The document discusses various C preprocessor directives and storage classes in C.
1. It defines storage class specifier and mentions the different types of storage classes - auto, extern, static, and register. It distinguishes between auto and register storage classes.
2. It explains what extern storage class means and provides an example. It identifies the storage class of a variable defined within a code block.
3. It discusses various preprocessor directives like #define, #undef, #if, #else, #include and explains their usage with examples.
1. Lab 2_5
EENG 3910: Project V - Digital Signal
Processing System Design
9/21/2015
Joseph Chandler
University of North Texas
College of Engineering
Electrical Engineering
2. Introduction
Lab 2_5 continuesthe studyof the TivaTM
C SeriesEK-TM4C123GXL and CCS software.Lab2_5 's aspects
consistof systemcontrols,timing,uartanddifferentmodules.
Results and Discussions
Problem 5
#include <stdint.h>
Thisline containsthe headerfile forvariabledefinitions.The headerfile isalreadydefinedinthe CCS
software.Examplesof the valuesare bitsize,precision,andsignedorunsignedintegers.
#include <stdbool.h>
Thisline containsthe headerfile forBooleandefinitions.The headerfile isalreadydefinedinthe CCS
software.The file definitionsare usedforoperations,comparingvariables,andprogramcontrol flow.
#include "inc/tm4c123gh6pm.h"
Thisline containsthe headerfile forthe TM4C123GH6PM microcontroller.The headerfile ispart-
specificandcontainsmacrosand definitionstosimplifyprogrammingthe peripheral'sregistersand
interruptcontrol.Thisiscontainedinthe incdirectory. The .c file forthe TM4C123GH6PM
microcontrollerisincludedinthe projectfolderfordirectaccess.
#include "inc/hw_memmap.h"
Thisline containsthe headerfile forthe TivaCSeriesdevice memorymapdefinitions.The headerfile
containsmanyof the same definitionsusedfordirectregisteraccess.The headerfilecontainsmacros
and definitionstosimplifyprogrammingthe peripheral'sregistersandinterruptcontrol.Thisis
containedinthe incdirectory.The definitionsare usedbydriverlibraries andare hiddenfromthe
programmer.
#include "inc/hw_types.h"
Thisline containsthe headerfile forcommontypesandmacros.The headerfile containsmanyof the
same definitionsusedfordirectregisteraccess.Thisiscontainedinthe incdirectory.The definitionsare
usedbydriverlibrariesandare hiddenfromthe programmer.The valuesare a wide varietyof general
use for itemssuchas arithmetic,clocktiming,file recognition,anddevicerecognition.
#include "inc/hw_gpio.h"
Thisline contains the headerfile forcommontypesandmacros.The headerfile containsmanyof the
same definitionsusedfordirectregisteraccess.Thisiscontainedinthe incdirectory.The definitionsare
3. usedbydriverlibrariesandare hiddenfromthe programmer.The valuesare a wide varietyof general
use for itemssuchas arithmetic,clocktiming,file recognition,anddevicerecognition.
#include "driverlib/sysctl.h"
Thisline containsthe headerfile forthe SystemControl APIdefinitionsandmacros.The headerfile isin
the directory"driverlib"of the CCSsoftware.The driversprovideguidedcontrol of the peripheralsand
allowsforquickapplication.Enablingperipheralsisanexampleof thiscontrol.
#include "driverlib/interrupt.h"
Thisline containsthe headerfile forthe SystemControl APIdefinitionsandmacros.The headerfile isin
the directory"driverlib"of the CCSsoftware.The driversprovideguidedcontrol of the peripheralsand
allowsforquickapplication.Enablingperipheralsisanexampleof thiscontrol.
#include "driverlib/gpio.h"
Thisline containsthe headerfile forGPIOAPIdefinitionsandmacros.The headerfile isinthe directory
"driverlib"of the CCSsoftware.The driverprovidesasetof functionstocontrol the inputand output
module.
#include "driverlib/timer.h"
Thisline containsthe headerfile forTimerAPIdefinitionsandmacros.The headerfile isinthe directory
"driverlib"of the CCSsoftware.The driversprovide quickcontrol of the peripheralsandallowsforquick
application.The timerAPIprovidesasetof functionsforusingthe timermodule.
#include "driverlib/pin_map.h"
Thisline containsthe headerfile forpin_mapAPIdefinitionsandmacros.The headerfile isinthe
directory"driverlib"of the CCSsoftware.The driversprovidequickcontrol of the peripheralsandallows
for quickapplication.The pin_map APIprovidesamapof the peripheral topinconfiguration.
#include "driverlib/uart.h"
Thisline containsthe headerfile forUART(Universal AsynchronousReceiver/Transmitter) API
definitionsandmacros.The headerfile isinthe directory"driverlib"of the CCSsoftware.The drivers
provide quickcontrol of the peripheralsandallowsforquickapplication.The UARTAPIprovidesasetof
functionsforusingthe TIVA UART module.
#include "utils/uartstdio.h"
Thisline containsthe header file forUART.The header file isinthe directory"utils"of the CCS
software.The utilityprovidesquickcontrol of the peripheralsandallowsforquickapplication. The file
containsprototypesforthe UART console functions.Onbuildingthe project,the .cfile hadtobe added
manuallytolinkthe filestogether.
#define RED_LED GPIO_PIN_1
4. Createsa constantfor pin1 inthe GPIO APImodule thatdisplaysthe red LED.
#define BLUE_LED GPIO_PIN_2
Createsa constantfor pin2 inthe GPIO APImodule thatdisplaysthe blue LED.
#define GREEN_LED GPIO_PIN_3
Createsa constantfor pin3 inthe GPIO APImodule thatdisplaysthe greenLED.
#define NUM_BUTTONS 2
Createsa constantusedfor the twoswitchbuttons.
#define LEFT_BUTTON GPIO_PIN_4
Createsa constantfor pin4 inthe GPIO APImodule forleftswitchbutton.
#define RIGHT_BUTTON GPIO_PIN_0
Createsa constantfor pin0 inthe GPIO APImodule rightswitchbutton.
#define NUM_DEBOUNCE_CHECKS 10
It checksbefore aswitchis debounced. Createsaconstantusedfor50msec debounce time.
#define TIMER0_FREQ 2
Createsa constantusedfor frequencyinthe TimerAPImacrowitha value of 2.
#define TIMER1_FREQ 200
Createsa constantusedfor frequencyinthe Timer APImacrowitha value of 200.
#define UART0_BAUDRATE 115200
Createsa constantusedfor baudrate inthe UART API macro witha of value 115200 bps.
#define NUM_DISP_TEXT_LINE 4
Createsa constantfor the numberof linesof textdisplayinthe characterpointer"disp_text"witha
value of 4.
void init_LEDs(void);
Thisline declaresthe functionprototype "init_LEDs".Declarationatthispointgivesthe actual functiona
global scope.Anyotherfunction,header,or.c file containedinthissource file isgivenaccesstothe
functionandaccessible bythe function.
void init_timer(void);
5. Thisline declaresthe functionprototype " init_timer".Declarationatthispointgivesthe actual function
a global scope.Anyotherfunction,header,or.cfile containedinthissource fileisgivenaccesstothe
functionandaccessible bythe function.
void init_UART(void);
Thisline declaresthe functionprototype " init_UART".Declarationatthispointgivesthe actual function
a global scope.Anyotherfunction,header,or.cfile containedinthissource fileisgivenaccesstothe
functionandaccessible bythe function.
void init_buttons(void);
Thisline declaresthe functionprototype " init_buttons".Declarationatthispointgivesthe actual
functionaglobal scope.Anyotherfunction,header,or.cfile containedinthissource fileisgivenaccess
to the functionandaccessible bythe function.
void set_button_states(void);
Thisline declaresthe functionprototype " set_button_states ".Declarationatthispointgivesthe actual
functionaglobal scope.Anyotherfunction,header,or.cfile containedinthissource fileisgivenaccess
to the functionandaccessible bythe function.
void Timer0_ISR(void);
Thisline declaresthe functionprototype " Timer0_ISR".Declarationat thispointgivesthe actual
functionaglobal scope.Anyotherfunction,header,or.cfile containedinthissource fileisgivenaccess
to the functionandaccessible bythe function.
void Timer1_ISR(void);
Thisline declaresthe functionprototype " Timer1_ISR".Declarationat thispointgivesthe actual
functionaglobal scope.Anyotherfunction,header,or.cfile containedinthissource fileisgiven access
to the functionandaccessible bythe function.
extern void UARTStdioIntHandler(void);
Thisline declaresafunctionprototype of type "extern".Thisinformsthe microprocessorthatitneedsto
access a functionthatexistsoutsideof thissource file.The uartstdio.cfileisincludedinthe project
folderfordirectaccess.The uartstdio.cfile hasadditional functionsforthe UARTconsole.Thisparticular
functionhandlesinterruptsfromthe UART.The UART has a transmitandreceive bufferthatis usedfor
data transfersbetweenthe microprocessorandthe puttyconsole.
uint32_t sys_clock;
Createsan unsigned32-bitglobal variable forthe systemclock.
uint8_t cur_LED = RED_LED;
6. Createsan unsigned8-bitglobal variable forthe systemclock.
const char *disp_text[NUM_DISP_TEXT_LINE] = {
"n",
"UART and LED Demon",
"H: help, R: red, G: green, B: blue.n",
"> " };
Thisline createsa pointer fora systemmessage communicated tothe userviaputtyconsole.
volatile uint8_t raw_button_states[NUM_DEBOUNCE_CHECKS];
Createsan unsigned8-bitglobal arrayfordebounce.
volatile uint32_t raw_button_states_index=0;
Createsan unsigned32-bitglobal variable forinitializing index pointerof state.
volatile uint8_t button_states=0;
Createsan unsigned8-bitglobal variable forinitializingdebounced state.
int main(void){
The main processcallsandacts on variables,macros,definitions,andothersystemfunctions.
uint32_t i;
Createsan unsigned32-bitvariable forloops.
unsigned char user_cmd;
Createsan unsignedcharactervariable foruserinput.
uint8_t saved_button_states=0, cur_button_states;
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SystemControl ClockSetsetsthe clockingof the device.Osc_Mainconfiguresthe oscillatorsource.
XTAL_16MHZ usesa 16 MHZ crystal clock. USE_PLL is a phase lockedloopat400MHZ. SYSDIV_5 divides
the clock bythe numberspecifiedgiving control of the frequency.
sys_clock = SysCtlClockGet();
Thisline retrievesthe processorclockrate andassignsit toa variable.
init_LEDs();
InitializesLEDconfigurationandenables by calling the function definition.
7. init_buttons();
Initializesbuttonsconfigurationandenables by calling the function definition.
init_UART();
InitializesUARTconfigurationandenables by calling the function definition.
init_timer();
InitializesTimerconfigurationandenables by calling the function definition.
IntMasterEnable();
ThisNVICAPIfunctionenablesinterruptsfromthe microprocessortointerruptcontroller.
TimerEnable(TIMER0_BASE, TIMER_A);
ThisTIMER API functionenablesoperationof the timer module.
TimerEnable(TIMER1_BASE, TIMER_A);
ThisTIMER API functionenablesoperationof the timer module.
for(i=0; i<NUM_DISP_TEXT_LINE; i++)
Thisline isa for loopto displayprogrammessage onconsole.
UARTprintf(disp_text[i]);
Thisfunctionprintsthe message onthe console.
while(1) {
The while loopprovidesacontinuousloopwhensetto"1".
if(UARTRxBytesAvail())
If the UART has available userinput.
user_cmd = UARTgetc();
Thisline retrievesthe userinputandstoresitina variable.
else
user_cmd = 0;
Else,the usercommandvariable issetto 0.
switch(user_cmd){
8. Switchcase for the userinputdata.
case 'r':
Switchcase for red.
case ' ':
Switchcase for empty.
case 'H':
Switchcase for H.
case 'h':
Switchcase for h.
for(i=0; i<NUM_DISP_TEXT_LINE; i++)
Switchcase display forlines87-90 is a for looptodisplayconsole message touserviaputtyconsole.
UARTprintf(disp_text[i]);
Thisfunctionprintsthe message onthe puttyconsole.
break;
Switchcase break.
case 'R':
Switchcase for redled.
case 'r':
Switchcase for redled.
cur_LED = RED_LED;
Storesthe red ledincurrentledvariable.
UARTprintf("n> ");
Thisfunctionprintsa newline witha> on the console.
break;
Switchcase break.
case 'B':
9. Switchcase for blue led.
case 'b':
Switchcase for blue led.
cur_LED = BLUE_LED;
Storesthe blue ledincurrentledvariable.
UARTprintf("n> ");
Thisfunctionprintsa newline witha> on the console.
break;
Switchcase break.
case 'G':
Switchcase for greenled.
case 'g':
Switchcase for greenled.
cur_LED = GREEN_LED;
Storesthe greenledincurrentledvariable.
UARTprintf("n> ");
Thisfunctionprintsa newline witha> on the console.
break;
Switchcase break.
// Check button states.
cur_button_states = button_states;
if(saved_button_states != cur_button_states){
if((~saved_button_states & LEFT_BUTTON) && (cur_button_states &
LEFT_BUTTON)) {
UARTprintf("Left button pushed down.n> ");
}
if((saved_button_states & LEFT_BUTTON) && (~cur_button_states &
LEFT_BUTTON)) {
UARTprintf("Left button released.n> ");
}
if((~saved_button_states & RIGHT_BUTTON) && (cur_button_states &
RIGHT_BUTTON)) {
10. UARTprintf("Right button pushed down.n> ");
}
if((saved_button_states & RIGHT_BUTTON) && (~cur_button_states &
RIGHT_BUTTON)) {
UARTprintf("Right button released.n> ");
}
if(cur_button_states == (LEFT_BUTTON | RIGHT_BUTTON)) {
UARTprintf("Both buttons held down.n> ");
}
saved_button_states = cur_button_states;
}
*The programcomparesincomingdatato saveddata. Whenthe data is notthe same,a nestedIF
statement ANDsall entriesof the array to configure the switchbuttonoutputdisplayonthe UART.
void init_LEDs(void)
User-definedfunctiondefinitionforinitializingLEDs.The functionreturnsavalue of 0.
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
The SystemControl APIfunctionenablesthe GPIOportF peripheral.
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
The GPIO APIfunction configurespins1,2, and3 of portF for use as GPIO outputs.
void init_timer(void)
User-definedfunctiondefinitionforinitializingTimer.The functionreturnsavalue of 0.
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
The SystemControl APIfunction enablesthe timer0peripheral.
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
The SystemControl APIfunctionenablesthe timer1peripheral.
TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
The TimerAPI functionconfiguresthe timerasa 32-bitfull-widthperiodictimer.
TimerLoadSet(TIMER0_BASE, TIMER_A, sys_clock/TIMER0_FREQ -1);
The TimerAPI functionspecifiesthe base addressforconfiguration,the correctname fora full-width
timer,andthe load value specifiedbyuser-definedconstants.
TimerConfigure(TIMER1_BASE, TIMER_CFG_PERIODIC);
11. The TimerAPI functionconfiguresthe timerasa 32-bitfull-widthperiodictimer.
TimerLoadSet(TIMER1_BASE, TIMER_A, sys_clock/TIMER0_FREQ -1);
The TimerAPI functionspecifiesthe base addressforconfiguration,the correctname fora full-width
timer,andthe load value specifiedbyuser-definedconstants.
IntRegister(INT_TIMER0A, Timer0_ISR);
The NVICAPIfunctionregistersthe "TIMER0_ISR"functiontobe calledwhenthe "TIMER0A"interruptis
enabled.
IntEnable(INT_TIMER0A);
The NVICAPIfunctionenables"TIMER0A"asa full-widthtimer tobe usedforthe interruptfunction
process.
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
The TimerAPI functionenablesthe specifictimermodule(TIMER0_Base) forthe timer interruptsource.
The bit maskof the interruptsource tobe enabledis"TIMER_TIMA_TIMEOUT".
IntRegister(INT_TIMER1A, Timer1_ISR);
The NVICAPIfunctionregistersthe "TIMER1_ISR"functiontobe calledwhenthe "TIMER0A"interruptis
enabled.
IntEnable(INT_TIMER1A);
The NVICAPIfunctionenables"TIMER1A"asa full-widthtimer tobe usedforthe interruptfunction
process.
TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
The TimerAPI functionenablesthe specifictimermodule(TIMER1_Base) forthe timerinterruptsource.
The bit maskof the interruptsource tobe enabledis"TIMER_TIMA_TIMEOUT".
void init_UART(void)
User-definedfunctiondefinitionforinitializingUART.The functionreturnsavalue of 0.
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
The SystemControl APIfunctionenablesthe UART0 peripheral.
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
The SystemControl APIfunctionenablesthe GPIOA peripheral.
12. GPIOPinConfigure(GPIO_PA0_U0RX);
The GPIO APIfunctionconfiguresthe alternate functionof aGPIO pin.GPIOPort A's pinmux is
configuredforthe UART peripheral.Pin0is configuredforthe UARTreceiverbuffer.
GPIOPinConfigure(GPIO_PA1_U0TX);
The GPIO APIfunctionconfiguresthe alternate functionof aGPIO pin.GPIOPort A's pinmux is
configuredforthe UART0 peripheral.Pin1isconfiguredforthe UART transmitterbuffer.
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
The GPIO APIfunctionconfigurespinsforuse bythe UART peripheral.GPIOPort A will be the peripheral
usedforUART communication.Pins0and1 of port A are available.
IntRegister(INT_UART0, UARTStdioIntHandler);
The NVICAPIfunctionregistersthe "UARTStdioIntHandler"functiontobe calledwhenthe "UART0"
interruptisenabled.
UARTStdioConfig(0, UART0_BAUDRATE, sys_clock);
The UART driverfunctionconfiguresthe UARTforinput/output.UARTPort0 isthe base that will be
used.The user-definedconstant"UART0_BAUDRATE"isthe bitrate forthe UART and the user-defined
constant "sys_clock"isthe frequencyusedforthe source clockof the UART module.
void Timer0_ISR(void)
User-definedfunctiondefinitionforinterrupthandler.The functionreturnsavalue of 0.
TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
The TimerAPI functionclearsthe timerinterruptsources.TIMER0 isthe base specifiedand
"TIMER_TIMA_TIMEOUT" isthe bitmaskfor the interruptsource cleared.
if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3)) {
If the GPIOAPIfunctionreadspins1,2, or 3 fromport F.
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0);
The GPIO APIfunctionwritesa0 to pins1,2, or 3.
else {
Else the GPIO APIfunction...
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, cur_LED);
Writesthe value of the variable "cur_LED" to the correct pin.
13. void Timer1_ISR(void)
User-definedfunctiondefinitionforinterrupthandler.The functionreturnsavalue of 0.
TimerIntClear(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
The TimerAPI functionclearsthe timerinterruptsources.TIMER1 isthe base specifiedand
"TIMER_TIMA_TIMEOUT" isthe bitmaskfor the interruptsource cleared.
set_button_states();
void init_buttons(void)
User-definedfunctiondefinitionfor switchbuttons.
uint32_t i
Createsan unsigned32-bitlocal index variable.
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
The SystemControl APIfunctionenablesthe GPIO peripheral portF.
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
Unlock port F from NMI as GPIO input pin.
14. HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= 0x01;
Configure port F base to enable pins 0 and 4.
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = 0;
Relock port F for permanent configuration.
GPIODirModeSet(GPIO_PORTF_BASE, LEFT_BUTTON|RIGHT_BUTTON, GPIO_DIR_MODE_IN);
The GPIO APIfunctionconfigurespins0and4 of portF for use as GPIO inputs.
GPIOPadConfigSet(GPIO_PORTF_BASE, LEFT_BUTTON|RIGHT_BUTTON,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
The GPIO APIfunctionconfigures pins0and4 of portF for weak pull-upbuttontype.
for(i=0; i<NUM_DEBOUNCE_CHECKS; i++)
raw_button_states[i] = 0;
The for loopmaintainsbounce statusfromuserinterface.
void set_button_states(void)
User-definedfunctiondefinitionforbuttonstates.
uint32_t i
Createsan unsigned32-bitlocal index variable.
uint8_t states = LEFT_BUTTON|RIGHT_BUTTON;
Createsan unsigned8-bitlocal GPIOportF pinnumber variable.
raw_button_states[raw_button_states_index] = ~ GPIOPinRead(GPIO_PORTF_BASE,
LEFT_BUTTON|RIGHT_BUTTON);
GPIO APIfunctionreadspins0 and4 from portF and storesstate in volatile memory.
if(raw_button_states_index >= NUM_DEBOUNCE_CHECKS-1)
raw_button_states_index = 0;
If the functionreads alarger index thanthe (debouncer - 1) checksfor, itstarts from0 again.
else
raw_button_states_index ++;
else the functionreadsasmallerindex andincrements.
for(i=0; i<NUM_DEBOUNCE_CHECKS; i++)
states = states & raw_button_states[i];