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Keynote: Machine Learning for Design Automation at DAC 2018
- 1. Manish Pandey Synopsys, Inc., Mountain View, CA Carnegie Mellon University, Pittsburgh, PA June 24, 2018 Keynote Talk Transforming EDA with Machine Learning Opportunities and Challenges
- 3. Design Productivity 3 [CCC Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond] HW Design Productivity with ML Gates Available/System Gates Designed/Day
- 4. Predict, Optimize, Recommend Tools Machine Learning Enabled tools and flows Predict, Optimize, Recommend Methodology/Flow [Synopsys 2018]
- 5. Applications across Design Abstractions 5 PARAMETEROPTIMIZATION DEBUGandRCARECOMMENDATION SILICON ENGINEERING FUNCT VERIFICATION SYNTHESIS PLACEMENT AUTOMATEDTESTSELECTION CHECKINRISK Performance, Accuracy, Faster Debug
- 6. Formal Verification: Improved Engine Throughput Assertion1 Assertion2 Assertion3 DESIGN Constraints Engine E1 Engine E2 Engine En + ML optimization Server Farm Property P1 Property P2 Property P3 Properties Dispatched to Formal Engines P1 P2 P3 … ML Optimization Challenges: • Hundreds/thousands of properties • 30+ formal engines/solvers • Fixed number of machines • Limited time • Numerous runs with incremental RTL changes Orchestration [Synopsys 2018] 6
- 7. Default Convergence ML Convergence Verification Throughput Optimization • Formal Verification problems are exponential in nature (NP complete) - - at some point little incremental progress will be made StateSpaceExplored Time and Compute Resources time & resources saved Gain [Synopsys 2018]
- 8. Optimizing Random Test Constraints Using RL • Constrained random simulation widely used to explore common and uncommon design corner cases – Generation of random instruction streams controlled through a set of adjustable constraints • Hard bugs difficult to find – Random distributions hit common case often • Insight: – Evaluate each test on its “quality” – Drive simulation coverage based on quality • Measuring Quality: – Non-trivial bugs require a combination of events and state changes to occur in close proximity => Approximation for “events lining up” = Two flops toggling in close proximity in time – This measure requires no understanding of the design Majority of Search Sokorac – DVCON 20178
- 9. Optimizing Random Test Constraints Using RL • Total toggle pairs a test produces: – indication of the volume of activity – Optimize for hard to hit bins that are rarely exercised • Having a “score” for a test good for learning algorithms – High score => High activity of rare events in the test • RL Algorithm – Select a random population of tests, and evaluate each • Create the next generation of tests by – Mutating (slightly adjusting constraints) current tests – Mating (take an average of two tests) current tests – Compute evaluation score based on toggle pair coverage • Select next round of tests based on evaluation score Sokorac – DVCON 2017 Toggle Matrix (Yellow=>high activity) 9
- 10. Static LP Verification: Noise Reduction and RCA (UPF) PST_VOLTA GE_DROPPE D? (UPF) UPF_SUPP LY_NOSTA TE (PG) PG_CSN_ CONN? VD D VDD1 VDDVDD1 1’b0 (DESIGN) LS_INST_TIEL O? iso1 ret1 iso2 iso3 ret3 ret4 ret5 ret6iso6 ret7 iso8 iso3 ret12 iso21 ret13 ret11 iso1 ret4 iso3 iso21 Encoding Dimensional ity reduction Clustering Score &Select Clusters 100K to Million Violations 10X Fewer Violations for Analysis Root Cause Information Root Cause Analysis [Synopsys 2018] 10
- 12. Deep Learning Exploits High-Quality Training Data to Reduce Dependence on Domain Expertise Training Data Machine Learning Mask Synthesis (ML) ! " #: ! → " Mask Synthesis (ILT+OPC) ! " Resist Simulation Fabrication and SEM Measurements Training Data Machine Learning PG Model ! " #: ! → " ! " Optics Simulation Full-Chip Resist Modeling Full-Chip Mask Synthesis [Synopsys 2018]12
- 13. Machine Learning Mask Synthesis Task : Predict Mask From Target Training Data DNN Mask Synthesis (ML) ! " #: ! → " Mask Synthesis (ILT+OPC) ! " X: Target (Input) Y: Mask (Output) [Synopsys 2018]13
- 14. Machine Learning Negative Tone Development (NTD) Model Calibration Training : Resist Simulation Fabrication and SEM Measurements Training Data Machine Learning System ML Model ! " #: ! → " ! " Optics Simulation Results : Input mask Predicted Resist ContourAerial Image ! " SEM images from IMEC Optics Simulation DL Model Comparison of Optical Iso-contour and Resist Contour [Synopsys 2018]14
- 15. Learn how to approximate the behavior of a computationally-expensive function from examples. Supervised Learning to Approximate Physics Systems Data Storage Model Training Platform Partial Differential Equation Solvers Example Simulated Results High-Speed Manufacturing Production Line Application Accelerated ML Model Development Phase : Training Data Generation and Model Training Manufacturing Phase : Inference [Synopsys 2018]15
- 16. Production Line Manufacturing Optimization Enable and Optimize Yield for Production-line Manufacturing Tools [Synopsys 2018] 16
- 17. 17 https://arxiv.org/pdf/1711.10907.pdf Deep RL Design Synthesis
- 18. Device Placement Optimization with RL 18 GPU 0 GPU 1 GPU 2 GPU 3 Where to place operations? Mirhoseini etal. ICML’17
- 19. Representation of Words 0 0 1 1 0 1 1 1 … 1 1 0 0 1 0 1 1 sentences words
- 20. Word2Vec • Matrix representation is very inefficient – Vocabulary of 100k words – Representation of word is a one-hot encoding – Representation of ”the dog is on the table” • R(”dog”) | R(”is”) | R(”on”) | R(”the”) | R(”table”) • ! ∶ #$%&' → {0,1}|/0123| • Can we find a representation that is denser than one-hot encoding 0 0 1 1 0 1 1 1 … 1 1 0 0 1 0 1 1 sentences words
- 21. Word2Vec • ! ∶ #$%&' → {0,1}. , / << |#$%&'| • |W(w1)| = 1 • cos 5, 6 = 8.: 8 : , 5 = ! #1 , 6 = !(#2) • king - queen + woman = man
- 22. Using ML/DL for Debugging • Using word2vec to code waveforms 0 0 1 1 0 1 1 1 … 1 1 0 0 1 0 1 1 cycles !"#$%&!'
- 23. 0 0 1 1 0 1 1 1 … 1 1 0 0 1 0 1 1 Using ML/DL for Debugging cycles !"#$%&!' 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 … 1 1 0 0 1 0 1 1 !"#$%&!'() A + B – C = D Can be used to extract relations/properties between events for any number of cycles
- 24. Optimize Engineering Productivity with ML Smarter Flows Productivity Auto Triaging – Failures, Bugs, and Logs Parameter Tuning and Optimization Actionable, Predictive Insights Quality Test Analytics Check-in Risk Advisor Global Release Dashboard Smarter Operations Cost Optimized Test Selection Optimized Grid Scheduling Real-time guidance, prescriptive insights, and resource optimization [Synopsys 2018]
- 25. SAT Solver Parameter Tuning and Solver Selection for Formal Verification • SAT is NP complete – Little hope we will find efficient solver that fits all problems • Different solvers have strengths and weaknesses – MiniSat, MarchSAT, … • Each solver has a number of parameters that can perform well on certain types of problems
- 26. Parameter Tuning and SAT Solver Selection Features 1. Property circuit level 2. SCOAP cycles 3. Number of flops uninitialized after RESET 4. Circuit Testability Index 5. Property Testability Index 6. SCOAP adjusted flops 7. SCMax 8. Number of flops 9. Number of gate bits 10. Number of free variables 11. Number of bits directly affected by constraints 12. Number of counters flops 13. Number of FSM flops 14. Number of memory array flops Penido et al, STTT 2010 We know the problem is NP complete, but different engines may affected differently by the features, some polynomially and some exponentially We attempt to optimize how many instances we can run to reduce the risk of a property not being proven
- 27. Tool Parameters Design Parameters Tool QoR, TTR Design Quality Metrics Customized Settings for Circuit Simulation Tool Parameters Tool Parameters Tool Parameters Design Parameters Design Parameters Design Parameters total_wire_length total_neg_slack frequency wall_time accuracy #memoryCells #stdcells #routingTracks #gates #signals heuristic-config user-config Parameters QoR ? Simulator [Synopsys 2018]27
- 28. Speed Accuracy Customized Tool Settings for Simulators – Cont’d set_capacitor_option -min 1e-@1@ -rule 1 set_ccap_option -ccap_to_gcap @2@ -ccap_to_scap @3@ set_dc_option -pwrnet_level 1 set_identification_rule -type force_digital -force_parasitic_diode digital set_model_option -merge_parallel_level @4@ -mos_bin_ratio @5@% set_option xa_cap_strong_coupling_ratio @6@ set_option xa_cap_weak_coupling_ratio @7@ set_option xa_collapse_external_bulk @8@ set_option xa_digital_cap_strong_coupling_ratio @9@ set_option xa_digital_cap_weak_coupling_ratio @10@ set_option xa_dynamic_table_grid_scale_by_vsupply @11@ set_option xa_handle_wireccap @12@ set_option xa_highcap_threshold @13@ set_option xa_lns_accept_ratio 0 set_option xa_moscap_optimization @14@ set_option xa_mtr_current_accuracy_notamc @15@ set_option xa_mtr_dpart_level @16@ set_option xa_op_auto_set_maxv_minv @17@ set_option xa_opt_post_layout_array_new_cap 1 set_option xa_optimize_rc 10 set_option xa_optimize_rc_cap_method @18@ set_option xa_optimize_rc_cap_ratio @19@ set_option xa_optimize_rc_cc_to_cg @20@ set_option xa_optimize_rc_ccnt_max @21@ set_option xa_optimize_rc_edge_ratio @22@ set_option xa_optimize_rc_intra_cc @23@ set_option xa_optimize_rc_mos_g_method @24@ set_option xa_optimize_rc_node_ccnt @25@ set_option xa_optimize_rc_node_ccnt_method @26@ set_option xa_optimize_rc_rcnt_max @27@ set_option xa_optimize_rc_tconst_max @28@ set_option xa_optimize_rc_tconst_max_mos @29@ set_option xa_prefdi_parallel_merge @30@ set_option xa_sole_fastcap_acceptance_ratio @31@ set_partition_level @32@ set_partition_option -widemos 0 -ap @33@ set_powernet_level @34@ set_powernet_option -ideal_rmax @35@ set_probe_option -skip_flat_pl_node 1 set_resistor_option -min @36@ -max @37@ -rule 1 set_sim_level @38@ set_synchronization_level @39@ set_tolerance_option @40@ set_waveform_option -compress_v 0.1m -compress_i 0.1n Active Machine Learning Good Settings Outlier Detection, Problem Discovery Config-space size ≈ 3#$ Sample circuits [Synopsys 2018]
- 29. Challenges • Data – Availability – Ownership • Model – Parameters – Model Details – Topology, Hyperparams 29
- 30. Easy: Data Availability • Does data reside in customer IT systems? • Is data shipped to tool vendor? • On-site learning vs off-line learning • Encryption/Anonymization 30 To ML Pipeline
- 31. Hard: Data Ownership • Who owns the data generated during tools runs on customer designs? – Value extraction ($$) • Can the data obtained from one customer’s design be used to improve the tool for another customer? 31 To ML Pipeline
- 32. Model • Parameters learned on customer site – Can these be shipped back to vendor? • Can this be used to refine models further by vendor into newer products? – Can these be shipped to other customers? • Similar questions for hyper params • Model type/topology IP – Does exposing to parameters/data expose IP? 32
- 33. Concluding Remarks • Opportunities for ML extend across all design abstraction levels – Large gains in performance and productivity • Creating labeled datasets for training is a must – Unsupervised, Semi-supervised and Reinforcement Learning provide powerful capabilities • Leverage ML for tool flows as well – Can provide significant ROI • Data availability and ownership issues must be resolved 33
- 34. Thank You 34
- 36. EDA – Fundamental Enabling Technology 36