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SHASHANK CHATURVEDI
ADD: SHASHANK CHATURVEDI
House No 83, GALI NO 2
BASELWA COLONEY
FARIDABAD, NEAR SEC-29
HARYANA
Email ID: shanky250489@gmail.com
Mobile : +919456051001, +919560788663
ACADEMIC BACKGROUND :
• B-Tech (2008-2012) [Electronics and Instrumentation Engineering] from IIMT College
Of Engineering, Greater Noida [Affiliated to GBTU, Lucknow] with an aggregate of
74.4%.
• Passed XII (2007) from HARMILAP MISSION SCHOOL, KANPUR [C.B.S.E Board] with an
Aggregate of 77.4%.
• Passed X (2005) from HARMILAP MISSION SCHOOL, KANPUR [C.B.S.E Board] with an
Aggregate of 77.6%.
PROFESSIONAL EXPERIENCE
• 1.5 year Experience as a Product Validation Engineer - II in Cadence Design
Systems.
• A total of 2 YEAR Experience as a DESIGN ENGINEER (LAYOUT) in SANKALP & KPIT
SEMICONDUCTOR PVT. LTD.
• Did 3 months VLSI Training in Sankalp , Hubli (180 nm technology) on LAYOUTS and did a
project in which made complete PLL from scratch to top.
• Gone through a 2 month on 40 nm technology in ST MICROELECTRONICS (As a
subcontractor) including the basics of layout.
Working on project in PLL team for 1.5 years on 28nmbulk, M40 and 28FDSOI technology in ST
MICROELECTRONICS (As a subcontractor). Made all the critical ANALOG BLOCKS in PLL team
including V.C.O, PFD, CHARGE PUMP, OP-AMP etc.
• Ran all kind of Packaging checks like LFD, LIBBE, PERC, TILING, Via REDUNDANCY etc
• Familiar With CAD Tools:-
Layout: - Virtuoso - 6.1.6, 6.1.7, 12.1, 12.2 Virtuoso L, XL (& GXL),
MODGEN, SRD
Layout Verification: - Caliber, LVS, DRC, PLS, Spice Model
Design: - Cadence Schematic Composer.
Operating System: - UNIX, Windows
Blocks Made: - PLL (V.C.O., PFD, Charge Pump, Op-amp, and BGR)
• Analog Electronics
• Digital Electronics
• Skill Language
• Network Analysis and Synthesis
ACADEMIC INTEREST:
• Microcontrollers.
• Microprocessor.
Latest Project Done :
C28SOI_VFCG_3000MHZ
Technology DK_cmos28FDSOI_AMS_6U1x_2U2x_2T8x_LB
Challenges
 Did Floor planning of critical blocks like CCO ring and rest of the VCO.
 Made the VCO Block for C28SOI_VFCG_3000MHZ.
 Made the blocks Like PFD, OP-Amp, Charge Pump and some Digital Blocks.
 Made all the block got it reviewed and delivered it in time.
EXTRA CURRICULAR ACTIVITIES:
• 1st
RUNNER-UP in the inter school chess champion ship at city level in Kanpur.
• Coordinator of the event named ELECTRONIC NETWORK ANALISIS AND DESIGN in
the Most SUCCESSFUL tech fest of greater Noida named SYNERGY-2010.
• Best project in the CETPA InfoTech from where I have done training on Embedded System
PERSONAL PROFILE
Name : Shashank Chaturvedi
Father’s Name : Mr. Uday Chandra Chaturvedi
Date of Birth : 25th
April 1989
Marital Status : single
Nationality : Indian
Language Known : Hindi & English
Country of Living : India
DECLARATION:
I hereby declare that above information is true and complete to the best of my knowledge.
Place:
Date: (SHASHANK CHATURVEDI)
Shashank_resume.doc

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Shashank_resume.doc

  • 1. SHASHANK CHATURVEDI ADD: SHASHANK CHATURVEDI House No 83, GALI NO 2 BASELWA COLONEY FARIDABAD, NEAR SEC-29 HARYANA Email ID: shanky250489@gmail.com Mobile : +919456051001, +919560788663 ACADEMIC BACKGROUND : • B-Tech (2008-2012) [Electronics and Instrumentation Engineering] from IIMT College Of Engineering, Greater Noida [Affiliated to GBTU, Lucknow] with an aggregate of 74.4%. • Passed XII (2007) from HARMILAP MISSION SCHOOL, KANPUR [C.B.S.E Board] with an Aggregate of 77.4%. • Passed X (2005) from HARMILAP MISSION SCHOOL, KANPUR [C.B.S.E Board] with an Aggregate of 77.6%. PROFESSIONAL EXPERIENCE • 1.5 year Experience as a Product Validation Engineer - II in Cadence Design Systems. • A total of 2 YEAR Experience as a DESIGN ENGINEER (LAYOUT) in SANKALP & KPIT SEMICONDUCTOR PVT. LTD. • Did 3 months VLSI Training in Sankalp , Hubli (180 nm technology) on LAYOUTS and did a project in which made complete PLL from scratch to top. • Gone through a 2 month on 40 nm technology in ST MICROELECTRONICS (As a subcontractor) including the basics of layout. Working on project in PLL team for 1.5 years on 28nmbulk, M40 and 28FDSOI technology in ST MICROELECTRONICS (As a subcontractor). Made all the critical ANALOG BLOCKS in PLL team including V.C.O, PFD, CHARGE PUMP, OP-AMP etc. • Ran all kind of Packaging checks like LFD, LIBBE, PERC, TILING, Via REDUNDANCY etc • Familiar With CAD Tools:- Layout: - Virtuoso - 6.1.6, 6.1.7, 12.1, 12.2 Virtuoso L, XL (& GXL), MODGEN, SRD Layout Verification: - Caliber, LVS, DRC, PLS, Spice Model Design: - Cadence Schematic Composer. Operating System: - UNIX, Windows Blocks Made: - PLL (V.C.O., PFD, Charge Pump, Op-amp, and BGR) • Analog Electronics • Digital Electronics • Skill Language • Network Analysis and Synthesis ACADEMIC INTEREST:
  • 2. • Microcontrollers. • Microprocessor. Latest Project Done : C28SOI_VFCG_3000MHZ Technology DK_cmos28FDSOI_AMS_6U1x_2U2x_2T8x_LB Challenges  Did Floor planning of critical blocks like CCO ring and rest of the VCO.  Made the VCO Block for C28SOI_VFCG_3000MHZ.  Made the blocks Like PFD, OP-Amp, Charge Pump and some Digital Blocks.  Made all the block got it reviewed and delivered it in time. EXTRA CURRICULAR ACTIVITIES: • 1st RUNNER-UP in the inter school chess champion ship at city level in Kanpur. • Coordinator of the event named ELECTRONIC NETWORK ANALISIS AND DESIGN in the Most SUCCESSFUL tech fest of greater Noida named SYNERGY-2010. • Best project in the CETPA InfoTech from where I have done training on Embedded System PERSONAL PROFILE Name : Shashank Chaturvedi Father’s Name : Mr. Uday Chandra Chaturvedi Date of Birth : 25th April 1989 Marital Status : single Nationality : Indian Language Known : Hindi & English Country of Living : India DECLARATION: I hereby declare that above information is true and complete to the best of my knowledge. Place: Date: (SHASHANK CHATURVEDI)