1. HOMEWORK#2
4 Stage Ring Oscillator based VCO
EECT7v88 High Speed Data
Communication Circuits
By Usama Awais
Instructor: Jin Liu
Department of Electrical Engineering
The University of Texas at Dallas
Contact: uxa140430@utdallas.edu

2. 2
FEATURES:
• Good control over delay + high
dynamic supply noise rejection
• A buffered version of PMOS
Vbias from Vctrl  Vbp
• Vctrl isolated from noise and
capacitive coupling
CHALLENGES:
• Ensuring stability with respect
to closed loop gain of diff. amp.
• Phase margin >=45

3. 3
Gain=45.25dB
PM= 53.5 deg

4. 4
FEATURES:
• Simplest implementation
consisting active loaded
differential amplifier followed by
source follower.
• Not so ideal in terms of high
dynamic supply noise rejection.
• VPBIAS applied to symmetric
load configuration covered in
homework 1.
Current Source = 187uA
Capacitors in Ring Oscillator= 10fF

5. 5

6. 6
• 256 point FFT with Rectangular window
Magnitude
dB

7. 7

8. 8
• 256 point FFT with Rectangular window
Magnitude
dB

9. 9
• Decrease in the overall amplitude = 452.4 p-p

10. 10
• 256 point FFT with Rectangular window
Magnitude
dB

11. 11
Slope = Kvco=
5.082GHz/V

12. 12
 Challenges included the low supply voltage (1.2V) and headroom
problems for the replica feedback bias circuit
 Overall good Kvco but design not strictly immune to supply noise
and process variations
 Future work includes integrating the Maneatis replica feedback
biasing instead of the simple feedback biasing in the charge pump
PLL

13. 13
 [1] J.G Meantis, “Low-Jitter Process-Independent DLL and PLL Based
on Self-Biased Techniques”, 2]IEEE JSSC VOL. 31, NO. 11,
NOVEMBER 1996
 [2] J.G Meantis, J.Kim, I. McClatchie,J. Maxey, M. Shankaradas, “Self-
Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock
Generator PLL”,IEEE JSSC VOL. 38, NO. 11, NOVEMBER 2003
 Sam Palermo, High Speed Links
 Elad Alon, EE290c
ACKNOWLEDGEMENTS:
Jiajun Ren and Hao Chen