This document describes hardware description languages (HDLs) which are textual languages used to describe digital circuits. It provides examples of describing simple circuits like an OR gate and door opener in VHDL, one of the most popular HDLs. It shows how to describe the structure of circuits, behavioral models, and testbenches to verify designs. Structures like a 4-bit carry ripple adder and register are demonstrated. Overall the document serves as an introduction to HDL concepts like modeling logic gates, circuits, and testing designs using languages like VHDL.

1. Hardware Description Languages
Digital Logic Design
Instructor: Kasım Sinan YILDIRIM

2. Introduction
• A drawing of a circuit, or schematic,
contains graphical information about
a design
– Inverter is above the OR gate,
AND gate is to the right, etc.
• Such graphical information may not
be useful for large designs
• Can use textual language instead si
g
t
o
c
o
n
t
r
a
tap
a
DoorOpener
c
h
p
f

3. Computer-Readable Textual Language for
Describing Hardware Circuits: HDLs
• Hardware description language (HDL)
– Intended to describe circuits textually, for a computer to read
– Evolved starting in the 1970s and 1980s
• Popular languages today include:
– VHDL –Defined in 1980s by U.S. military; Ada-like language
– Verilog –Defined in 1980s by a company; C-like language
– SystemC –Defined in 2000s by several companies; consists of libraries in
C++

4. Describing Structure in VHDL
DoorOpener
c
h
p
f
AND2_1
OR2_1
Inv_1
n2
n1
(a)
(b) (c)
We'll now describe a circuit whose name is DoorOpener.
The external inputs are c, h and p, which are bits.
The external output is f, which is a bit.
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
A 2-input OR gate, which has inputs x and y,
and bit output F.
A 2-input AND gate, which has bit inputs x and y,
and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connects to
external input c, and whose output connects to n1.
A 2-input OR gate named OR2_1, whose inputs
connect to external inputs h and p, and whose output
connects to n2.
A 2-input AND gate named AND2_1, whose inputs
connect to n1 and n2, and whose output connects to
external output f.
That's all.
l i b r a r y i e e e ;
u s e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Do o r Op e n e r i s
p o r t ( c , h , p : i n s t d _ l o g i c ;
f : o u t s t d _ l o g i c
) ;
e n d Do o r Op e n e r ;
a r c h i t e c t u r e Ci r c u i t o f Do o r Op e n e r i s
c o mp o n e n t I n v
p o r t ( x : i n s t d _ l o g i c ;
F : o u t s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
c o mp o n e n t OR2
p o r t ( x , y : i n s t d _ l o g i c ;
F : o u t s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
c o mp o n e n t AND2
p o r t ( x , y : i n s t d _ l o g i c ;
F : o u t s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
s i g n a l n 1 , n 2 : s t d _ l o g i c ; - - i n t e r n a l wi r e s
b e g i n
I n v _ 1 : I n v p o r t ma p ( x = > c , F = > n 1 ) ;
OR2 _ 1 : OR2 p o r t ma p ( x = > h , y = > p , F = > n 2 ) ;
AND2 _ 1 : AND2 p o r t ma p ( x = > n 1 , y = > n 2 , F = > f ) ;
e n d Ci r c u i t ;

5. Describing Combinational Behavior in VHDL
• Describing an OR gate's behavior
– Entity defines input/output ports
– Architecture
• Process – Describes behavior
– Behavior assigns a new value to
output port F, computed using
built-in operator "or"
library ieee;
use ieee.std_logic_1164.all;
entity OR2 is
port (x, y: in std_logic;
F: out std_logic );
end OR2;
architecture behavior of OR2 is
begin
process (x, y)
begin
F <= x or y;
end process ;
end behavior;
• Describing a custom function's behavior
– Desired function: f = c'*(h+p)
architecture beh of DoorOpener is
begin
process (c, h, p)
begin
f <= not (c) and (h or p);
end process ;
end beh;

6. Testbenches
• Testbench
– Assigns values to a system's inputs, check that system outputs
correct values
– A key use of HDLs is to simulate system to ensure design is correct
SystemToTest
Testbench
Set input
values,
check
output
values

7. Testbench in VHDL
• Entity
– No inputs or outputs
• Architecture
– Declares component to test, declares
signals
– Instantiates component, connects to
signals
– Process writes input signals, checks
output signal
• Waits a small amount of time after
writing input signals
• Checks for correct output value
using "assert" statement
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e nt i t y Te s t b e n c h i s
e nd Te s t b e n c h ;
a r c hi t e c t ur e b e h a v i o r of Te s t b e n c h i s
c ompone nt Do o r Op e n e r
por t ( c , h , p : i n s t d _ l o g i c ;
f : o u t s t d _ l o g i c
) ;
e nd c ompone nt ;
s i gna l c , h , p , f : s t d _ l o g i c ;
be gi n
Do o r Op e n e r 1 : Do o r Op e n e r por t ma p ( c , h , p , f ) ;
pr oc e s s
be gi n
- - c a s e 0
c < = ' 0 ' ; h < = ' 0 ' ; p < = ' 0 ' ;
wa i t f or 1 ns ;
a s s e r t ( f = ' 0 ' ) r e por t " Ca s e 0 f a i l e d " ;
- - c a s e 1
c < = ' 0 ' ; h < = ' 0 ' ; p < = ' 1 ' ;
wa i t f or 1 ns ;
a s s e r t ( f = ' 1 ' ) r e por t " Ca s e 1 f a i l e d " ;
- - ( c a s e s 2 - 6 o mi t t e d f r o m f i g u r e )
- - c a s e 7
c < = ' 1 ' ; h < = ' 1 ' ; p < = ' 1 ' ;
wa i t f or 1 ns ;
a s s e r t ( f = ' 0 ' ) r e por t " Ca s e 7 f a i l e d " ;
wa i t ; - - p r o c e s s d o e s n o t wa k e u p a g a i n
e nd pr oc e s s ;
e nd b e h a v i o r ;
SystemToTest
Testbench
Set input
values,
check
output
values
process
DoorOpener1

8. Describing a Full-Adder in VHDL
• Entity
– Declares inputs/outputs
• Architecture
– Described behaviorally (could
have been described
structurally)
– Process sensitive to inputs
– Computes expressions, sets
outputs
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e nt i t y Fu l l Ad d e r i s
por t ( a , b , c i : i n s t d _ l o g i c ;
s , c o : out s t d _ l o g i c
) ;
e nd Fu l l Ad d e r ;
a r c hi t e c t ur e b e h a v i o r of Fu l l Ad d e r i s
be gi n
pr oc e s s ( a , b , c i )
be gi n
s < = a x or b x or c i ;
c o < = ( b a nd c i ) or ( a a nd c i ) or ( a a nd b ) ;
e nd pr oc e s s ;
e nd b e h a v i o r ;
s = a xor b xor ci
co = bc + ac + ab
co
ci
b
a
s
Full
adder

9. 9
Describing a Carry-
Ripple Adder in VHDL
• Entity
– Declares inputs/outputs
– Uses std_logic_vector for 4-bit
inputs/outputs
• Architecture
– Described structurally by composing four
full-adders (could have been described
behaviorally instead)
– Declares full-adder component,
instantiates four full-adders, connects
• Note use of three internal signals for
connecting carry-out of one stage to
carry-in of next stage
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e nt i t y Ca r r y Ri p p l e Ad d e r 4 i s
por t ( a : i n s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
b : i n s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
c i : i n s t d _ l o g i c ;
s : out s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
c o : out s t d _ l o g i c
) ;
e nd Ca r r y Ri p p l e Ad d e r 4 ;
a r c hi t e c t ur e s t r u c t u r e of Ca r r y Ri p p l e Ad d e r 4 i s
c ompone nt Fu l l Ad d e r
por t ( a , b , c i : i n s t d _ l o g i c ;
s , c o : out s t d _ l o g i c
) ;
e nd c ompone nt ;
s i gna l c o 1 , c o 2 , c o 3 : s t d _ l o g i c ;
be gi n
Fu l l Ad d e r 1 : Fu l l Ad d e r
por t ma p ( a ( 0 ) , b ( 0 ) , c i , s ( 0 ) , c o 1 ) ;
Fu l l Ad d e r 2 : Fu l l Ad d e r
por t ma p ( a ( 1 ) , b ( 1 ) , c o 1 , s ( 1 ) , c o 2 ) ;
Fu l l Ad d e r 3 : Fu l l Ad d e r
por t ma p ( a ( 2 ) , b ( 2 ) , c o 2 , s ( 2 ) , c o 3 ) ;
Fu l l Ad d e r 4 : Fu l l Ad d e r
por t ma p ( a ( 3 ) , b ( 3 ) , c o 3 , s ( 3 ) , c o ) ;
e nd s t r u c t u r e ;
a3
co s
FA
co
b3 a2 b2
s3 s2 s1
ci
b
a
co s
FA
ci
b
a
a1 b1
co s
FA
ci
b
a
s0
a0 b0 ci
co s
FA
ci
b
a
co1
co2
co3

10. Describing a 4-bit Register in VHDL
• Entity
– 4 data inputs, 4 data outputs, and a clock
input
– Use std_logic_vector for 4-bit data
• I: in std_logic_vector(3 downto 0)
• I <= "1000" would assign I(3)=1, I(2)=0,
I(1)=0, I(0)=0
• Architecture
– Process sensitive to clock input
• First statement detects if change on clock
was a rising edge
• If clock change was rising edge, sets
output Q to input I
• Ports are signals, and signals store values
– thus, output retains new value until set
to another value
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e nt i t y Re g 4 i s
p o r t ( I : i n s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
Q: out s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
c l k : i n s t d _ l o g i c
) ;
e nd Re g 4 ;
a r c hi t e c t ur e b e h a v i o r of Re g 4 i s
be gi n
pr oc e s s ( c l k )
be gi n
i f ( c l k =' 1 ' a nd c l k ' e v e nt ) t he n
Q <= I ;
e nd i f ;
e nd pr oc e s s ;
e nd b e h a v i o r ;

11. 11
Describing an
Up-Counter in VHDL
• Described structurally (could have
been described behaviorally)
• Includes process that updates
output port C whenever internal
signal tempC changes
– Need tempC signal because
can't read C due to C being an
output port
ld
4-bit register
C
tc
4
4 4
4
cnt
4-bit up-counter
+1
l i b r a r y i e e e ;
u s e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e n t i t y Up Co u n t e r i s
p o r t ( c l k : i n s t d _ l o g i c ;
c n t : i n s t d _ l o g i c ;
C: o u t s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
t c : o u t s t d _ l o g i c
) ;
e n d Up Co u n t e r ;
a r c h i t e c t u r e s t r u c t u r e o f Up Co u n t e r i s
c o mp o n e n t Re g 4
por t ( I : i n s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
Q: o u t s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
c l k , l d : i n s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
c o mp o n e n t I n c 4
por t ( a : i n s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
s : o u t s t d _ l o g i c _ v e c t o r ( 3 downt o 0 )
) ;
e n d c o mp o n e n t ;
c o mp o n e n t AND4
por t ( w, x , y , z : i n s t d _ l o g i c ;
F : o u t s t d _ l o g i c
) ;
e n d c o mp o n e n t ;
s i g n a l t e mp C: s t d _ l o g i c _ v e c t o r ( 3 downt o 0 ) ;
s i g n a l i n c C: s t d _ l o g i c _ v e c t o r ( 3 d o wn t o 0 ) ;
b e g i n
Re g 4 _ 1 : Re g 4 por t ma p ( i n c C, t e mp C, c l k , c n t ) ;
I n c 4 _ 1 : I n c 4 por t ma p ( t e mp C, i n c C) ;
AND4 _ 1 : AND4 por t ma p ( t e mp C( 3 ) , t e mp C( 2 ) ,
t e mp C( 1 ) , t e mp C( 0 ) , t c ) ;
o u t p u t C: p r o c e s s ( t e mp C)
b e g i n
C < = t e mp C;
e n d pr oc e s s ;
e n d s t r u c t u r e ;
tempC

12. Describing an Oscillator in VHDL
• Entity
– Defines clock output
• Architecture
– Process
• Has no sensitivity list, so
executes non-stop as infinite
loop
• Sets clock to 0, waits 10 ns, sets
clock to 1, waits 10 ns, repeats
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
e nt i t y Os c i s
por t ( c l k : out s t d _ l o g i c ) ;
e nd Os c ;
a r c hi t e c t ur e b e h a v i o r of Os c i s
be gi n
pr oc e s s
be gi n
c l k < = ' 0 ' ;
wa i t f or 1 0 ns ;
c l k < = ' 1 ' ;
wa i t f or 1 0 ns ;
e nd pr oc e s s ;
e nd b e h a v i o r ;

13. Describing a Controller
in VHDL
Inputs: b; Outputs: x
On2
On1 On3
Off
x=1
x=1
x=1
x=0
b’
b
l i b r a r y i e e e ;
u s e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l
e n t i t y L a s e r T i me r i s
p o r t ( b : i n s t d _ l o g i c ;
x : o u t s t d _ l o g i c ;
c l k , r s t : i n s t d l o g i c
) ;
e n d L a s e r T i me r ;
a r c h i t e c t u r e b e h a v i o r o f L a s e r T i me r i s
t y p e s t a t e t y p e i s
( S_ Of f , S_ On 1 , S_ On 2 , S_ On 3 ) ;
s i g n a l c u r r e n t s t a t e , n e x t s t a t e :
s t a t e t y p e ;
b e g i n
s t a t e r e g : p r o c e s s ( c l k , r s t )
b e g i n
i f ( r s t = ' 1 ' ) t h e n - - i n t i a l s t a t e
c u r r e n t s t a t e < = S_ Of f ;
e l s i f ( c l k = ' 1 ' a n d c l k ' e v e n t ) t h e n
c u r r e n t s t a t e < = n e x t s t a t e ;
e n d i f ;
e n d p r o c e s s ;
c o mb l o g i c : p r o c e s s ( c u r r e n t s t a t e , b )
b e g i n
c a s e c u r r e n t s t a t e i s
wh e n S_ Of f = >
x < = ' 0 ' ; - - l a s e r o f f
i f ( b = ' 0 ' ) t h e n
n e x t s t a t e < = S_ Of f ;
e l s e
n e x t s t a t e < = S_ On 1 ;
e n d i f ;
wh e n S_ On 1 = >
x < = ' 1 ' ; - - l a s e r o n
n e x t s t a t e < = S_ On 2 ;
wh e n S_ On 2 = >
x < = ' 1 ' ; - - l a s e r s t i l l o n
n e x t s t a t e < = S_ On 3 ;
wh e n S_ On 3 = >
x < = ' 1 ' ; - - l a s e r s t i l l o n
n e x t s t a t e < = S_ Of f ;
e n d c a s e ;
e n d p r o c e s s ;
e n d b e h a v i o r ;
• FSM behavior captured using architecture with
2 processes
– First process models state register
• Asynchronous reset sets state to "S_Off"
• Rising clock edge sets currentstate to nextstate
– Second process models combinational logic
• Sensitive to currentstate and FSM inputs
• Sets FSM outputs based on currentstate
• Sets nextstate based on currentstate and present
FSM input values
– Note declaration of new type, statetype
Combinational
logic
State register
s1 s0
n1
n0
x
b
clk
FSM
inputs
FSM
outputs

14. Summary
• Hardware Description Languages (HDLs) are widely used in
modern digital design
– Textual rather than graphical language sufficient for many
purposes
– HDLs are computer-readable
– Great for simulation
• VHDL, Verilog, and SystemC are popular
• Introduced languages mainly through examples
• Numerous HDL books exist to teach each language in more
detail