Advanced 5G wireless infrastructure should support any-to-any connectivity between densely arranged smart objects that form the emerging paradigm known as the Internet of Everything (IoE). While traditional wireless networks enable communication between devices using a single technology, 5G networks will need to support seamless connectivity between heterogeneous wireless objects, and consequently enable the proliferation of IoE networks. To tackle the complexity and versatility of the future IoE networks, 5G has to guarantee optimal usage of both spectrum and energy resources and further support technology-agnostic connectivity between objects. This can be realized by combining intelligent network control with adaptive software-defined air interfaces. In order to achieve this, current radio technology paradigms like Cloud RAN and Software Defined Radio (SDR) utilize centralized baseband signal processing mainly performed in software. With traditional SDR platforms, composed of separate radio and host commodity computer units, computationally-intensive signal processing algorithms and high-throughput connectivity between processing units are hard to realize. In addition, significant power consumption and large form factor may preclude any real-life deployment of such systems. On the other hand, modern hybrid FPGA technology tightly couples a FPGA fabric with hard core CPU on a single chip. This provides opportunities for implementing air interfaces based on hardware/software co-processing, resulting in increased processing throughput, reduced form factor and power consumption, while at the same time preserving flexibility. This paper examines how hybrid FPGAs can be combined with novel ideas such as RF Network-on-Chip (RFNoC) and partial reconfiguration, to form a flexible and compact platform for implementing low-power adaptive air interfaces. The proposed platform merges software and hardware processing units of SDR systems on a single chip. Therefore, it can provide interfaces for on-the-fly composition and reconfiguration of software and hardware radio modules. The resulting system enables the abstraction of air interfaces, where each access technology is composed of a structured sequence of modular radio processing units.
Design and implementation of sdr based qpsk transceiver using fpgaTarik Kazaz
Software-defined radio (SDR) technology enables
implementation of wireless devices that support multiple air interfaces and modulation formats, which is very important
if consider the proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP
Builder Tool combined with Matlab/Simulink, Modelsim and
Quartus II design tools. As reconfigurable hardware platform
we used Altera DE2-115 development and education board with
AD/DA daughter card. Software and Hardware-in-the-loop (HIL)
simulation was conducted before hardware implementation and
verification of designed system. This method of design makes
implementation of SDR based modulators simpler ad faster.
Index Terms—SDR, FPGA, QPSK, DSP Builder, NCO, RRC
Universal software defined radio development platformBertalan EGED
Award winning presentation at a NATO RTO IST symposium in 2006 on Universal Software Defined Radio (SDR) Development Platform and its use for prototyping radar system and spectrum monitoring receiver. Till this time I made several presentations on the topic, but this is the original version from 2006.
Design and implementation of sdr based qpsk transceiver using fpgaTarik Kazaz
Software-defined radio (SDR) technology enables
implementation of wireless devices that support multiple air interfaces and modulation formats, which is very important
if consider the proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP
Builder Tool combined with Matlab/Simulink, Modelsim and
Quartus II design tools. As reconfigurable hardware platform
we used Altera DE2-115 development and education board with
AD/DA daughter card. Software and Hardware-in-the-loop (HIL)
simulation was conducted before hardware implementation and
verification of designed system. This method of design makes
implementation of SDR based modulators simpler ad faster.
Index Terms—SDR, FPGA, QPSK, DSP Builder, NCO, RRC
Universal software defined radio development platformBertalan EGED
Award winning presentation at a NATO RTO IST symposium in 2006 on Universal Software Defined Radio (SDR) Development Platform and its use for prototyping radar system and spectrum monitoring receiver. Till this time I made several presentations on the topic, but this is the original version from 2006.
SCA To Date and Motivation for Change. These slides will discuss why the JTRS Program Executive Office (JPEO) is aggressively procuring Software Defined Radio (SDR) consortium and industry assistance to spearhead a high impact evolution of the Software Communications Architecture (SCA) intended to deliver better radio performance along with a smaller footprint for waveforms and radio software. The webcast audience will learn about innovative SCA change proposal details and identified opportunities for near term radio performance impact with rapid market availability of these new capabilities via highly motivated COTS SDR software and development tool vendors.
Introduction to Software Defined Radio (SDR)Pamela O'Shea
For less than $20 anyone can listen to the airwaves! In this workshop, we will look at what is around us in the airwaves, including frequency scanning, pagers, airplanes, remote controls and more. Please see associated worksheet for the exercises.
SDR Training with HackRF - Tonex TrainingBryan Len
Length: 3 Days
SDR Training with HackRF, Advanced Software Defined Radio Training is a 3-day hands-on advanced SDR training course, Software-Defined Radio Development with GNU Radio utilizing HackRF One. The 3-day advanced SDR covers both hypothesis and application of SDR utilizing HackRF One.
.
SDR Training with HackRF. Advanced Software Defined Radio Training.
Participants will learn about:
Software Defined Radio and Digital Signal Processing
Theory and practice with hands-on SDR implementations using the Universal Software Radio Peripheral (USRP) SDR platforms
Necessary SDR signal processing building blocks, SDR application development using Python and C++ concepts required for GNU Radio development
How to apply HackRF and GNU Radio
How to use and apply GNU Radio Companion (GRC)
Security applications of SDR and RF Vulnerabilities
Course Agenda
Principles of Signal processing and applied RF
Overview of SDR
Overview of GNU Radio
Overview of GNU Radio software libraries
Overview of GNU Radio Companion (GRC)
Overview of Python and C++
Overview of Linux
Overview of Universal software radio peripherals
SDR and GNU Radio modules
Systems using HackRF One
Assessments of physical RF devices
How to Fingerprint on RF spectrum?
Hunting signals
Hardware Hacking 101
Reversing and Instrumentation (embedded RF systems)
IoT Hacking with SDR
Overview of Wi-Fi and Bluetooth
Open source SDR LTE software / FM Radio
Principles of Radar detector
Principles of Remote Controlled Cars
SDR Offensive Security
Request more information regarding SDR Training with HackRF. Visit tonex.com for course and workshop detail.
SDR Training with HackRF - Tonex Training
https://www.tonex.com/training-courses/sdr-training-with-hackrf-advanced-software-defined-radio-training/
A Glimpse into Developing Software-Defined Radio by PythonAlbert Huang
Software-defined radio~(SDR) has been emerging for many years in
various fields, including military, commercial communication
systems, and scientific research, e.g. space exploration. GNU Radio
is an open source SDR framework written in Python. This talk will introduce from basic concept of software-defined radio and various
front-end hardware, and then illustrate how to use Python to develop
SDR.
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
SCA To Date and Motivation for Change. These slides will discuss why the JTRS Program Executive Office (JPEO) is aggressively procuring Software Defined Radio (SDR) consortium and industry assistance to spearhead a high impact evolution of the Software Communications Architecture (SCA) intended to deliver better radio performance along with a smaller footprint for waveforms and radio software. The webcast audience will learn about innovative SCA change proposal details and identified opportunities for near term radio performance impact with rapid market availability of these new capabilities via highly motivated COTS SDR software and development tool vendors.
Introduction to Software Defined Radio (SDR)Pamela O'Shea
For less than $20 anyone can listen to the airwaves! In this workshop, we will look at what is around us in the airwaves, including frequency scanning, pagers, airplanes, remote controls and more. Please see associated worksheet for the exercises.
SDR Training with HackRF - Tonex TrainingBryan Len
Length: 3 Days
SDR Training with HackRF, Advanced Software Defined Radio Training is a 3-day hands-on advanced SDR training course, Software-Defined Radio Development with GNU Radio utilizing HackRF One. The 3-day advanced SDR covers both hypothesis and application of SDR utilizing HackRF One.
.
SDR Training with HackRF. Advanced Software Defined Radio Training.
Participants will learn about:
Software Defined Radio and Digital Signal Processing
Theory and practice with hands-on SDR implementations using the Universal Software Radio Peripheral (USRP) SDR platforms
Necessary SDR signal processing building blocks, SDR application development using Python and C++ concepts required for GNU Radio development
How to apply HackRF and GNU Radio
How to use and apply GNU Radio Companion (GRC)
Security applications of SDR and RF Vulnerabilities
Course Agenda
Principles of Signal processing and applied RF
Overview of SDR
Overview of GNU Radio
Overview of GNU Radio software libraries
Overview of GNU Radio Companion (GRC)
Overview of Python and C++
Overview of Linux
Overview of Universal software radio peripherals
SDR and GNU Radio modules
Systems using HackRF One
Assessments of physical RF devices
How to Fingerprint on RF spectrum?
Hunting signals
Hardware Hacking 101
Reversing and Instrumentation (embedded RF systems)
IoT Hacking with SDR
Overview of Wi-Fi and Bluetooth
Open source SDR LTE software / FM Radio
Principles of Radar detector
Principles of Remote Controlled Cars
SDR Offensive Security
Request more information regarding SDR Training with HackRF. Visit tonex.com for course and workshop detail.
SDR Training with HackRF - Tonex Training
https://www.tonex.com/training-courses/sdr-training-with-hackrf-advanced-software-defined-radio-training/
A Glimpse into Developing Software-Defined Radio by PythonAlbert Huang
Software-defined radio~(SDR) has been emerging for many years in
various fields, including military, commercial communication
systems, and scientific research, e.g. space exploration. GNU Radio
is an open source SDR framework written in Python. This talk will introduce from basic concept of software-defined radio and various
front-end hardware, and then illustrate how to use Python to develop
SDR.
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
This presentation is a great overview about the capabilities and shortfalls of current SDR Transceivers. The presentation was created and presented by Claudio, I4LEC in September 2012 at the HamRadioWeb Convention in Bologna, Italy.
ODSA Proof of Concept SmartNIC Speeds & FeedsODSA Workgroup
Achronix presented, "ODSA Proof of Concept SmartNIC Speeds & Feeds," at the ODSA Workshop. The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
Spectra IP Core ORB - high-performance, low-latency solution for FPGA-GPP com...ADLINK Technology IoT
Various approaches have been developed for integrating FPGA and GPP application components in a Software Communications Architecture (SCA) radio. Most of these have been less than successful, primarily due to overhead, latency and/or maintainability issues. Spectra IP Core is a second-generation solution to FPGA-GPP component integration that provides a low-latency, standards-based CORBA protocol with excellent performance metrics and the robustness of a proven, deployed solution. Building on PrismTech’s ICO v1, Spectra IP Core is a second-generation COTS product. This webcast will introduce the Spectra IP Core architecture, its main functions and its performance benchmarks. Although FPGA ‘middleware’ is a new concept for many FPGA developers, the capabilities provided by Spectra IP Core not only provide valuable integration ‘hooks’, but also help support a highly-efficient, proven radio component that simplifies the integration of high-level software development with digital design and accelerates the development of SCA-compliant FPGA components for SCA radios. These slides will be of great interest and value to project managers, systems engineers and architects as well as software and digital engineers involved in designing, building and testing SCA-compliant SDRs.
High Speed Data Connectivity: More Than Hardware (Design Conference 2013)Analog Devices, Inc.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
At Microsoft’s annual developers conference, Microsoft Azure CTO Mark Russinovich disclosed major advances in Microsoft’s hyperscale deployment of Intel field programmable gate arrays (FPGAs). These advances have resulted in the industry’s fastest public cloud network, and new technology for acceleration of Deep Neural Networks (DNNs) that replicate “thinking” in a manner that’s conceptually similar to that of the human brain.
Watch the video: http://wp.me/p3RLHQ-gNu
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
DPDK Summit 2015 - NTT - Yoshihiro NakajimaJim St. Leger
DPDK Summit 2015 in San Francisco.
NTT presentation by Yoshihiro Nakajima.
For additional details and the video recording please visit www.dpdksummit.com.
Fully programmable SmartNICs allow new offloads like OVS, eBPF, P4 or vRouter, and the Linux kernel is changing for supporting them. Having these same offloads when using DPDK is a possibility although the implications are not clear yet. Alejandro Lucero presented Netronome’s perspective for adding such a support to DPDK mainly for OVS and eBPF.
Spectra Operating Environment (OE) - Setting a new standard for high performance SCA compliant radio development.
A presentation about the SCA Operating Environment, requirements, a business case for COTS OE & an introduction to Spectra OE and its benefits, performance & complementary products.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
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Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
2. Overview
Common SDR approach
Propposed approach
Hardware accelerated SDR
Use case example
3. Common SDR approach
Intensive signal processing is done in host PC
No real time processing
Significant power and space consumption (no portability)
FPGA is seriously underutilized!
USRP
Host PC
?
13. Hardware accelerated SDR platform on top of Zynq
Xilinx Zynq
Dual Core ARM Cortex A9
GNU Radio
FPGA Accelerated
Block
Linux Kernel Device Driver
ARM to FPGA Interface
FPGA Accelerator
FPGA Fabric
ARM
TFlow
GnuRadio with HW
acceleration capabilities
GReasy
ARM - FPGA
shared memory
separate control and data
plane interfaces
14. Hardware accelerated SDR platform on top of Zynq
This concept enables
Offload of GnuRadio blocks
to FPGA
Frees up processor to
perform other tasks
15. Hardware accelerated SDR platform on top of Zynq
This concept enables
Offload of GnuRadio blocks
to FPGA
Real time reconfigurability
Frees up processor to
perform other tasks
Configuration
Port or ICAP
Configuration
Port Full
Bit File
Partial
Bit Files
FunctionA1
FunctionB1
FunctionC1FunctionC2
FunctionB2
FunctionA2FunctionA3
16. Hardware accelerated SDR platform on top of Zynq
This concept enables
Offload of GnuRadio blocks
to FPGA
Whole SDR system should
fit on one board
Real time reconfigurability
Frees processor to perform
other tasks
17. Example Scenario
Different applications –
different wireless standards
Our platform should support
various existing and future
emerging wireless technologies
at same time
IoT-CUBE HUB IoT-CUBE HUB
Internet
Repository
of SDR
library and
HW ACC
802.11g
device 802.11ac
device
802.15.4
device
BLE
device
802.11ah
xyz
device
Download SDR packages from
cloud Wireless as a Service
18. First step
Locally reconfiguring FPGA part of
platform
Changing 802.15.4 Tx with 802.11g
Tx
Bitstream for 802.11g is stored
locally on SD memory card
Sniffing simultaneously 802.11g and
802.15.4 packets to detect
reconfiguration
IoT-CUBE HUB
SD memory
card
802.11g
device
802.15.4
device
Intensive signal processing is done in host PC, on processor,
- We know that CPUs have sequential-general propose nature, because of that there
is no guarantee that certain processing task could be completed on time (or better to say there is no real time processing)
- As a result limited number of radios can be supported with traditional SDR platforms
- Also this approach implies the usage of host PC, which consumes significant power and space and precludes
deployment of such a system in real life
In same time USRP with FPGA as main processing unit is used just as interface for simple down/up conversion to/from baseband towards IF and RF
- FPGA which is typically good candidate for dedicated parallel processing is in practice underutilized
This is block scheme typical OFDM transmitter
Which contains several units in baseband processing chain
Realization of such system in GnuRadio would assume that all baseband processing is done on HOST PC
While USRP with FPGA as main processing unit is used just for simple up conversion of signal from baseband to (IF or RF) or vice versa
But there are 2 algorithms or processing blocks in transmitter chain
1. which are computationally intensive compared to others: IFFT and pulse shaping filtering
General proposed processor is not dedicated for parallel and real time processing
- Implementation of those algorithms on general proposed processor can imply that they will be bottlenecks of system
1. In same time the FPGA is underutilized at all, while those algorithms could be implemented on it
1. Obviously some things are done wrong in common
Such a platform could be formed on top of Zynq SoC as it contains ARM (as an CPU) processing unit and
FPGA on a single chip.
There are several tools that should be run on ARM to form SW part of platform
- TFlow is tool used for bitstream construction, which places and routes parameterized pre-compiled modules into a FPGA bitstream, and does so in a few seconds time (at least based on
paper) – similar like software-only flow
- Standard GnuRadio library is extended with HW accelerated blocks
- Those two SW components are forming SDR framework which is called Greasy, originally developing is started computational laboratory at Virginia Institute of Technology.
3. Between ARM and FPGA there 4 high throughput interfaces which are used as data plane interface for forwarding samples
4. Memory mapped interfaces are used as control plane interfaces for control of FPGA accelerators from GnuRadio
1. What this approach certainly enables is offloading of computationally intensive GnuRadio blocks to FPGA
2. This frees up processor to perform other tasks
1. With addition of Partial Reconfiguration this approach could enable even real time configurability (less then 10ms)
2. Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption.
1. Such a system should be able to fit on one small PCB board which would enable usage of SDR in real life scenarios
Here we will show example usage of such a platform in real life scenario. In future there will be more
and more devices which will use different wireless technologies for establishing connectivity
Also every few years there is new wireless standard emerging
In order to support connectivity of devices that are using various technologies there is need
for development of some sort of upgradable IoT gateway (we can call it IoT-CUBE HUB)
SW part of IoT-CUBE HUB should have ability to download new SDR packages from cloud and to reprogram both HW and SW radio parts on SoC.
We can see this concept as Wireless as a Service)
As a first step we plan to illustrate the switching between two technologies - ZigBee and Wifi Tx
While bitstream for reconfiguration would be loaded on SD memory card, instead of downloading from remote repository