Award winning presentation at a NATO RTO IST symposium in 2006 on Universal Software Defined Radio (SDR) Development Platform and its use for prototyping radar system and spectrum monitoring receiver. Till this time I made several presentations on the topic, but this is the original version from 2006.
Hardware Accelerated Software Defined Radio Tarik Kazaz
Advanced 5G wireless infrastructure should support any-to-any connectivity between densely arranged smart objects that form the emerging paradigm known as the Internet of Everything (IoE). While traditional wireless networks enable communication between devices using a single technology, 5G networks will need to support seamless connectivity between heterogeneous wireless objects, and consequently enable the proliferation of IoE networks. To tackle the complexity and versatility of the future IoE networks, 5G has to guarantee optimal usage of both spectrum and energy resources and further support technology-agnostic connectivity between objects. This can be realized by combining intelligent network control with adaptive software-defined air interfaces. In order to achieve this, current radio technology paradigms like Cloud RAN and Software Defined Radio (SDR) utilize centralized baseband signal processing mainly performed in software. With traditional SDR platforms, composed of separate radio and host commodity computer units, computationally-intensive signal processing algorithms and high-throughput connectivity between processing units are hard to realize. In addition, significant power consumption and large form factor may preclude any real-life deployment of such systems. On the other hand, modern hybrid FPGA technology tightly couples a FPGA fabric with hard core CPU on a single chip. This provides opportunities for implementing air interfaces based on hardware/software co-processing, resulting in increased processing throughput, reduced form factor and power consumption, while at the same time preserving flexibility. This paper examines how hybrid FPGAs can be combined with novel ideas such as RF Network-on-Chip (RFNoC) and partial reconfiguration, to form a flexible and compact platform for implementing low-power adaptive air interfaces. The proposed platform merges software and hardware processing units of SDR systems on a single chip. Therefore, it can provide interfaces for on-the-fly composition and reconfiguration of software and hardware radio modules. The resulting system enables the abstraction of air interfaces, where each access technology is composed of a structured sequence of modular radio processing units.
SCA To Date and Motivation for Change. These slides will discuss why the JTRS Program Executive Office (JPEO) is aggressively procuring Software Defined Radio (SDR) consortium and industry assistance to spearhead a high impact evolution of the Software Communications Architecture (SCA) intended to deliver better radio performance along with a smaller footprint for waveforms and radio software. The webcast audience will learn about innovative SCA change proposal details and identified opportunities for near term radio performance impact with rapid market availability of these new capabilities via highly motivated COTS SDR software and development tool vendors.
Hardware Accelerated Software Defined Radio Tarik Kazaz
Advanced 5G wireless infrastructure should support any-to-any connectivity between densely arranged smart objects that form the emerging paradigm known as the Internet of Everything (IoE). While traditional wireless networks enable communication between devices using a single technology, 5G networks will need to support seamless connectivity between heterogeneous wireless objects, and consequently enable the proliferation of IoE networks. To tackle the complexity and versatility of the future IoE networks, 5G has to guarantee optimal usage of both spectrum and energy resources and further support technology-agnostic connectivity between objects. This can be realized by combining intelligent network control with adaptive software-defined air interfaces. In order to achieve this, current radio technology paradigms like Cloud RAN and Software Defined Radio (SDR) utilize centralized baseband signal processing mainly performed in software. With traditional SDR platforms, composed of separate radio and host commodity computer units, computationally-intensive signal processing algorithms and high-throughput connectivity between processing units are hard to realize. In addition, significant power consumption and large form factor may preclude any real-life deployment of such systems. On the other hand, modern hybrid FPGA technology tightly couples a FPGA fabric with hard core CPU on a single chip. This provides opportunities for implementing air interfaces based on hardware/software co-processing, resulting in increased processing throughput, reduced form factor and power consumption, while at the same time preserving flexibility. This paper examines how hybrid FPGAs can be combined with novel ideas such as RF Network-on-Chip (RFNoC) and partial reconfiguration, to form a flexible and compact platform for implementing low-power adaptive air interfaces. The proposed platform merges software and hardware processing units of SDR systems on a single chip. Therefore, it can provide interfaces for on-the-fly composition and reconfiguration of software and hardware radio modules. The resulting system enables the abstraction of air interfaces, where each access technology is composed of a structured sequence of modular radio processing units.
SCA To Date and Motivation for Change. These slides will discuss why the JTRS Program Executive Office (JPEO) is aggressively procuring Software Defined Radio (SDR) consortium and industry assistance to spearhead a high impact evolution of the Software Communications Architecture (SCA) intended to deliver better radio performance along with a smaller footprint for waveforms and radio software. The webcast audience will learn about innovative SCA change proposal details and identified opportunities for near term radio performance impact with rapid market availability of these new capabilities via highly motivated COTS SDR software and development tool vendors.
SDR Training with HackRF - Tonex TrainingBryan Len
Length: 3 Days
SDR Training with HackRF, Advanced Software Defined Radio Training is a 3-day hands-on advanced SDR training course, Software-Defined Radio Development with GNU Radio utilizing HackRF One. The 3-day advanced SDR covers both hypothesis and application of SDR utilizing HackRF One.
.
SDR Training with HackRF. Advanced Software Defined Radio Training.
Participants will learn about:
Software Defined Radio and Digital Signal Processing
Theory and practice with hands-on SDR implementations using the Universal Software Radio Peripheral (USRP) SDR platforms
Necessary SDR signal processing building blocks, SDR application development using Python and C++ concepts required for GNU Radio development
How to apply HackRF and GNU Radio
How to use and apply GNU Radio Companion (GRC)
Security applications of SDR and RF Vulnerabilities
Course Agenda
Principles of Signal processing and applied RF
Overview of SDR
Overview of GNU Radio
Overview of GNU Radio software libraries
Overview of GNU Radio Companion (GRC)
Overview of Python and C++
Overview of Linux
Overview of Universal software radio peripherals
SDR and GNU Radio modules
Systems using HackRF One
Assessments of physical RF devices
How to Fingerprint on RF spectrum?
Hunting signals
Hardware Hacking 101
Reversing and Instrumentation (embedded RF systems)
IoT Hacking with SDR
Overview of Wi-Fi and Bluetooth
Open source SDR LTE software / FM Radio
Principles of Radar detector
Principles of Remote Controlled Cars
SDR Offensive Security
Request more information regarding SDR Training with HackRF. Visit tonex.com for course and workshop detail.
SDR Training with HackRF - Tonex Training
https://www.tonex.com/training-courses/sdr-training-with-hackrf-advanced-software-defined-radio-training/
Design and implementation of sdr based qpsk transceiver using fpgaTarik Kazaz
Software-defined radio (SDR) technology enables
implementation of wireless devices that support multiple air interfaces and modulation formats, which is very important
if consider the proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP
Builder Tool combined with Matlab/Simulink, Modelsim and
Quartus II design tools. As reconfigurable hardware platform
we used Altera DE2-115 development and education board with
AD/DA daughter card. Software and Hardware-in-the-loop (HIL)
simulation was conducted before hardware implementation and
verification of designed system. This method of design makes
implementation of SDR based modulators simpler ad faster.
Index Terms—SDR, FPGA, QPSK, DSP Builder, NCO, RRC
A Glimpse into Developing Software-Defined Radio by PythonAlbert Huang
Software-defined radio~(SDR) has been emerging for many years in
various fields, including military, commercial communication
systems, and scientific research, e.g. space exploration. GNU Radio
is an open source SDR framework written in Python. This talk will introduce from basic concept of software-defined radio and various
front-end hardware, and then illustrate how to use Python to develop
SDR.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
Introduction to Software Defined Radio (SDR)Pamela O'Shea
For less than $20 anyone can listen to the airwaves! In this workshop, we will look at what is around us in the airwaves, including frequency scanning, pagers, airplanes, remote controls and more. Please see associated worksheet for the exercises.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
SDR Training with HackRF - Tonex TrainingBryan Len
Length: 3 Days
SDR Training with HackRF, Advanced Software Defined Radio Training is a 3-day hands-on advanced SDR training course, Software-Defined Radio Development with GNU Radio utilizing HackRF One. The 3-day advanced SDR covers both hypothesis and application of SDR utilizing HackRF One.
.
SDR Training with HackRF. Advanced Software Defined Radio Training.
Participants will learn about:
Software Defined Radio and Digital Signal Processing
Theory and practice with hands-on SDR implementations using the Universal Software Radio Peripheral (USRP) SDR platforms
Necessary SDR signal processing building blocks, SDR application development using Python and C++ concepts required for GNU Radio development
How to apply HackRF and GNU Radio
How to use and apply GNU Radio Companion (GRC)
Security applications of SDR and RF Vulnerabilities
Course Agenda
Principles of Signal processing and applied RF
Overview of SDR
Overview of GNU Radio
Overview of GNU Radio software libraries
Overview of GNU Radio Companion (GRC)
Overview of Python and C++
Overview of Linux
Overview of Universal software radio peripherals
SDR and GNU Radio modules
Systems using HackRF One
Assessments of physical RF devices
How to Fingerprint on RF spectrum?
Hunting signals
Hardware Hacking 101
Reversing and Instrumentation (embedded RF systems)
IoT Hacking with SDR
Overview of Wi-Fi and Bluetooth
Open source SDR LTE software / FM Radio
Principles of Radar detector
Principles of Remote Controlled Cars
SDR Offensive Security
Request more information regarding SDR Training with HackRF. Visit tonex.com for course and workshop detail.
SDR Training with HackRF - Tonex Training
https://www.tonex.com/training-courses/sdr-training-with-hackrf-advanced-software-defined-radio-training/
Design and implementation of sdr based qpsk transceiver using fpgaTarik Kazaz
Software-defined radio (SDR) technology enables
implementation of wireless devices that support multiple air interfaces and modulation formats, which is very important
if consider the proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP
Builder Tool combined with Matlab/Simulink, Modelsim and
Quartus II design tools. As reconfigurable hardware platform
we used Altera DE2-115 development and education board with
AD/DA daughter card. Software and Hardware-in-the-loop (HIL)
simulation was conducted before hardware implementation and
verification of designed system. This method of design makes
implementation of SDR based modulators simpler ad faster.
Index Terms—SDR, FPGA, QPSK, DSP Builder, NCO, RRC
A Glimpse into Developing Software-Defined Radio by PythonAlbert Huang
Software-defined radio~(SDR) has been emerging for many years in
various fields, including military, commercial communication
systems, and scientific research, e.g. space exploration. GNU Radio
is an open source SDR framework written in Python. This talk will introduce from basic concept of software-defined radio and various
front-end hardware, and then illustrate how to use Python to develop
SDR.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
Introduction to Software Defined Radio (SDR)Pamela O'Shea
For less than $20 anyone can listen to the airwaves! In this workshop, we will look at what is around us in the airwaves, including frequency scanning, pagers, airplanes, remote controls and more. Please see associated worksheet for the exercises.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
Bringing SDR to the pentest community - BlackHat USA 2014jmichel.p
The large adoption of wireless devices goes further than WiFi (smartmeters, wearable devices, Internet of Things, etc.).
The developers of these new types of devices may not have a deep security background and it can lead to security and privacy issues when the solution is stressed.
However, to assess those types of devices, the only solution would be a dedicated hardware component with an appropriate radio interface for each one of them.
That is why we developed an easy-to-use wireless monitor/injector tool based on Software Defined Radio using GNU Radio and the well-known scapy framework.
In this talk, we will introduce this tool we developed for a wide range of wireless security assessments: the main goal of our tool is to provide effective penetration testing capabilities for security auditors with little to no knowledge of radio communications.
Open Software Platforms for Mobile Digital BroadcastingFrancois Lefebvre
Overview of CRC projects in digital radio software projects. Discussion of potential future projects. Presented in Gatineau to students and professors of Computer Science and Engineering Department of UQO
NXFEE Innovation is the Industry of Semiconductor IP Development, IP Designs, and services of developing solution to provide core products and application to customers with a wide range of solution that include custom ASIC/ FPGA/ DSP/ EMBEDDED System/ Wireless Technologies. Having lustrum of expertise and satisfied customers, NXFEE have the capability to deliver solution that is fully meshed with customer’s business requirement, meeting the highest standards.
NXFEE will Provide cost effective outsourcing services for secure and turn key product development in the areas of Bio-Medical/ Wireless/ Robotics/ VLSI/ DSP/ Embedded design & Development from conceptualization to production. Our sound technology and knowledge base have helped us to create products using emerging technology that include FPGA, VHDL, VERILOG HDL, SYSTEM VERILOG HDL, UVM, OVM, VVM, DSP, RTOS, DSP, Bluetooth, WI-FI, RF, CDMA, AXI, AHP, APB, and other related technologies in the area of industrial automation, telecommunications, consumer electronics and automotive applications.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
Developing a wireless sensor network (WSN) can be an awesome challenge. Achieving desired battery life, useful range from a low power RF transmitter and reliable embedded software operation are just a few of the challenges the wireless sensor network design faces. This presentation gives an overview of design considerations to help assure your WSN project is a success.
Software defined radio technology : ITB research activitiesDr.Joko Suryana
A.Introduction
1.From 1G to 5G
2.5G, from Device to Data Center
B.Programmable Networks
1.Software Defined Radio Technology
2.From Software-Defined Radio to Software-Defined Networking
3.Project Example : Princeton Univ : Software-Defined Cellular Core networks and New York Univ USA : SDN-controlled LTE using SDR
C.SDR Projects at LTRGM ITB
1.SDR for 5G Physical Layer Design
2.SDR for AESA Radar Receiver
3.SDR for Nanosatellite Ground Station
4.SDR for Communication and Identification for IFX
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2. Analog- and digital hw Signal processing- and operating sw Equipment System
Universal Software Defined Radio
Development Platform
Dr. Bertalan Eged*, Benjamin Babják**
*Sagax Communication Ltd., 1096 Budapest Haller u. 11-13. Hungary
**Budapesti University of Technology and Economics,
Department of Broadband Infocommunications, 1111 Budapest Goldmann Gy. tér 3. Hungary
www.sagax.hu
3. CONTENT
• Introduction (1)
• Introduction to Software Defined Radio technology (4)
– Basic principle − Architectural model
– SDR open structure − SCA
• SDR based radio devices (2)
– Functional elements − Implementation levels
• Platform components (9)
– Radio front-ends − Converters
– Signal processing
• Implementation samples (5)
– Signal generator − Radar application
– Monitoring receiver − Scanning receiver
• Summary (1)
(22)
www.sagax.hu 3
4. Introduction
• The interoperability of existing various radio systems is highly
limited
• Each newly added system specification is accompanied by
the demand of new radio devices, requiring application
specific hardware and software components
• Manifolding new radio equipment adds significant costs to
service and maintenance of these systems
www.sagax.hu 4
5. Introduction to Software Defined Radio
• To solve the previously mentioned and some other problems
the concept of SDR has been introduced
• The main principle: considerable part of the radio is realized
as software on programmable and reconfigurable hardware
– universal and reusable components
– easy upgradeable
– cost saving
• Software Defined Radio: enabling technology, a kind of
principle to build radio devices
www.sdrforum.org
www.sagax.hu 5
6. SDR architecture model
solution
Antenna RF Modem TRSEC ISEC Codung User I/O
Radio
specific specific specific specific specific specific specific
modules modules modules modules modules modules modules
infrastucture
Common Common Common Common Common Common Common
Radio
software software software software software software software
OS OS OS OS OS OS OS
Hardware
Firmware Firmware Firmware Firmware Firmware Firmware Firmware
platform
Antenna RF Modem TRANSEC INFOSEC Coding User I/O
hardware hardware hardware hardware hardware hardware hardware
www.sagax.hu 6
8. Software Communication Architecture
• The most important initiative to accomplish all the benefits of SDR for
military applications is the US Joint Tactical Radio System project
• One of the most important outcome of the JTRS program is SCA
www.sagax.hu 8
9. Radio device modelling
Traditional implementation
Baseband
RF IF Baseband BB
IF Down Demodulation
Down
Conversion and
Conversion
Processing
Software Defined Radio based implementation
Domain
Analog Digital
conversion
processing processing
A/D and D/A
RF Conversion DSP GUI
technology technology technology technology
www.sagax.hu 9
10. Implementation levels
Digital
signals
Digital
BB
Digital
IF
Digital
RF
www.sagax.hu 10
11. Experimental SDR platform
SCA compatible API
Radio Domain Signal
front-end conversionm processing
RF hardware PCI slot card Intel based PC
www.sagax.hu 11
12. Universal front-end structure
FEU FCU IF
RF FEU FCU
FEU FCU
FEU FCU OUT
IN
LO1 LO1 LO1
LO1 LO1 LO1 Embedded
LO1 LO1 LO1
LO3 LO2 LO1
controller
FEU FCU
RF FEU FCU IF
FEU FCU
FEU FCU
OUT IN
Dual-conversion for 20-520MHz
Triple-conversion for 20-3000MHz
www.sagax.hu 12
14. General digital back-end for converters
PROM FPGA
JTAG JTAG
Control
EEPROM RS-232
I2C serial control
interface
Different Config
MCU
front-end EEPROM
configurations
FPGA CFG Dedicated
data
Control connection
BUS FPGA
LOGIC and DSP
Front-end resource External
BUS TRG in/out
PCI
Sampling
HOST
CLK
Interface
for converters
LCLK OSC Local
33MHz CLK
CLK DRV
External X2/X4/X8 Sampling
CLK SCLK OSC
10MHz CLK PCI BUS connector
in/out
www.sagax.hu 14
15. Wide-band and narrow-band converters
Analog
RX
ADC FIFO FPGA
(Direct sampled)
preamp
WIDE-BAND
Full bandwidth
Analog
TX
DAC FIFO FPGA
driver
Analog
RX
ADC DDC FPGA
NARROW-BAND
preamp
(Channelized)
Reduced bandwidth
Analog
TX
DAC DUC FPGA
driver
www.sagax.hu 15
16. Wide-band converters
DCU-2xx DCU-3xx
(DCU-214) (DCU-304)
Max. 4 analog I/O channels Max. 4 analog I/O channels
1 clock I/O channel 1 clock I/O channel
80Msps/14bit sampling 80Msps/14bit sampling
500MHz bandwidth 500MHz bandwidth
40 bit front-end bus 80 bit front-end bus
Xilinx Spartan II FPGA Xilinx Virtex II FPGA
32bit/33MHz PCI interface 64bit/66MHz PCI interface
133Mbyte/sec signalling rate 528Mbyte/sec signalling rate
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17. Narrow-band converters
DRU-2xx DRU-3xx
(DRU-204) (DRU-304-FE16D1)
Max. 4 independent analog I/O channels Max. 16 independent analog I/O channels
1 clock I/O channel 1 clock I/O channel
80Msps/14bit sampling 80Msps/14bit sampling
500MHz bandwidth 500MHz bandwidth
Xilinx Spartan II FPGA Xilinx Virtex II FPGA
Max. 4 independent digital tuner Max. 16 independent digital tuner
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24. Samples: scanning receiver
•40MHz instantaneous
bandwidth
•1ms time resolution
•1KHz frequency
resolution
•1200/3200 pixel
display
•Full or partial
bandwidth processing
SRS-3000H receiver
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25. Summary
• In my presentation I introduced the basic principle of SDR
technology as the framework of future radio equipment and
system developments
• I defined a basic model for SDR radio devices based
consisting of three main elements: analogue front-end,
converter and digital processor
• I introduced the available components of an universal
development platform for radio solution developments
• Finally I presented some example application for the platform
components
• We would like to join the NATO RTO IST ET-33 or TG based
on the initiative developed by ET.
www.sagax.hu 25
Editor's Notes
In my first slide the content of my presentation is shown. After a short introduction of the topic, I would like to introduce Software Defined Radio technology concentrating mostly on to the main features using this technology. In the next four slides I will introduce a high level model of a radio communication device based on traditional and SDR technology. Following that I will introduce the main components of the SDR platform developed by our team , and I will show some example application s based o n this platform. Finally I will summarize may talk.
As an introduction for the topic let me summarize some basic characteristic of existing and evolving radio communication. As you may know the armed forces are equipped with a lot of communication devices including radio equipments and systems. E.g. in the US Army up to 25-30 radio-families are in use, which applied in a complex mission have to co-operate with Navy and Air force systems too. Assuming an operation carried out by international troops the number of systems and equipments becomes even larger, and the problem of interoperability becomes sorely serious. More complex missions require more complex communication systems. Each newly added system specification is accompanied by the demand of new radio devices, requiring application specific hardware and software components. Manifolding new radio equipment adds significant costs to service and maintenance of these systems.
Let us examine how Software Defined Radio Technology could help us solve the previously mentioned and other problems. The main principle of SDR is that considerable part of the radio is realized as software running on programmable and reconfigurable hardware devices. The hardware itself is referred to as the „ radio platform ”, while the different layers of software are called „ application framework ” . T his scheme provides universal and reusable components , which save costs and can be e as ily upgrade d . It is important to emphasize that although it is an enabling technology , SDR itself is not a n actual product . SDR is rather a kind of principle to build radio devices. SDR covers different kind of hardware and software components , which c an be stand alone products us ed to build SDR based solutions. The providers and users of this technology joined in an industrial alliance called SDR Forum.
The SDR architecture consists of functional hardware elements connected through open interfaces, and firmware procedures for adding software specific tasks to each of the functional areas. These parts of the model are jointly referred to as the „ hardware platform ” . The software necessary to operate is called the „ operating software ” (OS) running on the hardware based on its firmware. This operating environment provides a common interface for the upper layer. With the common interface we have a radio infrastructure, which is ready to run application specific software modules completing the whole solution.
The common software API layer shown in the current slide is standardized with common functions having open and published interfaces.
Currently the accepted common interface for military aplicatons is the Software Communication Architecture developed by t h e Joint Tactical Radio System (JTRS) project. „ The Joint Tactical Radio System is a DoD initiative. JTRS is designed to provide a flexible new approach to meet diverse warfighter communication needs through software programmable radio technology. ” Qouted from from http:// jtrs. army. mil/ The key result of the JTRS Program is the specification of the Software Communications Architecture (SCA) , which serves as standard for (nearly) all military SDRs . It is a framework of an open, distributed, object oriented architecture , and it separates the application (waveform functionality) from the Operating Environment . SCA defines common interfaces for the behavior and the installation of software components . Furthermore it defines common services & Application Programming Interface to support the portability of devices and applications .
Traditionally a radio has been considered to be the „box” connecting to the antenna and everything behind that. However many system designs are segmented into separate subsystems: RF to IF down-conversion, baseband conversion and demodulation, man-machine interface elements. The higher level functional model of the SDR radio platform consists of three main elements: the analogue front-end, the domain conversion and the digital back-end. The analogue front-end is responsible for frequency conversion between the transmitted signal frequency and the digitally processable frequency and bandwidth. The front-end is based on analogue amplifiers, mixers, filters and frequency sources. The domain converter responsible for the conversion between the analogue and digital domain are based on high-speed, wideband A/D and D/A converters. Properties of the domain converters highly influence the functionality of soft radio platforms. The digital back-end contains FPGA based configurable and/or DSP based programmable computing resources to run the software components.
S oftware defined radio technology is based on the principle , that conversion between analog and digital domain s should take place as close to the antenna as possible , providing the potential of maintain ing signals in digital domain. Based on the domain conversion s place the implementation level of SDR technology can be classified from digital signal handling t h rough digital baseband , digital IF or even digital RF implementation. Th is is the reason, why the converters bandwidth is so important . It can determine the whole solution s implementation level.
In this slide components of the SDR platform are shown . We have ready to use solutions for the analogue radio front-end ( in the form of traditional radio frequency hardware ) and for the wide-band and narrow-band domain conver sion ( in the form of PC slot card s with PCI interface ). Signal processing is done with an off-the-shelf Intel based PC , which also serves as control platform. Let u s examine the components one by one .
The radio front-ends are based on a universal structure build around 6 basic blocks. The frequency conversion between VHF/UHF frequency band and any standard intermediate frequency (IF) is realized by a dual-conversion structure , which requires two frequency synthesizers as local sources , and conversion hardware containing frequency mixers, filters, amplifiers. The number of basic building blocks depends on the application , which could be a receiver, transmitter or transceiver, single- or multi-channel and in case of multi - channel independent or phase array. The freqency and gain control elements could be controlled by the internal embedded controller , or could be controlled directly by the application or digital processor if the high-speed processing speed is required. In the case of VHF/UHF application where frequency coverage up to 3GHz is required one additional frequency extension unit and one more local oscillator is used. The number of units is determined by the application requirements.
In this slide t wo RF front-ends are shown . T he first front-end has 1 independent channel, while the second is capable of processing 4 RF channels simultaneously. Other parameters are fairly similar.
The parts of the converter product family are based on the same base structure. The cards contain a 5V tolerant, master mode, DMA capable PCI host-interface chip, which is connected to the FPGA reserved for on-board data pre-processing and glue-logic implementation. T he required logic functionality is implemented i n the FPGA to control the front-end functionality and manage the data flow. The FPGA can be configured directly through its JTAG port or it can boot from the programmed configuration EEPROM . Users also have the possibility to download firmware trough the PCI bus providing on the field pre-processor reprogramm ability . The cards also contain a micro controller unit. This MCU has an I2C connected external EEPROM and a n external serial port connection. The MCU is routed to the control bus and to the FPGA s configuration connection. Through its connections the MCU is able to configure the FPGA provided a configuration EEPROM is present , and is able to control the front-end if PCI control is not applicable. The data flow from/to the front-end can be implemented through the PCI bus or it is also possible to route the data flow to the dedicated ports of the FPGA. This option can be used to implement direct high-speed data connection directly to a DSP processor. In this case the PCI interface is used for control only, in addition the front-end may also be controlled by the MCU. The cards contain a clock generation block with internal and external clocking options. The clock buffer is able to multiply the clock by 2 to 8 depending on the configuration. The sampling clock is routed to the dedicated global clock input of the FPGA. The communication between the FPGA and the PCI chip is clocked from a separate local clock source. Sampling may also be triggerd external y .
Currently we offer two basic type of converter cards for domain conversion. One of them is wide-band, meaning that digitised samples are stored in a high-speed FIFO memory. Samples can be accessed by the digital pre-processor implemented in the FPGA for the purpose of reading or writing in case of transmit or receive operation. This way the converter hardware itself does not limit the data bandwidth. Generally it is limited by the throughput of the digital interface between converter and digital processor, e.g. the PCI bus. Provided we have enough resources it is possible to implement bandwidth reduction processing optionally in the configurable on-board pre-processor FPGA. Second type of the converter family is a narrow-band or channelised converter. In this case we have built in dedicated channel selector hardware components between the converters and the pre-processor. The bandwidth reduction is realised by the digital down-converter (DDC) and the digital up-converter (DUC) for the receiver and transmitter operations respectively. The digital tuners are implemented in ASIC chips in order to optimise the workload of the processing elements.
In this slide t wo wide-band converters are shown . T he first converter is from the DCU-2xx product family, it has 4 channels and a 32bit PCI interface. Converter products in the DCU-3xx family can also process 4 channels, and are connected to the host system via a 64bit PCI interface.
In this slide t wo narrow-band converters are shown . T he first converter is from the DRU-2xx product family, it has 4 channels and a 32bit PCI interface. Converter products in the DRU-3xx family may process up to 16 channels, and are connected to the host system via a 64bit PCI interface.
Digital processing may be done with dedicated digital signal processors (DSP) or general propose processors. The DSP elements generally provide more and dedicated bandwidth for data transfer. They provide more processing power mainly by their dedicated hardware multipliers and other processing oriented architectural elements. However, general processors recently show extremely fast growing thanks to the high volume production and market demands. It seems that data bandwidth between the peripheral components, memory and processor has significantly increased as they are routed together by one chip with dedicated data connections. The architecture and clock speed of general processors provide enough processing power for implementing signal processing algorithms without dedicated processing elements like multipliers. On the other hand ready to use operating systems (OS) or even real-time operating systems (RTOS) are avaliable for these processors with well documented and well supported software development tools. So we have decided to use latest Intel based processors as signal processing element instead of dedicated DSPs.
For processing purposes we have developed some basic software for the platform including waveform generation and signal analysis as represented by the pictures on the slides. As described at the principle of SDR technology, the success of the SDR is based on the published and open interface of the components. Our software is based on an application programming interface (API) defined by ourselves. Software modules and application developed by our team could be used as starting point to develop any other solution based on our hardware elements.
In the following slides I will show some practical example implementations based on our SDR technology. The first example is a signal generator which can be used to generate modulated carriers from 1MHz up to 2500MHz with 1Hz resolution. The unique feature of the this equipment is that it contains lot of modulation formats and sources called waveforms in the l a nguage of SDR technology. Simple analog modulations like AM, FM, SSB, digital modulations like ASK, PSK, FSK and its variant s , complex modulations up to 256 QAM and some other techniques like DSSS, FHSS, FDM, TDM could be used. T his is one good example for complex waveform generation.
The next example also a kind of waveform generation, but in this example we use the SDR technology and platform components to generate radar signals with sub-impulse modulation. As you may see from the screen shot of the signal processor the application is used for generating different kind of sub-pulse modulated BPSK bursts with some code content, linear and non-linear FM modulation. The signal processor of the receiver contains the matched filter based pulse compressor for these signals. This experimental radar system was used by in the trial of SET-078 TG-46 too.
This picture shows the PP indicator program of the experimental radar system.
The two last examples show other type of usage of our SDR technology. One of them is a monitoring receiver where the narrow-band converter is used for digitising the incoming 40MHz bandwidth limited from 1.5MHz to 32MHz HF band and form a direct digital received (DDR) for that band. The monitoring receiver provides up to 300KHz instantaneous bandwidth for digitally implemented demodulators.
The last examples illustrates the usage of the wide-band converter to build a fast scanning panorama receiver. In that case the spectrum estimation is done by digital processing, and using the Windows-based graphical interface it is possible to search a wide frequency range for signals. This kind of receiver can be integrated into a bigger spectrum management system.
In my presentation I introduced the basic principles of the SDR, the technology that is the framework of future radio devices and system development. I defined a basic model of radio devices based on SDR. Following that I introduced a universal development hardware platform and its components. Finally I presented some example applications based on the previously mentioned hardware platform.