This document presents FraCa cost-controlled 2kW inverter as an answer to the specifications of Google and IEEE Little Box Challenge.

1. LF switches
COLD
AIR
HOT
AIR
HF + ARCP switches
 8W
 4W
 4W
 4W
 4W
• Restricted height  selection of low profile SMD components using through PCB cooling (with thermal vias)
• Dual HF legs  use of symmetry to create a cooling duct acting as a double-side thermal system
• Split inductors are preferred to a single coupled inductor to benefit from the cooling concept and increase losses density
• All dimensions must be wisely chosen to align components.
1. PCB thickness + baseplate + D²Pak height  max value for Hind ; E32 Planar cores perfectly match the constraints
2. Thermal performances  Hfin ; Choice of an adequate form factor (H/D) for capacitors with high volumetric energy
2) 3D mechanical assembly of the converter
3) Thermal management approach
Conclusions
Motivated by reaching the target of the Little Box Challenge with a low-cost approach, a technical solution achieving a power
density around 4.3kW/l (71W/inch3) with a CEC efficiency higher than 97% and a 98.1% peak efficiency was presented. With a
second revision, the converter volume could be reasonably reduced to 370cm3 (5.4kW/l - 88W/in3) without affecting the cost but
this value is definitely capped by the DC link capacitors (1,7mF for PF=0,7).
CAPS
D²PAK
D²PAK
Output inductor 5mm
HIND
CAPACITORS
HFIN
CAPACITORS
PCB Insulating foil (TIM)Baseplate
Coupling PCB
D²PAK
D²PAK
INDUCTOR
INDUCTORD²PAKD²PAK
- Power supplies,
DSP board and DC
capacitors
- Fan and LF leg
cooling system
LF switches HF board n°1
HF board n°2
PCB Insulating foil (TIM)Baseplate
Duct equipped with fins
(not represented here)
COLD
AIR
HOT
AIR
Min 20mm
0 10 20 30
0.5
1
1.5
2
Fins H=12mm
Fins H=8mm
Fins H=4mm
Cooling air thermal resistance (°C/W)
Intermediate fins
0 10 20 30
0
1
2
3
4
5
Fins H=12mm
Fins H=8mm
Fins H=4mm
Thermal resistance (°C/W)
Intermediate fins
0 10 20 30
0
1
2
3
Fins H=12mm
Fins H=8mm
Fins H=4mm
Air flow (m3/h)
Intermediate fins
Air flow (m3/h) Thermal resistance (°C/W) Air thermal resistance (°C/W)
Intermediate fins Intermediate fins Intermediate fins
CM filter
115mm
138mm28mm
ARCP chokes
Distributed
DC link
Distributed
DC link
Power
Supply
LF leg
HF board n°1 DM filter
DM
choke
Meas. units
Distributed
DC link
Estimated losses assuming Tj = 125°C : 24W
(ARCP chokes, DC capacitors are cooled via the metallic enclosure)
Fan Selection
(flow rate ensuring Tair_out < 60°C)
Optimized heatsink geometry
(Depth is set to 50mm according to the PCB area needed for active devices)
Selected model : 2 x Alpha-Novatec UB60-7B (0.4mm thick, 4mm high fins)
Model
H/L/W
(mm)
Min/max
flow (m3/h)
BFB03512
HHA
7.7/24/35 2.9/3.6
24mm
Nint=11
HLF leg dedicated cooler with lowP
(Home made device : copper drains equipped with fins)
Cooling of the DM inductors
IN
OUT IN
Experimental results : HS_HF = 3°C/W (per side), HS_LF = 3°C/W, Air = 1,1°C/W and HS_ind=3,7°C/W
4) Prototype performances overview
88
90
92
94
96
98
100
0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Efficiency(%)
Ouput power (W)
Measurements
Calculation
Objective
• Converter volume  425cm3  77W/in3 (460cm3 w/ enclosure  71W/in3)
• Efficiency : 98,1% peak - 97,2% CEC. Optimized control laws of the ARCP circuitry are still possible to improve CEC efficiency
• Overall cost : 270€ assuming a MOQ=10kunits
+0,5% CEC
A cost-controlled, 4.3kW/l 1-ϕ Inverter with a 97.2% CEC efficiency
Guillaume Lefevre, Nicolas Degrenne , Jeffrey Ewanchuk, Yoan Lefevre
FraCa Team, Rennes, FRANCE
Specifications Approach
1. Active devices : avoid using the latest generation of SiC or GaN devices due to
cost and EMI requirements (high dV/dt) soft-switched SJ MOSFETs
2. DC Capacitors : conventional design using a wise selection of market sampling
3. AC Inductors : low Evol multilevel PWM + interleaving techniques
4. Cooling system : spread losses and optimized combination of fan and heatsink
5. EMI filter : prefer soft-switching and keep the first CM harmonic below 150kHz
6. Layout : Standard techniques with a minimum number of layers to reduce cost
Abstract : The motivation of this document is to describe the integration aspects of the independent Franco-Canadian Team
FraCa's entry into the Google Little box Challenge, the team being self-funded by persons working outside their current
positions. The cost-motivated design approach is presented, and the selected converter topology namely FraCa topology is
described in terms of its passive and active component contributions to meet the objective volumetric power density.
Experimental results confirm a 97.2% CEC and 98.1% peak efficiency, meeting both the power density and efficiency targets
Rated power 2kVA, PF≥0,7, leading-lagging
Power Density > 50W/in3 (3kW/l)
Output voltage 240Vrms ±12V@60Hz
Input voltage 450V + 10Ω in series
Input ripple 20% (I) and 3% (V) pk-pk
Maximum THD 5% on both Iac and Vac
Maximum Temp. 60°C with TAMB=30°C
EMC constraints - FCC Part 15 B EMI rules
- Ileak<50mA with 120nF of CM
capacitances between terminals
1) Overview of the FraCa topology operating under soft-switching conditions
Principles
• Combination of a LF-T-type leg and HF soft-switched legs
• Two interleaved HF legs were implemented  generation
of 5-level waveforms @ 2fsw
• T-type leg operating at the grid frequency :
1. no switching losses even with reduced dV/dt to
comply with the CM constraints
2. LV MOSFETS are implemented for the mid. switch
3. beneficial use of the capacitive mid. point to
implement a simple ARCP circuitry
4. easy to scale for higher power levels
• Body diodes related issues are tackled  full advantage of
the latest generation of the SuperJunction MOSFET
Typical waveforms@Pn
Voltage across the load and the low-frequency mid point
2ms
0,5 IL1
0,5 (IL1+ IL2)
0,5 Vload
VLF
VDS
VGS
IARCP
Increasing I
100ns
Max ISW
TZVS
Current flowing in L1 and (L1+L2) Typical turn-on transitions with the ARCP circuitry
LF-T-type leg HF leg n°1 HF leg n°2
ARCP circuit
L1
L2
Carcp
Larcp
VDCp
VDCn
Load
Special thanks to all those who contributed and helped us in this contest (Free samples, testing facilities,
measurement devices…) : ENS Rennes Ker Lann, G2Elab, CEFEM Industries, ST Microelectronics
0,0
0,2
0,4
0,6
0,8
1,0
1,2
1,4
1,6
1,8
1 2 3 4 5 6
Energydensity[J/cm3]
Form factor H/D
10
100
1000
10000
100000
0,01 0,1 1 10 100 1000
FOM((mm3*€)/J²)
Energy (J)
Electrolytic
Ceramic
Film
0
200
400
600
800
1000
1200
1400
1600
1800
0 100 200 300
FOM=Cost*OnResistance(€*mΩ)
Rds_On@25°C (mΩ)
HEMT GaN
MOS_JFET SiC
SJ MOSFET
SJ MOS w/ ARCP