EE315a_design_project

> Tamer Riad, EE315A Design Project, Spring 2010 < 1
Abstract—A low power high performance CMOS OTA for use
within a fifth order elliptic switched capacitor low pass filter is
described. The OTA is optimized for minimum power
consumption where its core consumes 0.973mA from a 1.8V
power supply. As predicted from simulations, the OTA is
designed to guarantee its output to settle within a dynamic error
of 0.1%. Full sampling is used at a clock rate fs equal to 103.68
MHz. The maximum allowed voltage at the OTA output is equal
to 1.002V whereas the maximum input signal level is limited to
926 mV. Under these conditions, the OTA total integrated noise is
equal to -67.45 dB yielding 54.4 dB of dynamic range at the filter
output. The third order harmonic distortion is equal to -81 dB
when the filter input is fed with a 3fs/128 sinusoidal tone running
at an amplitude equal to the maximum allowed input signal level.
The design was implemented based on a 0.18µm CMOS
technology.
Index Terms—Folded cascode, Operational transconductance
amplifier, OTA, switched capacitor filter.
I. INTRODUCTION
HE continuous down-scaling in CMOS technologies has
enabled astonishing high levels of integration that keep on
growing over the years. During the past decade, the System-
on-Chip concept [1] has been proven a reality enabling a
variety of Silicon applications to coexist on the same chip.
This evolution comes with the caveat of increased complexity
for design and verification. In particular, power consumption
has become one of the major concerns in most applications
and significant effort is typically dedicated to ensure it is kept
at the minimum possible level.
Manuscript received October 9, 2001. (Write the date on which you
submitted your paper for review.) This work was supported in part by the U.S.
Department of Commerce under Grant BS123456 (sponsor and financial
support acknowledgment goes here). Paper titles should be written in
uppercase and lowercase letters, not all uppercase. Avoid writing long
formulas with subscripts in the title; short formulas that identify the elements
are fine (e.g., "Nd–Fe–B"). Do not write “(Invited)” in the title. Full names of
authors are preferred in the author field, but are not required. Put a space
between authors’ initials.
F. A. Author is with the National Institute of Standards and Technology,
Boulder, CO 80305 USA (corresponding author to provide phone: 303-555-
5555; fax: 303-555-5555; e-mail: author@ boulder.nist.gov).
S. B. Author, Jr., was with Rice University, Houston, TX 77005 USA. He
is now with the Department of Physics, Colorado State University, Fort
Collins, CO 80523 USA (e-mail: author@lamar.colostate.edu).
T. C. Author is with the Electrical Engineering Department, University of
Colorado, Boulder, CO 80309 USA, on leave from the National Research
Institute for Metals, Tsukuba, Japan (e-mail: author@nrim.go.jp).
Power consumption minimization is usually a complicated
process that necessitates a clear understanding of the design
problem at hand. In order to make the right decisions, the
major tradeoffs need to be identified together with their
respective knobs. While this task is not always straightforward,
it helps the designer make adequate compromises in order to
reconcile the different tradeoffs towards the optimum desired
region.
In this paper, we investigate the design analysis for a high
performance CMOS operational transconductance amplifier
(OTA). The OTA is intended to be used within a specific fifth
order elliptic switched capacitor low pass filter. While the
filter design is completely established in [2] based on a
0.35µm technology, our role is to investigate the minimum
required power consumption when migrating the design to a
given smaller process node at 0.18µm. Maintaining high level
specs that guarantee successful operation for the filter is also
taken into account.
In Section II, the high level filter architecture is briefly
reviewed. The OTA architecture is established in Section III
where the different design equations and knobs are identified
and related to specifications of relevance. Next, Section IV
introduces an approximate analysis to identify the critical OTA
suffering the toughest settling requirements. A thorough design
procedure and optimization follows in Section V. Finally,
simulation testbenches and results are covered in Section VI
before closing with the conclusion in Section VII.
II. FILTER ARCHITECTURE
The filter in question is a low pass, fifth order elliptic
switched capacitor ladder filter. Fig.1 shows the overall filter
architecture where its implementation details are described in
[2]. Five fully differential operational transconductance
amplifiers (OTA’s) sit at the filter core while driving switched
and non-switched capacitors as dictated by the
implementation. In addition, ideal samplers are used at both
the input and output of the filter for subsequent processing.
While the implementation in [2] uses double-sampling to
reduce the clock rate, full sampling is deployed in our case.
The latter choice is possible given the smaller 0.18µm CMOS
technology at hand allowing to relax the upper limit on the
maximum achievable clock rate. It follows that the sampling
frequency for this design is assumed to run at 103.68 MHz. In
A Low Power High-Frequency CMOS OTA for
a 5th
Order Elliptic Switched-Capacitor Filter
Tamer Riad, Member, IEEE
T

the next subsequent sections, we limit our focus to the design
of the OTA block while accounting for its impact on the
overall response and performance of the filter.
III. OTA ARCHITECTURE AND ANALYSIS
The standard folded cascode configuration is chosen to be
studied for the implementation of the OTA. In particular, the
gm generator at the input comprises of an NMOS type
differential pair as depicted in Fig. 2. The OTA is biased such
that the current in the input branch Id1 is slightly less than Id2
flowing through the cascoded loads to avoid asymmetric
slewing as will be discussed later in this section.
Based on first order considerations, the NMOS type chosen
for the input pair can be justified to optimize the tradeoff
between speed and power. Assuming the settling time without
slewing falls roughly at Ts/4, this will yield a unity cross over
frequency fc near 456MHz for a 0.1% dynamic settling error.
In this case, the device cutoff frequency fT ≈ 15 fc ≈ 7GHz for
80° phase margin. Technology data show that, at this cutoff
frequency, for a standard device (10µm/0.18µm), the ratios
between (gm/Id)N and (gm/Id)P is roughly equal to 1.8, hence
dictating a significant power savings advantage provided by
the NMOS type. On the other hand, the typical PMOS
advantage of quieter noise contribution is considered less
beneficial since γp/ γn ≈ 0.8 in our technology.
A. DC Analysis
High order elliptic type filters are known to exhibit high-Q
poles that can quickly distort the overall filter response once
the finite gain and bandwidth of the integrator are included. To
derive a rough estimate for the minimum required gain, the s-
domain filter transfer function is implemented in Matlab based
on the filter original specs including order, frequency corner,
passband ripple and stopband attenuation. This step is also
equivalent to performing an inverse bilinear transform for the
filter transfer function in the z-domain. The corresponding
poles are then extracted and the larger Q is found equal to 5.86
at a pole frequency fp = 20.84 MHz. In this case, the DC finite
gain of the OTA is expected to degrade the ideal quality
factor of the pole ( ) using
, (1)
where is the actual resultant quality factor due to finite
. Next, a maximum passband attenuation of 1dB requires
is to be larger than 40.65dB. This result is also verified
Fig. 1. Fifth order elliptic switched-capacitor ladder low pass filter as implemented in [2].
Fig. 2. OTA folded cascade configuration, biasing not fully shown.

more accurately using Spectre-PAC simulation for the entire
filter. In this case, infinite bandwidth amplifiers are used and
their finite gain is swept while attenuation within a passband of
18MHz is monitored not to exceed 1dB as dictated by the
spec. The minimum gain required in this case is slightly larger
and equals 40.97dB.
Next, the DC gain of the folded cascode OTA is derived. In
the analysis, due to the large DC impedance seen at the drain
of M4 ( )544~ oom rrg , M2 is not assumed as a unity current
buffer and a current splitting factor








+
=
225431
31
/||
||
4 omoomoo
oo
rgrrgrr
rr is taken into account. In this
case, the overall half circuit DC gain can be expressed as












++











++
=
3
1
12
54
31
13
254
1
1
5
1
111
1
o
o
o
o
m
m
m
m
o
r
r
ra
ra
ag
ag
aaa
a
g
g
a
a
, (2)
where ai is the intrinsic gain for device Mi.
The above expression is rather complicated to determine the
individual intrinsic gains for different devices. Instead, we
look at the intrinsic gain versus gm/Id charts for both NMOS
and PMOS devices. For a 0.18µm device, the NMOS gain is
measured to be around 35 as opposed to 30 for a PMOS within
a [10, 15] range of gm/Id. Assuming all transistors share the
minimum length, a0 is estimated to equal 46.26dB using Eq. 2.
This result is found acceptable since it exceeds the minimum
required gain by more than two times. One may also conclude
that all OTA transistors can probably have their length sized at
the minimum feature size provided by the technology without
violating the minimum required gain. The latter observation is
attractive as it lies at an optimum when considering the
tradeoff between power efficiency and speed for an arbitrary
device.
B. AC Analysis
As seen within the filter architecture, the OTA is wrapped
within a capacitive feedback network. In this case, one can
show that the unity cross over frequency is roughly given by
totLmc Cg ,1 /βω ≅ . (3)
Table I below summarizes the definition for the different
symbols defined in Eq. 3.
TABLE I
SUMMARY FOR SYMBOLS DEFINITION
Symbol Definition
β
11 gdggsf
f
CCCC
C
+++
fC Feedback capacitance
sC Source capacitance
totLC , ( ) foL CCC β−++ 1
oC 42 dddd CC +
Note that the β factor assumes neutralization capacitors are
used around the input differential pair to mitigate Cgd Miller
amplification.
In addition, a non-dominant pole is introduced at the source
of the cascode device M2 and can be expressed as
xmx Cg /2=ω , (4)
where 321 ddssddx CCCC ++= . In this case, the phase
margin can be calculated using
( )cxPM ωω /tan 1−
≅ , (5)
provided that xT ωω >2 .
C. Noise Analysis
To estimate the total integrated voltage noise at the OTA
output, equivalent drain noise current sources
2
di are used in a
half circuit representation. KCL is applied at the source and
drain of M2 where all noise contributions can be lumped into
the following expression
( ) ( )







+
+
+
+++=
ycm
m
ycym
cm
mn
mp
xmn
cmp
n
totL
o
g
g
g
g
g
g
g
g
C
kT
v
ωωωωω
ω
g
g
ωg
ωg
g
β /1/1
1
1
5
1
4
1
3
1
2
,
2
,(6)
where ymy Cg /4=ω , and 54 ssddy CCC += .
Eq. 6 conforms with the familiar result for the OTA noise to
be inversely proportional to the feedback factor β and the total
capacitance seen by the OTA output. Additional terms exhibit
dependencies on ratios between device transconductances as
well as xc ωω / and yc ωω / . The latter two ratios are
expected to be small leading one to conclude that gm ratios
13 / mm gg and 15 / mm gg should be minimized as much as
possible.
D. Settling Analysis
Given the switched nature of the signal propagation, it
becomes important to quantify the OTA performance in
response to step-like excitation signals. For small steps, the
settling time can be shown to be approximately equal to








+
−−≅ )1(ln
Lf
f
dsettle
CC
C
T βet , (7)
where cωτ /1= and dε is the dynamic settling error.
For a relatively large step, the OTA is expected to enter a
non-linear regime also known as slewing for a time period that
can be approximated by
SR
I
g
V
t d
m
xstep
slew
.
8.2
1
1
β






−
= , (8)
where xstepV is the resultant step at the OTA input and SR is
the slew rate given by totLd CI ,12 . It follows that as a general
guideline the overall settling time can be estimated using

SR
I
g
V
V
V
T d
m
xstep
linod
finalod
dsettle
.
8.2
ln 1
1
,
,
β
et






−
+







−= , (9)
where SRtVV slewfinalodlinod −= ,, .
It is worth mentioning here that Id2 and Id1 are designed such
that Id2 is slightly larger than Id1. Fig. 3 as shown below,
depicts the current paths during slewing assuming a large
positive step at the input of M1’. In this case, M1 is off
and totLC , on the Vop branch is charged positively with Id1. On
the other hand, M1’ is forced by the tail current source to
conduct 2Id1. It follows that the current entering the source of
M2’ is now Id2 - Id1 and totLC , on the Vom is charged negatively
with Id1.
While the above analysis holds when Id1 = Id2, it was found
through transient simulations that it becomes difficult to match
exact equal amounts of currents between the two cascode
branches during the nonlinear slewing period. This was
observed to adversely affect the slewing symmetry between the
output branches leading to undesired anomalies to appear at
the differential output during settling. As a design safety
precaution, Id2 will be kept larger than Id1 by 20% during the
design process.
IV. CRITICAL OTA FOR SETTLING
Based on the filter architecture presented earlier in Fig. 1, we
run a high-level first order analysis to identify the critical OTA
suffering the worst settling conditions. To do this, a capacitive
network wrapped around each OTA is derived. This step is
approximate since it assumes each OTA can be analyzed
individually while multiple input excitations are lumped to a
single source. Despite the simplicity of the assumption, it is
still considered as a good representation capturing the
fundamental settling behavior for each OTA as a function of
the capacitive loading imposed by the filter architecture.
Based on the above approach, the middle OTA as seen in
Fig. 1 can be identified as the bottleneck that may limit the
overall settling performance if not designed carefully. In this
case, during phase 2 operation, the equivalent feedback
capacitance is measured to be equal to 9C . At the output, the
capacitive loading is estimated to be equal to the parallel
combination of ,5C 10C , 22C and 23C . Similarly, the
equivalent input capacitance is calculated as the summation of
7C , 8C , 24C and 21C . Based on these values, an effective
loading capacitance ( ) fLeffL CCC β−+= 1, is calculated
using the corresponding β factor. It follows that
the effLC ,/β ratio becomes a good relative indication for the
expected settling behavior of the OTAs where
effLc
settle
C
T
,
11
βω
∝∝ . In this case, the middle OTA is
found to have the smallest effLC ,/β ratio. Consequently, we
will focus our efforts henceforward to the design of this
particular OTA.
V. OTA CIRCUIT DESIGN
A. Initial Guess Analysis
At the opening stage of the design process, an initial guess
for the maximum achievable output swing can be obtained by
ensuring the devices in the cascode branch remain in
saturation. Assuming a minimum compound margin of 3Vov
for devices M4(M4’) and M5(M5’), the minimum output
voltage becomes ~ 3(2/gm/Id) = 400mV where gm/Id is pushed
to its maximum1
≈15 to promote power efficiency. Similarly,
the maximum output voltage can be calculated as (1.8-
2(2/gm/Id)x1.83-(2/gm/Id)) ~ 1.18V where the 1.83 factor
accounts for M3(M3’) sustaining Id1+Id2 = 1.83Id2. Assuming a
common mode voltage of 900mV, the maximum differential
output swing is concluded to be governed by the PMOS
cascodes ≈ 4(1.18-0.9) ≈1.12V. Furthermore, if the minimum
DR for the overall filter is targeted to be larger than 54dB, the
noise level should reside at -59dB while including a 6dB
margin of noise contribution by the OTA. A filter top level
simulation using ideal amplifiers shows that the latter noise
level is achievable when all capacitors are scaled by a common
factor k ≈ 0.05. This initial estimation is found useful as it
pushes the entire design to jump quickly within the final
optimization space. Moreover, k is chosen as a primary knob
that directly controls the tradeoff between power consumption
and noise level.
Next, we choose the second design knob to be Cgg1. This
choice is attractive in the sense that it reveals values for the
capacitive network around the OTA within a good level of
1
In our technology, the noise device SPICE models were viewed optimistic
for gm/Id > 15.
Fig. 3 Current paths during slewing in a folded cascode OTA.

accuracy (See Table I). It follows that one can now calculate
the required cω using
















+
−−=
Lf
f
d
s
c
CC
C
T
βε
α
ω 1ln
2/
1
, (10)
where α is the ratio between the settling time for small signal
excitations and half the sampling period sT . A common
practice choice is applied whereα is set to 0.5 predicting the
OTA will slew for half of the time. Consequently, we obtain
gm1 ≈ ωcβ/CL,tot and fT1 = gm1/Cgg1. The latter values can then be
used to obtain the resultant gm1/Id1 using the fT versus gm/Id
design charts at L1=0.18µm. To minimize the power
consumption by M1(M1’), gm1/Id1 is targeted at its maximum
(~15) and the previous steps are iterated to arrive at a suitable
value for Cgg1 satisfying the latter condition. Fig 4. portrays the
behaviors of gm1/Id1 as well as Id1 versus Cgg1 where gm1 is fixed
by the settling requirement set earlier by 5.0=α . The
conduct embodies the tradeoff between device speed and
power consumption: larger Cgg1 will dictate a smaller fT while
boosting the power efficiency indicated by larger values of
gm1/Id1 (and smaller values for Id1). This step can be concluded
by choosing Cgg1 ≈ 63.5fF dictating gm1 = 5.5mS, Id1= 366µA
and 4682 ×≅ πωc MHz.
Subsequently, the phase margin condition (PM = 75°) can
be used to determine a rough estimate for the location of the
non-dominant pole xω relative to cω . In addition,
assuming xT ωω 32 ≈ , gm2/Id2 is obtained to be equal to 13.5
and is reiterated later on to approach ~ 15.
In the following step, the remaining transconductances for
devices M3/4/5 can be simply computed knowing their bias
current (Id2 = 1.2Id1) while setting their corresponding gmi/Id2
equal to 15 to shoot for the maximum possible swing. It
follows that gm3/gm1 = 2.2, gm4/gm1 = gm5/gm1 = 1.2. This
strategy is beneficial in the sense that once gm1/Id1 is
maximized, it will directly set the same maximum value for
devices M3/4/5.
Finally, having determined all devices currents and gm’s,
one can simply use the current density design charts (Id /W
versus gm/Id) to properly size all transistor widths. Moreover,
technology database lookup functions are used to estimate all
devices intrinsic and extrinsic capacitances. This will help
evaluate some design parameters more accurately. For
instance, CL,tot is reevaluated while including Co to result in a
more accurate estimation for 3552 ×= πωc MHz. The latter
shift will cause an increase in the actual resultant phase margin
by about 5°. To minimize this shift, several iterations were
performed where the minimum resultant PM was impossible to
decrease below 79° if the maximum gm/Id condition is
preserved. This behavior is attributed to the fact that
parameters cω , xω and 2Tω are all related and tend to move
together. At this point, relaxing the PM condition above 75°
was sacrificed for maximum power efficiency. Consequently,
gm2/Id2 is restored from 13.5 to 15 by setting xT ωω 5.32 ≈
yielding a PM of 79.1°. Other design parameters were kept the
same as discussed before.
Under these conditions, the power consumed by folded
cascode can be estimated to be 2.89mW. Table II below
summarizes the major device parameters as concluded from
the previous discussion.
TABLE II
SUMMARY FOR INITIAL GUESS DEVICE PARAMETERS
Parameter M1 M2 M3 M4 M5
gm (mS) 5.5 6.6 12.1 6.6 6.6
gm/Id 15.1 15.1 15.1 15.1 15.1
W(µm) 31.48 115.15 210.16 37.78 37.78
L (µm) 0.18 0.18 0.18 0.18 0.18
B. Biasing Network Design
The folded cascode OTA requires proper biasing for the pair
of cascoded active loads in addition to the tail current source.
To achieve this, magic batteries were considered where single
mirroring configuration was investigated at first (See Fig. 5
below). This attempt was quickly abandoned due to the limited
voltage headroom caused by the stack of four devices. This
conclusion is justified considering the threshold voltage Vt to
be around 550mV while taking one Vov of margin (f=2) above
the minimum biasing point condition to keep all devices
reasonably in saturation. In this case, Vx ≈ 1.63V thus pinching
any practical current source device to the supply rail.
Instead, double mirroring configuration is used as shown in
Fig. 6 below. A reference current equal to Id2/R is assumed
where R is a common mirroring ratio between the biasing
Fig. 4 Bias current Id1 and gm/Id1 versus Cgg1.

network and the OTA branches. In this case, the biasing
voltages for M4(M4’) and M5(M5’) are denoted by VB_M4
and VB_M5, respectively. Assuming one needs to bias the
drain of M5 to f.Vov, L5x can be obtained using
( )ffLL x 22
55 += , (11)
provided that W4 = W5.
A similar argument can be made for M2(M2’) and M3(M3’)
while accounting for the current and width mismatch between
M2 and M3. This is realized by setting W/L in the replica
device equal to that of M2 (W2/L2). On the other hand, we use
a scaled width for the M3 replica equal to W3x = W3/(1+Id1/Id2).
Moreover, similar to the above analysis, L5x can be determined
using






−++= 1
122
55
xx
f
fLL x , (12)
where x is equal to W2/W3
It remains to mention that a minimum value for f equal to 2.5
was found sufficient to preserve the designed operating point
within an acceptable level of accuracy of about 3~4%. As for
WB and LB sizes, their design is found highly related to
stabilizing the common mode feedback network through the
tail current source, as will be discussed shortly. A thorough
analysis yields WB = 1.3µm and LB = 0.5µm.
C. CMFB Circuit Design
An ideal common mode feedback network is assumed to set
the desired common mode DC output at 0.9 V. It comprises of
an ideal GM element connected at the tail of the input
differential pair producing a negative feedback current, the
latter being proportional to the common mode voltage error.
Analyzing the loop gain for this feedback loop becomes tricky
as it involves an additional internal loop formed by Cf.
To simplify the analysis, Cf is initially ignored and half
circuit analysis is considered. The loop gain can be found to
equal
totLmxm
MCMFB
CsRgsCgsC
RGT
,0211
0
1
1
/1
1
/1
1
+++
≅ , (13)
where R0 is the output resistance at the OTA half circuit output
and C1 = Css1 + 0.5Cdd_N, Cdd_N being the equivalent
capacitance seen at the drain of the tail current source. To
ensure stability, 111 /Cgm=ω is set to be ~ xω3 to shoot for
a 70° phase margin. The latter condition sets a constraint on
the device size of the tail current source and consequently on
the maximum mirror ratio R discussed earlier.
The above step is followed by more accurate loop gain
simulations to account for the effect of Cf. While the measured
phase margin is smaller than predicted, it can be restored by
slightly reducing the unity cross over frequency. This can be
achieved by lowering GM as R0 is sufficiently large.
D. Design Optimization
Having discussed the initial guesses achieved together with
the major design knobs and tradeoffs, the design equations
were implemented in a Matlab script and thereby iterated
while meeting a set of design specs summarized below in
Table IV.
TABLE IV
SUMMARY FOR INITIAL GUESS DEVICE PARAMETERS
Parameter Specification
Supply Voltage 1.8V
Fig. 6 Magic batteries used to bias the OTA circuitry.
Fig. 5 Magic battery with single mirroring configuration.

Temperature 27°C
Corner Frequency fedge 20 MHz
Tolerable Passband error (up to 0.9fedge) +/- 1dB
Stopband Attenuation at 1.3fedge > 35 dB
HD3 (for fin=3fs/128 < -60 dB
Dynamic Range > 54 dB
OTA Dynamic Settling Error < 0.1%
OTA Power Consumption Minimum
The optimization procedure is targeted at minimizing the
bias current Id1 by primarily reducing the value of k while
respecting a minimum dynamic range of 54dB. To ensure the
latter spec is not severely violated during iterations, a pilot
pnoise simulation was performed where the OTA noise was
observed to degrade the dynamic range by ~2dB. Using this
result as a rough guideline, the corresponding OTA total
integrated noise is set as a reference and is used to quickly
estimate dynamic range violations.
As for the settling performance, we start by considering
small signal excitations to ensure simplicity and develop clear
correlations between the design script and simulations. As
discussed later in Section VI, this strategy has helped refine
the testbench setup to closely mimic a key limiting effect
occurring within the filter top level circuit. This testbench is
subsequently reused to examine the OTA slewing. After a few
iterations, it was concluded that setting should not be
regarded as an exaggerated overdesign choice given that the
OTA is examined to slew about 30% of the total settling time.
Finally, we conduct a few global iterations before
minimizing Id1 down to 220.4 µA while Id2 is kept larger by
20% (= 264.5 µA) to avoid asymmetric slewing. Under this
condition, devices M[1-5] are ensured to operate for maximum
power efficiency (gm/Id ~ 15) while maximizing the output
signal swing. The common scaling factor for capacitors in the
circuit is equal to 0.03. Moreover, to reduce the power
consumption by the biasing network, R is set equal to 9
resulting in a maximum current mirror ratio of 12.7 between
the OTA tail current source and the main reference current.
Fig. 7 shows a schematic capture with annotations for all
device geometries and operating points. The ideal CMFB is
found to consume ~90uA with a GM = 10mS. The overall
power consumption is simulated to equal 2.08mW including
biasing.
Finally, the design is verified to abide by all specs listed in
Table IV. The next section will describe the simulation
testbenches used to assess the design performance together
with the final simulation results for the final optimized design.
VI. SIMULATION TESTBENCHES & RESULTS
A. Common OTA Testbench
A common simulation testbench is built in Cadence as shown
in Fig. 8. In this testbench, ideal baluns are used to
conveniently develop common mode and differential mode
Fig. 7. Final OTA schematic annotated with device geometries and operating conditions.
Fig. 8. Common testbench used to simulate the DC, AC and settling
performance of the OTA.

excitation signals onto the input of the OTA. Large resistors
are used to set the OTA input common mode at 0.9 V during
operating point calculation. Moreover, to set the OTA output
common mode, an ideal common mode feedback is used and
comprises of a simple voltage controlled current source that
minimizes the feedback error between the output common
mode and the desired level of 0.9 V. Finally, to enable loop
gain simulations, a probe is carefully inserted at the OTA
output such that it breaks the two major feedback loops in the
setup.
B. OTA DC Gain Simulation
Using the test setup as described before in Fig. 8, a DC
analysis is run while sweeping the differential input voltage Vid
from -250mV to +250mV. The DC differential output Vod is
measured and the DC gain is calculated as the ratio between
Vod and Vid. Fig. 9 shows the final DC simulation results where
the maximum gain is measured to be equal to 204.4 hence
above the minimum gain spec derived earlier (=40.97dB) by
about 5.24dB. When Vod becomes relatively large, the gain
starts to decline. To avoid ill behaviors in the overall filter
response related to insufficient gain, we define the maximum
allowable OTA output Vod_max to correspond to a maximum
loss in gain by 30%. In this case, Vod_max is measured to equal
1.002V.
C. OTA Loop Gain Simulation
A regular AC simulation is next executed to extract the loop
gain around the OTA. While still relying on Fig. 8 test setup,
an AC source is used to excite the differential input terminal
Vid while the input common mode is set at 0.9V. The loop gain
simulation results for the final OTA are presented in Fig. 10.
Based on a targeted β factor equal to 0.34, the simulated loop
gain magnitude To equals 36.83dB conforming within 5%
error relative to hand calculations. In addition, the measured
unity cross over frequency is equal to 313.5 MHz while the
phase margin is equal to 82.7°. These results are again found
to correlate reasonably well (~13%) relative to their
corresponding predicted values from Matlab.
Moreover, the loop gain for the common mode feedback
network is also measured as shown in Fig. 11.These results are
obtained while setting GM = 10 mS.
Fig. 11. Bode plot for common mode feedback loop gain.
Fig. 10. OTA loop gain AC simulation results.
Fig. 9. OTA DC gain simulation. Maximum gain is measured to be equal to
204.4. Maximum Vod_max = 1.002V corresponds to a 30% gain drop below the
maximum gain.
0 dB
313.5 MHz
-97.3°
77.39°
0 dB
734.6 MHz

D. OTA Settling Performance Simulation
To measure the OTA settling performance, the testbench
shown in Fig. 8 was initially used where the differential input
Vid was excited with a small signal step equal to 1mV. At a
later stage, when the overall filter settling performance was
verified, a considerable mismatch (~20%) in the output
behavior was observed relative to the obtained value using the
individual testbench excitation. At this point, the finite
resistance of the switch at the OTA input was closely
investigated. To quantify its impact, the OTA settling test was
repeated while taking the finite switch resistance into account.
The setup was modified accordingly as shown in Fig. 12.
Transient results comparison shows that the filter finite
resistance is considerable where it introduces an additional
delay of ~0.6ns (See Fig. 13). In order to keep close
correlation between the filter top level and the individual OTA
testbenches, the switch resistance has to be included during
OTA settling simulations.
Using the final optimized design parameters, the OTA
settling test is performed and the results are presented in Fig.
14. The small signal test shows that the OTA settles within a
0.1% of dynamic error after 4.13ns. On the other hand, to
include slewing, an input step of 590mV is used to drive the
OTA output to its maximum designed value = 1.002V. In this
case, the OTA needs 4.51ns to settle within the same accuracy
level.
E. Overall Filter Transfer Function & Dynamic Range
Simulations
To assess the overall filter transfer function in presence of
the critical designed OTA, a Spectre PAC analysis is
conducted using a similar setup as appearing in Fig. 1. In this
setup, full transistor level circuitry (including bias network) is
used to represent the critical OTA. Other OTA’s are
represented by a gain element with infinite bandwidth while
the finite gain is set equal to the maximum DC gain previously
obtained as 204.4.
The final simulation results fall well within the dictated
passband and attenuation specs given the excess DC gain. The
top plot in Fig. 15 shows the overall filter response between
the sampled output and the sampled input. At 18 MHz, the
attenuation is measured to be 0.5dB while the stopband
rejection at 26MHz equals -42.4dB. In addition, the sinc
corrected response is also measured between the critical OTA
output and the filter input. A peaking of 0.684dB can be
observed to occur at 19.95MHz. The latter observation can
then be used to calculate the maximum amplitude at the filter
input without driving the critical OTA beyond its desired
maximum output voltage (Vod_max = 1.002V). In this case, the
maximum input voltage level Vin_max is readily obtained as
926mV =-0.667dB.
The above result can also help quantify the minimum
expected dynamic range at the filter output under worst case
Fig. 13. Effect of finite switch resistance on the effective differential input
Vid applied to the OTA (top) and the settling of its differential output Vod
(bottom)..
Fig. 14. Final OTA settling test for small and large excitations. The dashed
curve indicates the 0.1% dynamic error settling spec.
Fig. 12. Settling simulation special setup accounting for the finite resistance
of the input switch.

conditions. Using the same current setup, PNOISE simulation
is run to yield a total integrated output noise level of -55.6dB
(See Fig. 16). Moreover, after considering a maximum
attenuation in the filter passband response of 0.5dB, the
dynamic range at the output can be calculated as
DR = Vin_max (dB) – 0.5dB – (-55.6 dB) = 54.4dB.
F. OTA Settling Performance within Filter
The final verification step is performed using traditional
transient simulation for the entire filter. The setup is similar to
the previous step except that a sinusoidal source is used at the
filter input with the maximum allowed amplitude of 926 mV
and running at 20MHz. The latter choice is intentional to
generate the largest allowed steps the OTA has been designed
to tolerate. Fig. 17 shows a zoomed version of a large settling
step the OTA output undergoes starting at time = 907 ns. At
this instant, the original output level is equal to -375.8 mV
while the final value reaches 747.1 mV. In this case, the OTA
is observed to require 4.7ns before satisfying the 0.1%
dynamic error condition.
To assess linearity, a sinusoidal tone at 3fs/128 is injected at
the filter input with an amplitude corresponding to Vid_max =
926 mV. The corresponding HD3 is measured at the output to
equal -81 dB.
VII. CONCLUSION
This paper has presented a thorough discussion for the
design and optimization of a high performance folded cascode
OTA using 0.18µm CMOS technology. Identified as a critical
block, the OTA is verified to sustain successful operation
when used for the implementation of a high frequency
(SDV/VDSL) fifth order elliptic switched capacitor filter.
Simulation results show the design meets all specs while
consuming 2.08mW from a 1.8V supply voltage.
REFERENCES
[1] J.M Rabaey, F. D. Bernardinis, A. M. Niknejad, B. Nikolic, and . A.
Sangiovanni-Vincentelli, “Embedding mixed-signal design in systems-
on-chip,” Proc. IEEE, Vol. 94, no. 6, pp. 1070-1088, Jun. 2006.
Fig. 16. Filter PNOISE simulation results while including full transistor
circuitry for the critical OTA.
Fig. 15. PAC transfer functions simulation results measured at the filter
output (top) and at the critical OTA output (bottom). Responses are sinc
corrected.
Fig. 17. Settling at the OTA output within a top level transient simulation
for the filter. Phi2 switch is measured to switch at 907ns where the signal
level is at -375.8mV. The dashed line sets the 0.1% dynamic error level.
-0.5dB
18MHz
+0.684dB
19.95MHz

[2] Un-Ku Moon, “CMOS high-frequency switched-capacitor filters for
telecommunication applications,” IEEE J. Solid-State Circuits, Vol. 35,
No. 2, pp. 212-220, Feb. 2000.
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