This document describes the design of an automatic college bell system using an FPGA board. The objectives are to reduce human error and save resources by automating the bell timing based on a real-time clock. It will be programmed using Verilog HDL on a Zed Board FPGA. The design includes a digital clock, buzzer, seven segment displays, and scheduling logic to ring the bell automatically according to a programmed schedule without manual switching. This provides more accurate and efficient automation than a microcontroller-based approach, while FPGAs allow for simpler coding and testing than alternative solutions.

1. By
VAGGU SRIKANTH

2. INTRODUCTION:
 In today’s life, everyone gives importance to time. time
does not wait for anybody.
 Everything should be performed in time & accurately. Now
a day’s school or college bells are manually operated.
 Hence there is a big question of accuracy. Also there is
necessity of manpower and money.
 Hence here we should use automatic control system, which
saves our manpower and money & also gets highest
accuracy. Hence we have selected the project.

3. OBJECTIVE:
 The main objective of this project is to implement Automatic college
bell on a ZED Board/FPGA using Verilog HDL coding.
 the primary objective of designing this project is to reduce the human
intervention for the purpose of manual switching operation of a bell.
 Because of this manual switching we are not sure about the accuracy of
the time.
 So, a system should be designed in such a way that it is exactly
dependent on real time clock and the switching of the bell should be
controlled automatically without human intervention.

4. What is the need of a bell?
 Generally, wherever we may go, it might be a school or an organisation
if start or stop of any process is to be conveyed to a large number of
people, a bell is used over there which signals the start or stop of any
process.
 So, simply a bell is used to give indication about the beginning or
termination of any process.
How is it operated?
 From olden days to till today we are still dependent on manual
switching operation of a bell with the help of a person.

5. Disadvantages of manual switching:
 Accuracy is reduced
 Waste of man power
 Waste of money
Need for automation:
 Increased throughput or productivity
 Improved quality or increased predictability of quality.
 Improved robustness (consistency), of processes or
product.
 Increased consistency of output.
 Reduced direct human labor costs and expenses.

6. EXISTING SYSTEM: (microcontroller based bell system)
 Currently, microcontroller based embedded designs of automatic bells
are readily available in the market.
 It has an Inbuilt Real Time Clock (DS1307 /DS 12c887)which tracks over
the Real Time.
 When this time equals to the Bell Ringing time, then the Relay for the
Bell is switched on. The Bell Ringing time can be edited at any Time, so
that it can be used at Normal Class Timings as well as Exam Times.
DRAWBACKS:
 Circuit complexity is high and even coding is complex.
 development time due to complexity of the circuit,the development
time of a microcontroller increases and cost increases.
 All ringing should be given at a time.
 previous ringing time will be cleared from the memory.

7. FPGA IMPLEMENTATION OF AUTOMATIC BELL SYSTEM:
 This method eliminates some of disadvantages which occured in
microcontroller based design.
 In this design programming is done in xilinx vivado through verilog
coding and then after, the written code is dumped on to the FPGA kit
and then the result is verified practically.
 easy to design when compared to a microcontroller based design.

8. BLOCK DIAGRAM:

9. COMPONENTS INVOLVED IN THIS DESIGN:
 PC
 xilinx vivado IDE 2014.2 licensed software.
 Zed board or FPGA kit.
 Buzzer or bell.
 Power supply.
 PCB.
 Seven segment LED’s.
 IC 7447 DECODER.
 Female ports and jumper wires.

10. SEVEN SEGMENT DISPLAY AND BUZZER INTERFACED TO ZED BOARD :

11. FUNCTIONING PROCESS:
 Create a new project in vivado and then write the code for the design to
be implemented
 As the bell is dependent on real time clock for its functioning as per the
given schedule, firstly, we have to design a digital clock to implement
the functioning of the bell.
 Based upon the digital clock ,a schedule is assigned in the code itself
for the bell to ring at some regular intervals of time without human
intervention.
 After the code is written, check for errors and then simulate it to
observe the waveforms theoritically.
 For practical verification purpose, generate a bit-stream file and then
after dump the code onto the FPGA kit to verify the functioning of the
bell as per the given logic in the code.

12. ADVANTAGES:
 Accuracy is more when compared to a microcontroller based design
 Efficiency is high
 Coding is less complex
 Circuit complexity is less
 Automatic scheduling of bell is possible in the code itself directly.
LIMITATIONS OF FPGA :
 Cost is very high when compared to a microcontroller based design.
 Need for internal memory
 Faster FPGAs : limited by reconfiguration switches

13. APPLICATIONS:
 Can be used in schools or colleges or any other organizations
 Washing machines
 Microwave ovens
 Video recorders
 Security systems
 Digital watches.

14. CONCLUSION:
 So, a VLSI based design is more efficient and accurate when compared to a
embedded system based design.
 Any other complex designs of embedded systems can be developed
through VLSI technology with less complexity.
 Even though FPGA based bell system has some limitations, but it is able to
eliminate some of the drawbacks arised in microcontroller based design.
 Generally, this FPGA based design is recommended only when the
application level which we need to design is of wider range.
 As the application here we are trying to design is a small one, FPGA based
system is not recommended for practical implementation in this case.
 But, for testing of the design upto simulation level FPGA is preferred over
microcontroller based design.
 So, for practical verification of any digital design through verilog/VHDL
coding, FPGA is the best option for testing of the design upto simulation
level before going for practical implementation.

15. THANK YOU